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([5.14.146.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4247d208b60sm174127905e9.37.2024.06.24.05.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 05:50:13 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v6 2/6] dt-bindings: iio: adc: ad7192: Update clock config Date: Mon, 24 Jun 2024 15:49:37 +0300 Message-Id: <20240624124941.113010-3-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624124941.113010-1-alisa.roman@analog.com> References: <20240624124941.113010-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are actually 4 configuration modes of clock source for AD719X devices. Either a crystal can be attached externally between MCLK1 and MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 pin. The other 2 modes make use of the 4.92MHz internal clock. To configure external clock as either a crystal or a CMOS-compatible clock, changing the register settings is necessary. Therefore, add clock name xtal alongside mclk. By selecting one or the other, the register is configured. The presence of an external clock source is optional, not required. When both clocks and clock-names properties are present, an external clock source is used. If the intention is to use the internal clock, both properties should be absent. Modify required properties accordingly. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Conor Dooley --- .../bindings/iio/adc/adi,ad7192.yaml | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index a03da9489ed9..c3adc32684cf 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -39,11 +39,15 @@ properties: =20 clocks: maxItems: 1 - description: phandle to the master clock (mclk) + description: + Optionally, either a crystal can be attached externally between MCLK= 1 and + MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2 + pin. If absent, internal 4.92MHz clock is used. =20 clock-names: - items: - - const: mclk + enum: + - xtal + - mclk =20 interrupts: maxItems: 1 @@ -135,8 +139,6 @@ patternProperties: required: - compatible - reg - - clocks - - clock-names - interrupts - dvdd-supply - avdd-supply @@ -157,6 +159,16 @@ allOf: then: patternProperties: "^channel@[0-9a-f]+$": false + - if: + anyOf: + - required: + - clocks + - required: + - clock-names + then: + required: + - clocks + - clock-names =20 unevaluatedProperties: false =20 --=20 2.34.1