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Here is a failed example on ASUS B1400CEAE: Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Sub= states+ PortCommonModeRestoreTime=3D32us PortTPowerOnTime=3D10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D0us LTR1.2_Threshold=3D0ns L1SubCtl2: T_PwrOn=3D10us Power on all of the VMD remapped PCI devices to D0 before enable PCI-PM L1 PM Substates by following "PCIe r6.0, sec 5.5.4". Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D218394 Signed-off-by: Jian-Hong Pan Reviewed-by: Kuppuswamy Sathyanarayanan --- v2: - Power on the VMD remapped devices with pci_set_power_state_locked() - Prepare the PCIe LTR parameters before enable L1 Substates - Add note into the comments of both pci_enable_link_state() and pci_enable_link_state_locked() for kernel-doc. - The original patch set can be split as individual patches. v3: - Re-send for the missed version information. - Split drivers/pci/pcie/aspm.c modification into following patches. - Fix the comment for enasuring the PCI devices in D0. v4: - The same v5: - Tweak the commit title and message - Change the goto label from out_enable_link_state to out_state_change v6: - The same drivers/pci/controller/vmd.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 87b7856f375a..5309afbe31f9 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -751,11 +751,9 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, v= oid *userdata) if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) return 0; =20 - pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); - pos =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); if (!pos) - return 0; + goto out_state_change; =20 /* * Skip if the max snoop LTR is non-zero, indicating BIOS has set it @@ -763,7 +761,7 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, vo= id *userdata) */ pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg); if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) - return 0; + goto out_state_change; =20 /* * Set the default values to the maximum required by the platform to @@ -775,6 +773,13 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, v= oid *userdata) pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg); pci_info(pdev, "VMD: Default LTR value set by driver\n"); =20 +out_state_change: + /* + * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + */ + pci_set_power_state_locked(pdev, PCI_D0); + pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); 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charset="utf-8" According to "PCIe r6.0, sec 5.5.4", add note about D0 requirement in pci_enable_link_state() kernel-doc. Signed-off-by: Jian-Hong Pan Acked-by: Bjorn Helgaas Reviewed-by: Kuppuswamy Sathyanarayanan --- v3: - Fix as readable comments v4: - The same v5: - Tweak and simplify the commit message v6: - The same drivers/pci/pcie/aspm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index cee2365e54b8..bd0a8a05647e 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -1442,6 +1442,9 @@ static int __pci_enable_link_state(struct pci_dev *pd= ev, int state, bool locked) * touch the LNKCTL register. Also note that this does not enable states * disabled by pci_disable_link_state(). Return 0 or a negative errno. * + * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, = per + * PCIe r6.0, sec 5.5.4. + * * @pdev: PCI device * @state: Mask of ASPM link states to enable */ @@ -1458,6 +1461,9 @@ EXPORT_SYMBOL(pci_enable_link_state); * can't touch the LNKCTL register. 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Mon, 24 Jun 2024 01:22:48 -0700 (PDT) From: Jian-Hong Pan To: Bjorn Helgaas Cc: Francisco Munoz , Johan Hovold , David Box , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Kuppuswamy Sathyanarayanan , Mika Westerberg , Damien Le Moal , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH v6 3/3] PCI: vmd: Drop resetting PCI bus action after scan mapped PCI child bus Date: Mon, 24 Jun 2024 16:21:45 +0800 Message-ID: <20240624082144.10265-2-jhp@endlessos.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240624081108.10143-2-jhp@endlessos.org> References: <20240624081108.10143-2-jhp@endlessos.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to "PCIe r6.0, sec 5.5.4", before enabling ASPM L1.2 on the PCIe Root Port and the child device, they should be programmed with the same LTR1.2_Threshold value. However, they have different values on VMD mapped PCI child bus. For example, Asus B1400CEAE's VMD mapped PCI bridge and NVMe SSD controller have different LTR1.2_Threshold values: 10000:e0:06.0 PCI bridge: Intel Corporation 11th Gen Core Processor PCIe Co= ntroller (rev 01) (prog-if 00 [Normal decode]) ... Capabilities: [200 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Sub= states+ PortCommonModeRestoreTime=3D45us PortTPowerOnTime=3D50us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D45us LTR1.2_Threshold=3D101376ns L1SubCtl2: T_PwrOn=3D50us 10000:e1:00.0 Non-Volatile memory controller: Sandisk Corp WD Blue SN550 NV= Me SSD (rev 01) (prog-if 02 [NVM Express]) ... Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Sub= states+ PortCommonModeRestoreTime=3D32us PortTPowerOnTime=3D10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D0us LTR1.2_Threshold=3D0ns L1SubCtl2: T_PwrOn=3D10us After debug in detail, both of the VMD mapped PCI bridge and the NVMe SSD controller have been configured properly with the same LTR1.2_Threshold value. But, become misconfigured after reset the VMD mapped PCI bus which is introduced from commit 0a584655ef89 ("PCI: vmd: Fix secondary bus reset for Intel bridges") and commit 6aab5622296b ("PCI: vmd: Clean up domain before enumeration"). So, drop the resetting PCI bus action after scan VMD mapped PCI child bus. Signed-off-by: Jian-Hong Pan --- v6: - Introduced based on the discussion https://lore.kernel.org/linux-pci/CAPp= J_efYWWxGBopbSQHB=3DY2+1RrXFR2XWeqEhGTgdiw3XX0Jmw@mail.gmail.com/=20 drivers/pci/controller/vmd.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 5309afbe31f9..af413cdb4f4e 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -793,7 +793,6 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsig= ned long features) resource_size_t offset[2] =3D {0}; resource_size_t membar2_offset =3D 0x2000; struct pci_bus *child; - struct pci_dev *dev; int ret; =20 /* @@ -935,25 +934,6 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsi= gned long features) pci_scan_child_bus(vmd->bus); vmd_domain_reset(vmd); =20 - /* When Intel VMD is enabled, the OS does not discover the Root Ports - * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies - * a reset to the parent of the PCI device supplied as argument. This - * is why we pass a child device, so the reset can be triggered at - * the Intel bridge level and propagated to all the children in the - * hierarchy. - */ - list_for_each_entry(child, &vmd->bus->children, node) { - if (!list_empty(&child->devices)) { - dev =3D list_first_entry(&child->devices, - struct pci_dev, bus_list); - ret =3D pci_reset_bus(dev); - if (ret) - pci_warn(dev, "can't reset device: %d\n", ret); - - break; - } - } - pci_assign_unassigned_bus_resources(vmd->bus); =20 pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features); --=20 2.45.2