From nobody Sun Feb 8 08:31:02 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F32E3181B96; Sun, 23 Jun 2024 13:35:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719149703; cv=none; b=QD84Lqn/lw6gzUYl0WzFTA7gqHFivPEXpn6CIbr+s3hyKzCCr2WxFWYjZnEzBpuyo1bj2uMhxoQQegJ98dn5ya+Hn1VLwI3hY37bAbko6mb3zxC4HwkM2+ckYt4ZH8xAQDAS74YJ8B5/8KvtGMZsGAIurmdzRPvrF6DhdoWoeV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719149703; c=relaxed/simple; bh=qyqBA4nAmJd8XITMyxqAL9q0T8AwJp01B2uqQrhwkEo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LB51Xs1dQxirXMxr8TlMQu1V35GBJZOy1eX87teoQUbFPKdVjqjKFfZ/2SXBgupAkaycNNk/FGCl4N57E0dL6CRN987rv6z5sScqxq5h1biY/bfhv5yrPplgebwbLmkk2Plii0C/JxVJGCbuQ67gHcOcp+qPdfKuChCmr0wBLrs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 49315FEC; Sun, 23 Jun 2024 06:35:20 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 847F63F64C; Sun, 23 Jun 2024 06:34:52 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , James Clark , Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Ian Rogers , Mark Rutland , Alexander Shishkin , Adrian Hunter , "Liang, Kan" , Kajol Jain , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 1/2] perf arm-spe: Support multiple Arm SPE PMUs Date: Sun, 23 Jun 2024 14:34:36 +0100 Message-Id: <20240623133437.222736-2-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240623133437.222736-1-leo.yan@arm.com> References: <20240623133437.222736-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A platform can have more than one Arm SPE PMU. For example, a system with multiple clusters may have each cluster enabled with its own Arm SPE instance. In such case, the PMU devices will be named 'arm_spe_0', 'arm_spe_1', and so on. Currently, the tool only supports 'arm_spe_0'. This commit extends support to multiple Arm SPE PMUs by detecting the substring 'arm_spe'. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/arch/arm/util/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c index 8b7cb68ba1a8..29cfa1e427ed 100644 --- a/tools/perf/arch/arm/util/pmu.c +++ b/tools/perf/arch/arm/util/pmu.c @@ -27,7 +27,7 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unu= sed) pmu->selectable =3D true; pmu->is_uncore =3D false; pmu->perf_event_attr_init_default =3D arm_spe_pmu_default_config; - if (!strcmp(pmu->name, "arm_spe_0")) + if (strstr(pmu->name, "arm_spe")) pmu->mem_events =3D perf_mem_events_arm; } else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) { pmu->selectable =3D true; --=20 2.34.1 From nobody Sun Feb 8 08:31:02 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8CBE6180A94; Sun, 23 Jun 2024 13:34:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719149701; cv=none; b=ah3rrN/7HkB9FI0sLOm+ql440pAerbmlcTe0Lv5E0UGOtRexwZDlgQWGj0YeW8e4RERs3S2hHnI9b+Ly2KeeACYhkUYOv27t3SE5W0QGY2UbuwuHETXazE0pvsRaCBzSvgsfXFLM48/nPZ9NlClMYji21M7NgFbMWScNDeuShdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719149701; c=relaxed/simple; bh=Ac43lwqqsumZqlDVKpvPeyfLvA/qgugt7tJ1HelShso=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HhqtENAEruexj8gStweDDSR+CV5F7gtbIdYMEs9pRaaLkTpjRAAxNOwo+TAz0eTHhEREUR74XAAZuyukngDbz6rQTjuH3dIbMIZsGU/I7IVub7GuHjIOKSNS7OKV0YeRcXle6Qo+9nRbr5SLw1AGqW4SgGxdCIH3Ff8e28jphxY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 815E6168F; Sun, 23 Jun 2024 06:35:23 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C1AB93F64C; Sun, 23 Jun 2024 06:34:55 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , James Clark , Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Ian Rogers , Mark Rutland , Alexander Shishkin , Adrian Hunter , "Liang, Kan" , Kajol Jain , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 2/2] perf mem: Warn if memory events are not supported on all CPUs Date: Sun, 23 Jun 2024 14:34:37 +0100 Message-Id: <20240623133437.222736-3-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240623133437.222736-1-leo.yan@arm.com> References: <20240623133437.222736-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is possible that memory events are not supported on all CPUs. Prints a warning by dumping the enabled CPU maps in this case. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/mem-events.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 6dda47bb774f..8aff2ca8bbd5 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -8,6 +8,7 @@ #include #include #include +#include "cpumap.h" #include "map_symbol.h" #include "mem-events.h" #include "mem-info.h" @@ -242,6 +243,7 @@ int perf_mem_events__record_args(const char **rec_argv,= int *argv_nr) int i =3D *argv_nr; const char *s; char *copy; + struct perf_cpu_map *cpu_map =3D NULL; =20 while ((pmu =3D perf_pmus__scan_mem(pmu)) !=3D NULL) { for (int j =3D 0; j < PERF_MEM_EVENTS__MAX; j++) { @@ -266,7 +268,19 @@ int perf_mem_events__record_args(const char **rec_argv= , int *argv_nr) =20 rec_argv[i++] =3D "-e"; rec_argv[i++] =3D copy; + + cpu_map =3D perf_cpu_map__merge(cpu_map, pmu->cpus); + } + } + + if (cpu_map) { + if (!perf_cpu_map__equal(cpu_map, cpu_map__online())) { + char buf[200]; + + cpu_map__snprint(cpu_map, buf, sizeof(buf)); + pr_warning("Memory events are enabled on a subset of CPUs: %s\n", buf); } + perf_cpu_map__put(cpu_map); } =20 *argv_nr =3D i; --=20 2.34.1