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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-th1520-clk-v2-7-ad8d6432d9fb@tenstorrent.com> References: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> In-Reply-To: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719195343; l=1705; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=1YUFcjPStRQXnRCkm7LFCYqYtH2keuIc2Ndi6ymcweU=; b=rYBGKNJzXmCmLAga5clXqSFTTT6acEgLUJTAcP100RcfUjqlXe3oY4DKYzEONUhMhRslOqumq IBxq129anadAhKP9VsQmsnBjrF17brGOw1fgRg6bSOgGM2pr+vivXcb X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Add clock property to TH1520 gpio controller nodes. These clock gates refer to corresponding enable bits in the peripheral clock gate control register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the TH1520 System User Manual. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index d05002ad7c96..351e09beab70 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -237,6 +237,7 @@ gpio2: gpio@ffe7f34000 { reg =3D <0xff 0xe7f34000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO2>; =20 portc: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -255,6 +256,7 @@ gpio3: gpio@ffe7f38000 { reg =3D <0xff 0xe7f38000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO3>; =20 portd: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -273,6 +275,7 @@ gpio0: gpio@ffec005000 { reg =3D <0xff 0xec005000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO0>; =20 porta: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -291,6 +294,7 @@ gpio1: gpio@ffec006000 { reg =3D <0xff 0xec006000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO1>; =20 portb: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; --=20 2.34.1