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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-th1520-clk-v2-6-ad8d6432d9fb@tenstorrent.com> References: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> In-Reply-To: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719195343; l=4851; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=CJyRU2euk+h8MQ3uF4akWb8lHgrUYTVPRvEJzPNHbOU=; b=mNsn8JF4kFtRIlgga/Xmq9+3MshgDGyu9OUR6HpWzEdWNOwPQV05o7B8GmUXs3Dk7ZQ2mNxJi 2BPyOgkY7t/CJRA4WBk2A5H8jQn9JkuBsh1SoYfj6/gWb5uq9Mn+hF0 X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the dma-controller and timer nodes to use the APB clock provided by the AP_SUBSYS clock controller. Remove apb_clk reference from BeagleV Ahead and LPI4a dts. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++----------= ---- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 55f1ed0cb433..1180e41c7b07 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -44,10 +44,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 762eceb415f8..78977bdbbe3d 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,10 +25,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index ce3a0847aa9c..d05002ad7c96 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -135,12 +135,6 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 - apb_clk: apb-clk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "apb_clk"; - #clock-cells =3D <0>; - }; - soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -325,7 +319,7 @@ dmac0: dma-controller@ffefc00000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0xff 0xefc00000 0x0 0x1000>; interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&apb_clk>, <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; dma-channels =3D <4>; @@ -340,7 +334,7 @@ dmac0: dma-controller@ffefc00000 { timer0: timer@ffefc32000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -349,7 +343,7 @@ timer0: timer@ffefc32000 { timer1: timer@ffefc32014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -358,7 +352,7 @@ timer1: timer@ffefc32014 { timer2: timer@ffefc32028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -367,7 +361,7 @@ timer2: timer@ffefc32028 { timer3: timer@ffefc3203c { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc3203c 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -398,7 +392,7 @@ uart5: serial@fff7f0c000 { timer4: timer@ffffc33000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -407,7 +401,7 @@ timer4: timer@ffffc33000 { timer5: timer@ffffc33014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -416,7 +410,7 @@ timer5: timer@ffffc33014 { timer6: timer@ffffc33028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -425,7 +419,7 @@ timer6: timer@ffffc33028 { timer7: timer@ffffc3303c { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc3303c 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; --=20 2.34.1