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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-th1520-clk-v2-1-ad8d6432d9fb@tenstorrent.com> References: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> In-Reply-To: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719195343; l=5553; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=N5edY6UhoTVg/tv2RPnMUCdUcddT79O4AMJWRMmP6w4=; b=K5JM6awYX+m3HA/VKe8t3EXTys9lTO5SMbn8NZDPKyNOxOr5TJorhjl2A/xe1d9ez4s77yLot 758n+ENvO61AfgRRtXF1o7wuAk/GO5WdAlXi2JbCbF4Cg53ceetVzDD X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Document bindings for the T-Head TH1520 AP sub-system clock controller. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T= H1520%20System%20User%20Manual.pdf Co-developed-by: Yangtao Li Signed-off-by: Yangtao Li Reviewed-by: Conor Dooley Signed-off-by: Drew Fustini --- .../bindings/clock/thead,th1520-clk-ap.yaml | 53 ++++++++++++ MAINTAINERS | 2 + include/dt-bindings/clock/thead,th1520-clk-ap.h | 96 ++++++++++++++++++= ++++ 3 files changed, 151 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.ya= ml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml new file mode 100644 index 000000000000..0129bd0ba4b3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 AP sub-system clock controller + +description: | + The T-HEAD TH1520 AP sub-system clock controller configures the + CPU, DPU, GMAC and TEE PLLs. + + SoC reference manual + https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH15= 20%20System%20User%20Manual.pdf + +maintainers: + - Jisheng Zhang + - Wei Fu + - Drew Fustini + +properties: + compatible: + const: thead,th1520-clk-ap + + reg: + maxItems: 1 + + clocks: + items: + - description: main oscillator (24MHz) + + "#clock-cells": + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + clock-controller@ef010000 { + compatible =3D "thead,th1520-clk-ap"; + reg =3D <0xef010000 0x1000>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index aacccb376c28..761fcbddc8d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19320,7 +19320,9 @@ M: Guo Ren M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained +F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: arch/riscv/boot/dts/thead/ +F: include/dt-bindings/clock/thead,th1520-clk-ap.h =20 RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-b= indings/clock/thead,th1520-clk-ap.h new file mode 100644 index 000000000000..a199784b3512 --- /dev/null +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + */ + +#ifndef _DT_BINDINGS_CLK_TH1520_H_ +#define _DT_BINDINGS_CLK_TH1520_H_ + +#define CLK_CPU_PLL0 0 +#define CLK_CPU_PLL1 1 +#define CLK_GMAC_PLL 2 +#define CLK_VIDEO_PLL 3 +#define CLK_DPU0_PLL 4 +#define CLK_DPU1_PLL 5 +#define CLK_TEE_PLL 6 +#define CLK_C910_I0 7 +#define CLK_C910 8 +#define CLK_BROM 9 +#define CLK_BMU 10 +#define CLK_AHB2_CPUSYS_HCLK 11 +#define CLK_APB3_CPUSYS_PCLK 12 +#define CLK_AXI4_CPUSYS2_ACLK 13 +#define CLK_AON2CPU_A2X 14 +#define CLK_X2X_CPUSYS 15 +#define CLK_AXI_ACLK 16 +#define CLK_CPU2AON_X2H 17 +#define CLK_PERI_AHB_HCLK 18 +#define CLK_CPU2PERI_X2H 19 +#define CLK_PERI_APB_PCLK 20 +#define CLK_PERI2APB_PCLK 21 +#define CLK_PERISYS_APB1_HCLK 22 +#define CLK_PERISYS_APB2_HCLK 23 +#define CLK_PERISYS_APB3_HCLK 24 +#define CLK_PERISYS_APB4_HCLK 25 +#define CLK_OSC12M 26 +#define CLK_OUT1 27 +#define CLK_OUT2 28 +#define CLK_OUT3 29 +#define CLK_OUT4 30 +#define CLK_APB_PCLK 31 +#define CLK_NPU 32 +#define CLK_NPU_AXI 33 +#define CLK_VI 34 +#define CLK_VI_AHB 35 +#define CLK_VO_AXI 36 +#define CLK_VP_APB 37 +#define CLK_VP_AXI 38 +#define CLK_CPU2VP 39 +#define CLK_VENC 40 +#define CLK_DPU0 41 +#define CLK_DPU1 42 +#define CLK_EMMC_SDIO 43 +#define CLK_GMAC1 44 +#define CLK_PADCTRL1 45 +#define CLK_DSMART 46 +#define CLK_PADCTRL0 47 +#define CLK_GMAC_AXI 48 +#define CLK_GPIO3 49 +#define CLK_GMAC0 50 +#define CLK_PWM 51 +#define CLK_QSPI0 52 +#define CLK_QSPI1 53 +#define CLK_SPI 54 +#define CLK_UART0_PCLK 55 +#define CLK_UART1_PCLK 56 +#define CLK_UART2_PCLK 57 +#define CLK_UART3_PCLK 58 +#define CLK_UART4_PCLK 59 +#define CLK_UART5_PCLK 60 +#define CLK_GPIO0 61 +#define CLK_GPIO1 62 +#define CLK_GPIO2 63 +#define CLK_I2C0 64 +#define CLK_I2C1 65 +#define CLK_I2C2 66 +#define CLK_I2C3 67 +#define CLK_I2C4 68 +#define CLK_I2C5 69 +#define CLK_SPINLOCK 70 +#define CLK_DMA 71 +#define CLK_MBOX0 72 +#define CLK_MBOX1 73 +#define CLK_MBOX2 74 +#define CLK_MBOX3 75 +#define CLK_WDT0 76 +#define CLK_WDT1 77 +#define CLK_TIMER0 78 +#define CLK_TIMER1 79 +#define CLK_SRAM0 80 +#define CLK_SRAM1 81 +#define CLK_SRAM2 82 +#define CLK_SRAM3 83 +#define CLK_PLL_GMAC_100M 84 +#define CLK_UART_SCLK 85 +#endif --=20 2.34.1 From nobody Tue Dec 16 19:23:26 2025 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22EFF4A31 for ; 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a=ed25519-sha256; t=1719195343; l=33677; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=Z+q7WWDSzisg09yDPO+uFWTuzbwdF6n7jJ/+dv6ctVc=; b=O4oFeA/z/SkkMxJOkKSkzceMvlWAspJLHJJI9+PsCGdymfpoxxtL2mb+zAMyHc/5PpeuWv0Cc ZqA/II66DwvAb88k0LSgvEBebXVhOcFcYH5EhM82ml6thiKbQ/2hyCM X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Add support for the AP sub-system clock controller in the T-Head TH1520. This include CPU, DPU, GMAC and TEE PLLs. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T= H1520%20System%20User%20Manual.pdf Co-developed-by: Yangtao Li Signed-off-by: Yangtao Li Co-developed-by: Jisheng Zhang Signed-off-by: Jisheng Zhang Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/thead/Kconfig | 12 + drivers/clk/thead/Makefile | 2 + drivers/clk/thead/clk-th1520-ap.c | 1086 +++++++++++++++++++++++++++++++++= ++++ 6 files changed, 1103 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 761fcbddc8d6..75880648dd14 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19322,6 +19322,7 @@ L: linux-riscv@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: arch/riscv/boot/dts/thead/ +F: drivers/clk/thead/clk-th1520-ap.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h =20 RNBD BLOCK DRIVERS diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3e9099504fad..d73ae04e427a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -495,6 +495,7 @@ source "drivers/clk/starfive/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sunxi-ng/Kconfig" source "drivers/clk/tegra/Kconfig" +source "drivers/clk/thead/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 4abe16c8ccdf..f793a16cad40 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -127,6 +127,7 @@ obj-y +=3D starfive/ obj-$(CONFIG_ARCH_SUNXI) +=3D sunxi/ obj-y +=3D sunxi-ng/ obj-$(CONFIG_ARCH_TEGRA) +=3D tegra/ +obj-$(CONFIG_ARCH_THEAD) +=3D thead/ obj-y +=3D ti/ obj-$(CONFIG_CLK_UNIPHIER) +=3D uniphier/ obj-$(CONFIG_ARCH_U8500) +=3D ux500/ diff --git a/drivers/clk/thead/Kconfig b/drivers/clk/thead/Kconfig new file mode 100644 index 000000000000..1710d50bf9d4 --- /dev/null +++ b/drivers/clk/thead/Kconfig @@ -0,0 +1,12 @@ +#SPDX-License-Identifier: GPL-2.0 + +config CLK_THEAD_TH1520_AP + bool "T-HEAD TH1520 AP clock support" + depends on ARCH_THEAD || COMPILE_TEST + default ARCH_THEAD + select REGMAP_MMIO + help + Say yes here to support the AP sub system clock controller + on the T-HEAD TH1520 SoC. This includes configuration of + both CPU PLLs, both DPU PLLs as well as the GMAC, VIDEO, + and TEE PLLs. diff --git a/drivers/clk/thead/Makefile b/drivers/clk/thead/Makefile new file mode 100644 index 000000000000..7ee0bec1f251 --- /dev/null +++ b/drivers/clk/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CLK_THEAD_TH1520_AP) +=3D clk-th1520-ap.o diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c new file mode 100644 index 000000000000..982d4d40f783 --- /dev/null +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -0,0 +1,1086 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TH1520_PLL_POSTDIV2 GENMASK(26, 24) +#define TH1520_PLL_POSTDIV1 GENMASK(22, 20) +#define TH1520_PLL_FBDIV GENMASK(19, 8) +#define TH1520_PLL_REFDIV GENMASK(5, 0) +#define TH1520_PLL_BYPASS BIT(30) +#define TH1520_PLL_DSMPD BIT(24) +#define TH1520_PLL_FRAC GENMASK(23, 0) +#define TH1520_PLL_FRAC_BITS 24 + +struct ccu_internal { + u8 shift; + u8 width; +}; + +struct ccu_div_internal { + u8 shift; + u8 width; + u32 flags; +}; + +struct ccu_common { + int clkid; + struct regmap *map; + u16 cfg0; + u16 cfg1; + struct clk_hw hw; +}; + +struct ccu_mux { + struct ccu_internal mux; + struct ccu_common common; +}; + +struct ccu_gate { + u32 enable; + struct ccu_common common; +}; + +struct ccu_div { + u32 enable; + struct ccu_div_internal div; + struct ccu_internal mux; + struct ccu_common common; +}; + +struct ccu_pll { + struct ccu_common common; +}; + +#define TH_CCU_ARG(_shift, _width) \ + { \ + .shift =3D _shift, \ + .width =3D _width, \ + } + +#define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ + { \ + .shift =3D _shift, \ + .width =3D _width, \ + .flags =3D _flags, \ + } + +#define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ + struct ccu_gate _struct =3D { \ + .enable =3D _gate, \ + .common =3D { \ + .clkid =3D _clkid, \ + .cfg0 =3D _reg, \ + .hw.init =3D CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parent, \ + &clk_gate_ops, \ + _flags), \ + } \ + } + +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) +{ + return container_of(hw, struct ccu_common, hw); +} + +static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mux, common); +} + +static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_pll, common); +} + +static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_div, common); +} + +static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_gate, common); +} + +static u8 ccu_get_parent_helper(struct ccu_common *common, + struct ccu_internal *mux) +{ + unsigned int val; + u8 parent; + + regmap_read(common->map, common->cfg0, &val); + parent =3D val >> mux->shift; + parent &=3D GENMASK(mux->width - 1, 0); + + return parent; +} + +static int ccu_set_parent_helper(struct ccu_common *common, + struct ccu_internal *mux, + u8 index) +{ + return regmap_update_bits(common->map, common->cfg0, + GENMASK(mux->width - 1, 0) << mux->shift, + index << mux->shift); +} + +static void ccu_disable_helper(struct ccu_common *common, u32 gate) +{ + if (!gate) + return; + regmap_update_bits(common->map, common->cfg0, + gate, ~gate); +} + +static int ccu_enable_helper(struct ccu_common *common, u32 gate) +{ + unsigned int val; + int ret; + + if (!gate) + return 0; + + ret =3D regmap_update_bits(common->map, common->cfg0, gate, gate); + regmap_read(common->map, common->cfg0, &val); + return ret; +} + +static int ccu_is_enabled_helper(struct ccu_common *common, u32 gate) +{ + unsigned int val; + + if (!gate) + return true; + + regmap_read(common->map, common->cfg0, &val); + return val & gate; +} + +static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + unsigned long rate; + unsigned int val; + + regmap_read(cd->common.map, cd->common.cfg0, &val); + val =3D val >> cd->div.shift; + val &=3D GENMASK(cd->div.width - 1, 0); + rate =3D divider_recalc_rate(hw, parent_rate, val, NULL, + cd->div.flags, cd->div.width); + + return rate; +} + +static u8 ccu_div_get_parent(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_get_parent_helper(&cd->common, &cd->mux); +} + +static int ccu_div_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_set_parent_helper(&cd->common, &cd->mux, index); +} + +static void ccu_div_disable(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + ccu_disable_helper(&cd->common, cd->enable); +} + +static int ccu_div_enable(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_enable_helper(&cd->common, cd->enable); +} + +static int ccu_div_is_enabled(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_is_enabled_helper(&cd->common, cd->enable); +} + +static const struct clk_ops ccu_div_ops =3D { + .disable =3D ccu_div_disable, + .enable =3D ccu_div_enable, + .is_enabled =3D ccu_div_is_enabled, + .get_parent =3D ccu_div_get_parent, + .set_parent =3D ccu_div_set_parent, + .recalc_rate =3D ccu_div_recalc_rate, + .determine_rate =3D clk_hw_determine_rate_no_reparent, +}; + +static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + unsigned long div, mul, frac, rate =3D parent_rate; + unsigned int cfg0, cfg1; + + regmap_read(pll->common.map, pll->common.cfg0, &cfg0); + regmap_read(pll->common.map, pll->common.cfg1, &cfg1); + + mul =3D FIELD_GET(TH1520_PLL_FBDIV, cfg0); + div =3D FIELD_GET(TH1520_PLL_REFDIV, cfg0); + if (!(cfg1 & TH1520_PLL_DSMPD)) { + mul <<=3D TH1520_PLL_FRAC_BITS; + frac =3D FIELD_GET(TH1520_PLL_FRAC, cfg1); + mul +=3D frac; + div <<=3D TH1520_PLL_FRAC_BITS; + } + rate =3D parent_rate * mul; + do_div(rate, div); + return rate; +} + +static unsigned long th1520_pll_postdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + unsigned long rate =3D parent_rate; + unsigned int cfg0, cfg1; + + regmap_read(pll->common.map, pll->common.cfg0, &cfg0); + regmap_read(pll->common.map, pll->common.cfg1, &cfg1); + + if (cfg1 & TH1520_PLL_BYPASS) + return rate; + + do_div(rate, FIELD_GET(TH1520_PLL_POSTDIV1, cfg0) * + FIELD_GET(TH1520_PLL_POSTDIV2, cfg0)); + + return rate; +} + +static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long rate =3D parent_rate; + + rate =3D th1520_pll_vco_recalc_rate(hw, rate); + rate =3D th1520_pll_postdiv_recalc_rate(hw, rate); + + return rate; +} + +static const struct clk_ops clk_pll_ops =3D { + .recalc_rate =3D ccu_pll_recalc_rate, +}; + +static const struct clk_parent_data osc_24m_clk[] =3D { + { .index =3D 0 } +}; + +static struct ccu_pll cpu_pll0_clk =3D { + .common =3D { + .clkid =3D CLK_CPU_PLL0, + .cfg0 =3D 0x000, + .cfg1 =3D 0x004, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("cpu-pll0", + osc_24m_clk, + &clk_pll_ops, + 0), + }, +}; + +static struct ccu_pll cpu_pll1_clk =3D { + .common =3D { + .clkid =3D CLK_CPU_PLL1, + .cfg0 =3D 0x010, + .cfg1 =3D 0x014, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("cpu-pll1", + osc_24m_clk, + &clk_pll_ops, + 0), + }, +}; + +static struct ccu_pll gmac_pll_clk =3D { + .common =3D { + .clkid =3D CLK_GMAC_PLL, + .cfg0 =3D 0x020, + .cfg1 =3D 0x024, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("gmac-pll", + osc_24m_clk, + &clk_pll_ops, + 0), + }, +}; + +static const struct clk_hw *gmac_pll_clk_parent[] =3D { + &gmac_pll_clk.common.hw +}; + +static const struct clk_parent_data gmac_pll_clk_pd[] =3D { + { .hw =3D &gmac_pll_clk.common.hw } +}; + +static struct ccu_pll video_pll_clk =3D { + .common =3D { + .clkid =3D CLK_VIDEO_PLL, + .cfg0 =3D 0x030, + .cfg1 =3D 0x034, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("video-pll", + osc_24m_clk, + &clk_pll_ops, + 0), + }, +}; + +static const struct clk_hw *video_pll_clk_parent[] =3D { + &video_pll_clk.common.hw +}; + +static const struct clk_parent_data video_pll_clk_pd[] =3D { + { .hw =3D &video_pll_clk.common.hw } +}; + +static struct ccu_pll dpu0_pll_clk =3D { + .common =3D { + .clkid =3D CLK_DPU0_PLL, + .cfg0 =3D 0x040, + .cfg1 =3D 0x044, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("dpu0-pll", + osc_24m_clk, + &clk_pll_ops, + 0), + }, +}; + +static const struct clk_hw *dpu0_pll_clk_parent[] =3D { + &dpu0_pll_clk.common.hw +}; + +static struct ccu_pll dpu1_pll_clk =3D { + .common =3D { + .clkid =3D CLK_DPU1_PLL, + .cfg0 =3D 0x050, + .cfg1 =3D 0x054, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("dpu1-pll", + osc_24m_clk, + &clk_pll_ops, + 0), + }, +}; + +static const struct clk_hw *dpu1_pll_clk_parent[] =3D { + &dpu1_pll_clk.common.hw +}; + +static struct ccu_pll tee_pll_clk =3D { + .common =3D { + .clkid =3D CLK_TEE_PLL, + .cfg0 =3D 0x060, + .cfg1 =3D 0x064, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("tee-pll", + osc_24m_clk, + &clk_pll_ops, + 0), + }, +}; + +static const struct clk_parent_data c910_i0_parents[] =3D { + { .hw =3D &cpu_pll0_clk.common.hw }, + { .index =3D 0 } +}; + +struct ccu_mux c910_i0_clk =3D { + .mux =3D TH_CCU_ARG(1, 1), + .common =3D { + .clkid =3D CLK_C910_I0, + .cfg0 =3D 0x100, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("c910-i0", + c910_i0_parents, + &clk_mux_ops, + 0), + } +}; + +static const struct clk_parent_data c910_parents[] =3D { + { .hw =3D &c910_i0_clk.common.hw }, + { .hw =3D &cpu_pll1_clk.common.hw } +}; + +struct ccu_mux c910_clk =3D { + .mux =3D TH_CCU_ARG(0, 1), + .common =3D { + .clkid =3D CLK_C910, + .cfg0 =3D 0x100, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("c910", + c910_parents, + &clk_mux_ops, + 0), + } +}; + +static const struct clk_parent_data ahb2_cpusys_parents[] =3D { + { .hw =3D &gmac_pll_clk.common.hw }, + { .index =3D 0 } +}; + +static struct ccu_div ahb2_cpusys_hclk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .clkid =3D CLK_AHB2_CPUSYS_HCLK, + .cfg0 =3D 0x120, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("ahb2-cpusys-hclk", + ahb2_cpusys_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data ahb2_cpusys_hclk_pd[] =3D { + { .hw =3D &ahb2_cpusys_hclk.common.hw } +}; + +static const struct clk_hw *ahb2_cpusys_hclk_parent[] =3D { + &ahb2_cpusys_hclk.common.hw, +}; + +static struct ccu_div apb3_cpusys_pclk =3D { + .div =3D TH_CCU_ARG(0, 3), + .common =3D { + .clkid =3D CLK_APB3_CPUSYS_PCLK, + .cfg0 =3D 0x130, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("apb3-cpusys-pclk", + ahb2_cpusys_hclk_parent, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data apb3_cpusys_pclk_pd[] =3D { + { .hw =3D &apb3_cpusys_pclk.common.hw } +}; + +static struct ccu_div axi4_cpusys2_aclk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_AXI4_CPUSYS2_ACLK, + .cfg0 =3D 0x134, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("axi4-cpusys2-aclk", + gmac_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data axi4_cpusys2_aclk_pd[] =3D { + { .hw =3D &axi4_cpusys2_aclk.common.hw } +}; + +static const struct clk_parent_data axi_parents[] =3D { + { .hw =3D &video_pll_clk.common.hw }, + { .index =3D 0 } +}; + +static struct ccu_div axi_aclk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .clkid =3D CLK_AXI_ACLK, + .cfg0 =3D 0x138, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("axi-aclk", + axi_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data axi_aclk_pd[] =3D { + { .hw =3D &axi_aclk.common.hw } +}; + +static const struct clk_parent_data perisys_ahb_hclk_parents[] =3D { + { .hw =3D &gmac_pll_clk.common.hw }, + { .index =3D 0 }, +}; + +static struct ccu_div perisys_ahb_hclk =3D { + .enable =3D BIT(6), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .clkid =3D CLK_PERI_AHB_HCLK, + .cfg0 =3D 0x140, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("perisys-ahb-hclk", + perisys_ahb_hclk_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data perisys_ahb_hclk_pd[] =3D { + { .hw =3D &perisys_ahb_hclk.common.hw } +}; + +static const struct clk_hw *perisys_ahb_hclk_parent[] =3D { + &perisys_ahb_hclk.common.hw +}; + +static struct ccu_div perisys_apb_pclk =3D { + .div =3D TH_CCU_ARG(0, 3), + .common =3D { + .clkid =3D CLK_PERI_APB_PCLK, + .cfg0 =3D 0x150, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("perisys-apb-pclk", + perisys_ahb_hclk_parent, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data perisys_apb_pclk_pd[] =3D { + { .hw =3D &perisys_apb_pclk.common.hw } +}; + +static struct ccu_div peri2sys_apb_pclk =3D { + .div =3D TH_CCU_DIV_FLAGS(4, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_PERI2APB_PCLK, + .cfg0 =3D 0x150, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("peri2sys-apb-pclk", + gmac_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data peri2sys_apb_pclk_pd[] =3D { + { .hw =3D &peri2sys_apb_pclk.common.hw } +}; + +static CLK_FIXED_FACTOR_FW_NAME(osc12m_clk, "osc_12m", "osc_24m", 2, 1, 0); + +static const char * const out_parents[] =3D { "osc_24m", "osc_12m" }; + +static struct ccu_div out1_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .clkid =3D CLK_OUT1, + .cfg0 =3D 0x1b4, + .hw.init =3D CLK_HW_INIT_PARENTS("out1", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out2_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .clkid =3D CLK_OUT2, + .cfg0 =3D 0x1b8, + .hw.init =3D CLK_HW_INIT_PARENTS("out2", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out3_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .clkid =3D CLK_OUT3, + .cfg0 =3D 0x1bc, + .hw.init =3D CLK_HW_INIT_PARENTS("out3", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out4_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .clkid =3D CLK_OUT4, + .cfg0 =3D 0x1c0, + .hw.init =3D CLK_HW_INIT_PARENTS("out4", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_parent_data apb_parents[] =3D { + { .hw =3D &gmac_pll_clk.common.hw }, + { .index =3D 0 }, +}; + +static struct ccu_div apb_pclk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(7, 1), + .common =3D { + .clkid =3D CLK_APB_PCLK, + .cfg0 =3D 0x1c4, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("apb-pclk", + apb_parents, + &ccu_div_ops, + 0), + }, +}; + +static const struct clk_hw *npu_parents[] =3D { + &gmac_pll_clk.common.hw, + &video_pll_clk.common.hw +}; + +static struct ccu_div npu_clk =3D { + .enable =3D BIT(4), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(6, 1), + .common =3D { + .clkid =3D CLK_NPU, + .cfg0 =3D 0x1c8, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("npu", + npu_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vi_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(16, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_VI, + .cfg0 =3D 0x1d0, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vi", + video_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vi_ahb_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_VI_AHB, + .cfg0 =3D 0x1d0, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vi-ahb", + video_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vo_axi_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_VO_AXI, + .cfg0 =3D 0x1dc, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vo-axi", + video_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vp_apb_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_VP_APB, + .cfg0 =3D 0x1e0, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vp-apb", + gmac_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vp_axi_clk =3D { + .enable =3D BIT(15), + .div =3D TH_CCU_DIV_FLAGS(8, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_VP_AXI, + .cfg0 =3D 0x1e0, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("vp-axi", + video_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div venc_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_VENC, + .cfg0 =3D 0x1e4, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("venc", + gmac_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div dpu0_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_DPU0, + .cfg0 =3D 0x1e8, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("dpu0", + dpu0_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div dpu1_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common =3D { + .clkid =3D CLK_DPU1, + .cfg0 =3D 0x1ec, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("dpu1", + dpu1_pll_clk_parent, + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd, 0x100, BI= T(4), 0); +static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd, 0x100, BIT(= 5), 0); +static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpus= ys2_aclk_pd, + 0x134, BIT(8), 0); +static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2= _aclk_pd, + 0x134, BIT(7), 0); +static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_= pd, 0x138, BIT(8), 0); +static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_c= pusys2_aclk_pd, + 0x140, BIT(9), 0); +static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hc= lk", perisys_ahb_hclk_pd, + 0x150, BIT(9), 0); +static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hc= lk", perisys_ahb_hclk_pd, + 0x150, BIT(10), 0); +static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hc= lk", perisys_ahb_hclk_pd, + 0x150, BIT(11), 0); +static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hc= lk", perisys_ahb_hclk_pd, + 0x150, BIT(12), 0); +static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, B= IT(5), 0); +static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, BIT(= 13), 0); +static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", video_pll_clk_p= d, 0x204, BIT(30), 0); +static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, BIT= (26), 0); +static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_p= d, 0x204, BIT(24), 0); +static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", perisys_apb_pclk_pd, 0x2= 04, BIT(23), 0); +static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", perisys_apb_pclk_p= d, 0x204, BIT(22), 0); +static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", axi4_cpusys2_aclk_= pd, 0x204, BIT(21), 0); +static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", peri2sys_apb_pclk_pd, 0= x204, BIT(20), 0); +static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", gmac_pll_clk_pd, 0x204, BIT= (19), 0); +static CCU_GATE(CLK_PWM, pwm_clk, "pwm", perisys_apb_pclk_pd, 0x204, BIT(1= 8), 0); +static CCU_GATE(CLK_QSPI0, qspi0_clk, "qspi0", video_pll_clk_pd, 0x204, BI= T(17), 0); +static CCU_GATE(CLK_QSPI1, qspi1_clk, "qspi1", video_pll_clk_pd, 0x204, BI= T(16), 0); +static CCU_GATE(CLK_SPI, spi_clk, "spi", video_pll_clk_pd, 0x204, BIT(15),= 0); +static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", perisys_apb_pclk= _pd, 0x204, BIT(14), 0); +static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", perisys_apb_pclk= _pd, 0x204, BIT(13), 0); +static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", perisys_apb_pclk= _pd, 0x204, BIT(12), 0); +static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", perisys_apb_pclk= _pd, 0x204, BIT(11), 0); +static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", perisys_apb_pclk= _pd, 0x204, BIT(10), 0); +static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", perisys_apb_pclk= _pd, 0x204, BIT(9), 0); +static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", perisys_apb_pclk_pd, 0x= 204, BIT(8), 0); +static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", perisys_apb_pclk_pd, 0x= 204, BIT(7), 0); +static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", peri2sys_apb_pclk_pd, 0= x204, BIT(6), 0); +static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", perisys_apb_pclk_pd, 0x204, BI= T(5), 0); +static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", perisys_apb_pclk_pd, 0x204, BI= T(4), 0); +static CCU_GATE(CLK_I2C2, i2c2_clk, "i2c2", perisys_apb_pclk_pd, 0x204, BI= T(3), 0); +static CCU_GATE(CLK_I2C3, i2c3_clk, "i2c3", perisys_apb_pclk_pd, 0x204, BI= T(2), 0); +static CCU_GATE(CLK_I2C4, i2c4_clk, "i2c4", perisys_apb_pclk_pd, 0x204, BI= T(1), 0); +static CCU_GATE(CLK_I2C5, i2c5_clk, "i2c5", perisys_apb_pclk_pd, 0x204, BI= T(0), 0); +static CCU_GATE(CLK_SPINLOCK, spinlock_clk, "spinlock", ahb2_cpusys_hclk_p= d, 0x208, BIT(10), 0); +static CCU_GATE(CLK_DMA, dma_clk, "dma", axi4_cpusys2_aclk_pd, 0x208, BIT(= 8), 0); +static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", apb3_cpusys_pclk_pd, 0x208,= BIT(7), 0); +static CCU_GATE(CLK_MBOX1, mbox1_clk, "mbox1", apb3_cpusys_pclk_pd, 0x208,= BIT(6), 0); +static CCU_GATE(CLK_MBOX2, mbox2_clk, "mbox2", apb3_cpusys_pclk_pd, 0x208,= BIT(5), 0); +static CCU_GATE(CLK_MBOX3, mbox3_clk, "mbox3", apb3_cpusys_pclk_pd, 0x208,= BIT(4), 0); +static CCU_GATE(CLK_WDT0, wdt0_clk, "wdt0", apb3_cpusys_pclk_pd, 0x208, BI= T(3), 0); +static CCU_GATE(CLK_WDT1, wdt1_clk, "wdt1", apb3_cpusys_pclk_pd, 0x208, BI= T(2), 0); +static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", apb3_cpusys_pclk_pd, 0x2= 08, BIT(1), 0); +static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", apb3_cpusys_pclk_pd, 0x2= 08, BIT(0), 0); +static CCU_GATE(CLK_SRAM0, sram0_clk, "sram0", axi_aclk_pd, 0x20c, BIT(4),= 0); +static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_aclk_pd, 0x20c, BIT(3),= 0); +static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2),= 0); +static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1),= 0); + +static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", + &gmac_pll_clk.common.hw, 10, 1, 0); + +static const struct clk_parent_data uart_sclk_parents[] =3D { + { .hw =3D &gmac_pll_clk_100m.hw }, + { .index =3D 0 }, +}; + +struct ccu_mux uart_sclk =3D { + .mux =3D TH_CCU_ARG(0, 1), + .common =3D { + .clkid =3D CLK_UART_SCLK, + .cfg0 =3D 0x210, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("uart-sclk", + uart_sclk_parents, + &clk_mux_ops, + 0), + } +}; + +static struct ccu_common *th1520_pll_clks[] =3D { + &cpu_pll0_clk.common, + &cpu_pll1_clk.common, + &gmac_pll_clk.common, + &video_pll_clk.common, + &dpu0_pll_clk.common, + &dpu1_pll_clk.common, + &tee_pll_clk.common, +}; + +static struct ccu_common *th1520_div_clks[] =3D { + &ahb2_cpusys_hclk.common, + &apb3_cpusys_pclk.common, + &axi4_cpusys2_aclk.common, + &perisys_ahb_hclk.common, + &perisys_apb_pclk.common, + &axi_aclk.common, + &peri2sys_apb_pclk.common, + &out1_clk.common, + &out2_clk.common, + &out3_clk.common, + &out4_clk.common, + &apb_pclk.common, + &npu_clk.common, + &vi_clk.common, + &vi_ahb_clk.common, + &vo_axi_clk.common, + &vp_apb_clk.common, + &vp_axi_clk.common, + &cpu2vp_clk.common, + &venc_clk.common, + &dpu0_clk.common, + &dpu1_clk.common, +}; + +static struct ccu_common *th1520_mux_clks[] =3D { + &c910_i0_clk.common, + &c910_clk.common, + &uart_sclk.common, +}; + +static struct ccu_common *th1520_gate_clks[] =3D { + &emmc_sdio_clk.common, + &aon2cpu_a2x_clk.common, + &x2x_cpusys_clk.common, + &brom_clk.common, + &bmu_clk.common, + &cpu2aon_x2h_clk.common, + &cpu2peri_x2h_clk.common, + &perisys_apb1_hclk.common, + &perisys_apb2_hclk.common, + &perisys_apb3_hclk.common, + &perisys_apb4_hclk.common, + &npu_axi_clk.common, + &gmac1_clk.common, + &padctrl1_clk.common, + &dsmart_clk.common, + &padctrl0_clk.common, + &gmac_axi_clk.common, + &gpio3_clk.common, + &gmac0_clk.common, + &pwm_clk.common, + &qspi0_clk.common, + &qspi1_clk.common, + &spi_clk.common, + &uart0_pclk.common, + &uart1_pclk.common, + &uart2_pclk.common, + &uart3_pclk.common, + &uart4_pclk.common, + &uart5_pclk.common, + &gpio0_clk.common, + &gpio1_clk.common, + &gpio2_clk.common, + &i2c0_clk.common, + &i2c1_clk.common, + &i2c2_clk.common, + &i2c3_clk.common, + &i2c4_clk.common, + &i2c5_clk.common, + &spinlock_clk.common, + &dma_clk.common, + &mbox0_clk.common, + &mbox1_clk.common, + &mbox2_clk.common, + &mbox3_clk.common, + &wdt0_clk.common, + &wdt1_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &sram0_clk.common, + &sram1_clk.common, + &sram2_clk.common, + &sram3_clk.common, +}; + +#define NR_CLKS (CLK_UART_SCLK + 1) + +static const struct regmap_config th1520_clk_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .fast_io =3D true, +}; + +static int th1520_clk_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct clk_hw_onecell_data *priv; + + struct regmap *map; + void __iomem *base; + struct clk_hw *hw; + int ret, i; + + priv =3D devm_kzalloc(dev, struct_size(priv, hws, NR_CLKS), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->num =3D NR_CLKS; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map =3D devm_regmap_init_mmio(dev, base, &th1520_clk_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + + for (i =3D 0; i < ARRAY_SIZE(th1520_pll_clks); i++) { + struct ccu_pll *cp =3D hw_to_ccu_pll(&th1520_pll_clks[i]->hw); + + th1520_pll_clks[i]->map =3D map; + + ret =3D devm_clk_hw_register(dev, &th1520_pll_clks[i]->hw); + if (ret) + return ret; + + priv->hws[cp->common.clkid] =3D &cp->common.hw; + } + + for (i =3D 0; i < ARRAY_SIZE(th1520_div_clks); i++) { + struct ccu_div *cd =3D hw_to_ccu_div(&th1520_div_clks[i]->hw); + + th1520_div_clks[i]->map =3D map; + + ret =3D devm_clk_hw_register(dev, &th1520_div_clks[i]->hw); + if (ret) + return ret; + + priv->hws[cd->common.clkid] =3D &cd->common.hw; + } + + for (i =3D 0; i < ARRAY_SIZE(th1520_mux_clks); i++) { + struct ccu_mux *cm =3D hw_to_ccu_mux(&th1520_mux_clks[i]->hw); + const struct clk_init_data *init =3D cm->common.hw.init; + + th1520_mux_clks[i]->map =3D map; + hw =3D devm_clk_hw_register_mux_parent_data_table(dev, + init->name, + init->parent_data, + init->num_parents, + 0, + base + cm->common.cfg0, + cm->mux.shift, + cm->mux.width, + 0, NULL, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->hws[cm->common.clkid] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(th1520_gate_clks); i++) { + struct ccu_gate *cg =3D hw_to_ccu_gate(&th1520_gate_clks[i]->hw); + + th1520_gate_clks[i]->map =3D map; + + hw =3D devm_clk_hw_register_gate_parent_data(dev, + cg->common.hw.init->name, + cg->common.hw.init->parent_data, + 0, base + cg->common.cfg0, + ffs(cg->enable) - 1, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->hws[cg->common.clkid] =3D hw; + } + + ret =3D devm_clk_hw_register(dev, &osc12m_clk.hw); + if (ret) + return ret; + priv->hws[CLK_OSC12M] =3D &osc12m_clk.hw; + + ret =3D devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw); + if (ret) + return ret; + priv->hws[CLK_PLL_GMAC_100M] =3D &gmac_pll_clk_100m.hw; + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id th1520_clk_match[] =3D { + { + .compatible =3D "thead,th1520-clk-ap", + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, th1520_clk_match); + +static struct platform_driver th1520_clk_driver =3D { + .probe =3D th1520_clk_probe, + .driver =3D { + .name =3D "th1520-clk", + .of_match_table =3D th1520_clk_match, + }, +}; +module_platform_driver(th1520_clk_driver); + +MODULE_DESCRIPTION("T-HEAD TH1520 AP Clock driver"); +MODULE_AUTHOR("Yangtao Li "); +MODULE_AUTHOR("Jisheng Zhang "); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Tue Dec 16 19:23:26 2025 Received: from mail-oa1-f41.google.com (mail-oa1-f41.google.com [209.85.160.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28D0C525E for ; Mon, 24 Jun 2024 02:15:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719195349; cv=none; b=Pwcyo05EJJDVKMm8bGMgjO+Vzwhi7mUaCOg0nR+5XIxk1fBqeBdomM1TJgsyQVOgbMs4hMwvQS+lTt6CNT2omcdUMh3SDWsqCgBKKk2KcDktyMhEUk4n8i0fAaR/nZC7Y2O9CUgVNyww2RS0yIcHBBFAWRh2N7/6N/jtDLl8/Kk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719195349; c=relaxed/simple; bh=Tex1awMNjudnvI3gtikHr2F7lrSHZ1e0QS1byS+Ld1c=; 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Sun, 23 Jun 2024 19:15:46 -0700 (PDT) From: Drew Fustini Date: Sun, 23 Jun 2024 19:12:33 -0700 Subject: [PATCH v2 3/7] riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-th1520-clk-v2-3-ad8d6432d9fb@tenstorrent.com> References: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> In-Reply-To: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719195343; l=1133; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=Tex1awMNjudnvI3gtikHr2F7lrSHZ1e0QS1byS+Ld1c=; b=pu8+Mu7mJzVnU5HrfATMNP9rHowooKXJoEvBNn6bXAtFkRqWrQI19xVB26zkobp5fnXrOXElB hN1N6vPKEoNCZlE+eMWGRcGy88R8bdUeAt6ViPI/yK9kVPYosF9CtGV X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Add node for the AP_SUBSYS clock controller on the T-Head TH1520 SoC. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T= H1520%20System%20User%20Manual.pdf Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index d2fa25839012..10a38ed55658 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -5,6 +5,7 @@ */ =20 #include +#include =20 / { compatible =3D "thead,th1520"; @@ -161,6 +162,13 @@ soc { dma-noncoherent; ranges; =20 + clk: clock-controller@ffef010000 { + compatible =3D "thead,th1520-clk-ap"; + reg =3D <0xff 0xef010000 0x0 0x1000>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + plic: interrupt-controller@ffd8000000 { compatible =3D "thead,th1520-plic", "thead,c900-plic"; reg =3D <0xff 0xd8000000 0x0 0x01000000>; --=20 2.34.1 From nobody Tue Dec 16 19:23:26 2025 Received: from mail-oi1-f173.google.com (mail-oi1-f173.google.com [209.85.167.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2A1079F6 for ; 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Sun, 23 Jun 2024 19:15:48 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:1584:936e:5eb0:fab]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-706511b137csm5071770b3a.86.2024.06.23.19.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jun 2024 19:15:47 -0700 (PDT) From: Drew Fustini Date: Sun, 23 Jun 2024 19:12:34 -0700 Subject: [PATCH v2 4/7] riscv: dts: thead: change TH1520 uart nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-th1520-clk-v2-4-ad8d6432d9fb@tenstorrent.com> References: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> In-Reply-To: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719195343; l=4110; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=auGSbMjsRld4SLXQydJm42vMc+m34WENWJOd8P1SjjI=; b=3eVam+1jlNyHHZSlI8nSDB4WHMB+sYoN7SK+tbRvC/FEfFfUGRXFLTp1g/HkUJ3oBhXKOc/78 K0J5eZxyEIoB264vRv0lqXTXewTuxOqn9JjwBYHq0ewVxivrvf5Q8yK X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the clock property in TH1520 uart nodes to a clock provided by AP_SUBSYS clock controller. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-------= ---- 3 files changed, 12 insertions(+), 20 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index d9b4de9e4757..164afd18b56c 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -52,10 +52,6 @@ &sdhci_clk { clock-frequency =3D <198000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1365d3a512a3..1b7ede570994 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -33,10 +33,6 @@ &sdhci_clk { clock-frequency =3D <198000000>; }; =20 -&uart_sclk { - clock-frequency =3D <100000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 10a38ed55658..66df04ceb3e4 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -141,12 +141,6 @@ apb_clk: apb-clk-clock { #clock-cells =3D <0>; }; =20 - uart_sclk: uart-sclk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "uart_sclk"; - #clock-cells =3D <0>; - }; - sdhci_clk: sdhci-clock { compatible =3D "fixed-clock"; clock-frequency =3D <198000000>; @@ -195,7 +189,8 @@ uart0: serial@ffe7014000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7014000 0x0 0x100>; interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -232,7 +227,8 @@ uart1: serial@ffe7f00000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f00000 0x0 0x100>; interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -242,7 +238,8 @@ uart3: serial@ffe7f04000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xe7f04000 0x0 0x100>; interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -324,7 +321,8 @@ uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&uart_sclk>; + clocks =3D <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; + clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; status =3D "disabled"; @@ -386,7 +384,8 @@ uart4: serial@fff7f08000 { compatible =3D "snps,dw-apb-uart"; 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a=ed25519-sha256; t=1719195343; l=2852; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=fVxaLUMTb3CyDlrBVjs+Sch5+L04pOv+EAfH3Xd/w5E=; b=HNA4TrACYlPMj2b3NCZ/cUVczsm8my7IqBecoB3JoarAlOInJZM8as4J/k9ayqg7ee3656Zyx vC3CHuzDSZVAdmafpeWS9vx0NjCbXL48XSXYgClr3N6mcirKtZ/noTJ X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the clock property in the TH1520 mmc controller nodes to a clock provided by AP_SYS clock controller. Remove sdhci fixed clock reference from BeagleV Ahead and LPI4a dts. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 13 +++---------- 3 files changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 164afd18b56c..55f1ed0cb433 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -48,10 +48,6 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 -&sdhci_clk { - clock-frequency =3D <198000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1b7ede570994..762eceb415f8 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,10 +29,6 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 -&sdhci_clk { - clock-frequency =3D <198000000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 66df04ceb3e4..ce3a0847aa9c 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -141,13 +141,6 @@ apb_clk: apb-clk-clock { #clock-cells =3D <0>; }; =20 - sdhci_clk: sdhci-clock { - compatible =3D "fixed-clock"; - clock-frequency =3D <198000000>; - clock-output-names =3D "sdhci_clk"; - #clock-cells =3D <0>; - }; - soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -200,7 +193,7 @@ emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&sdhci_clk>; + clocks =3D <&clk CLK_EMMC_SDIO>; clock-names =3D "core"; status =3D "disabled"; }; @@ -209,7 +202,7 @@ sdio0: mmc@ffe7090000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7090000 0x0 0x10000>; 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Sun, 23 Jun 2024 19:15:49 -0700 (PDT) From: Drew Fustini Date: Sun, 23 Jun 2024 19:12:36 -0700 Subject: [PATCH v2 6/7] riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-th1520-clk-v2-6-ad8d6432d9fb@tenstorrent.com> References: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> In-Reply-To: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719195343; l=4851; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=CJyRU2euk+h8MQ3uF4akWb8lHgrUYTVPRvEJzPNHbOU=; b=mNsn8JF4kFtRIlgga/Xmq9+3MshgDGyu9OUR6HpWzEdWNOwPQV05o7B8GmUXs3Dk7ZQ2mNxJi 2BPyOgkY7t/CJRA4WBk2A5H8jQn9JkuBsh1SoYfj6/gWb5uq9Mn+hF0 X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Change the dma-controller and timer nodes to use the APB clock provided by the AP_SUBSYS clock controller. Remove apb_clk reference from BeagleV Ahead and LPI4a dts. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++----------= ---- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 55f1ed0cb433..1180e41c7b07 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -44,10 +44,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 762eceb415f8..78977bdbbe3d 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -25,10 +25,6 @@ &osc_32k { clock-frequency =3D <32768>; }; =20 -&apb_clk { - clock-frequency =3D <62500000>; -}; - &dmac0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index ce3a0847aa9c..d05002ad7c96 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -135,12 +135,6 @@ osc_32k: 32k-oscillator { #clock-cells =3D <0>; }; =20 - apb_clk: apb-clk-clock { - compatible =3D "fixed-clock"; - clock-output-names =3D "apb_clk"; - #clock-cells =3D <0>; - }; - soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -325,7 +319,7 @@ dmac0: dma-controller@ffefc00000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0xff 0xefc00000 0x0 0x1000>; interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&apb_clk>, <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; clock-names =3D "core-clk", "cfgr-clk"; #dma-cells =3D <1>; dma-channels =3D <4>; @@ -340,7 +334,7 @@ dmac0: dma-controller@ffefc00000 { timer0: timer@ffefc32000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -349,7 +343,7 @@ timer0: timer@ffefc32000 { timer1: timer@ffefc32014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -358,7 +352,7 @@ timer1: timer@ffefc32014 { timer2: timer@ffefc32028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -367,7 +361,7 @@ timer2: timer@ffefc32028 { timer3: timer@ffefc3203c { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc3203c 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -398,7 +392,7 @@ uart5: serial@fff7f0c000 { timer4: timer@ffffc33000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33000 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -407,7 +401,7 @@ timer4: timer@ffffc33000 { timer5: timer@ffffc33014 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33014 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -416,7 +410,7 @@ timer5: timer@ffffc33014 { timer6: timer@ffffc33028 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33028 0x0 0x14>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; clock-names =3D "timer"; interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; @@ -425,7 +419,7 @@ timer6: timer@ffffc33028 { timer7: timer@ffffc3303c { compatible =3D "snps,dw-apb-timer"; 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Sun, 23 Jun 2024 19:15:50 -0700 (PDT) From: Drew Fustini Date: Sun, 23 Jun 2024 19:12:37 -0700 Subject: [PATCH v2 7/7] riscv: dts: thead: add clock to TH1520 gpio nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-th1520-clk-v2-7-ad8d6432d9fb@tenstorrent.com> References: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> In-Reply-To: <20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com> To: Jisheng Zhang , Guo Ren , Fu Wei , Yangtao Li , Thomas Bonnefille , Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719195343; l=1705; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=1YUFcjPStRQXnRCkm7LFCYqYtH2keuIc2Ndi6ymcweU=; b=rYBGKNJzXmCmLAga5clXqSFTTT6acEgLUJTAcP100RcfUjqlXe3oY4DKYzEONUhMhRslOqumq IBxq129anadAhKP9VsQmsnBjrF17brGOw1fgRg6bSOgGM2pr+vivXcb X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Add clock property to TH1520 gpio controller nodes. These clock gates refer to corresponding enable bits in the peripheral clock gate control register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the TH1520 System User Manual. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/d= ocs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index d05002ad7c96..351e09beab70 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -237,6 +237,7 @@ gpio2: gpio@ffe7f34000 { reg =3D <0xff 0xe7f34000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO2>; =20 portc: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -255,6 +256,7 @@ gpio3: gpio@ffe7f38000 { reg =3D <0xff 0xe7f38000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO3>; =20 portd: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -273,6 +275,7 @@ gpio0: gpio@ffec005000 { reg =3D <0xff 0xec005000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO0>; =20 porta: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -291,6 +294,7 @@ gpio1: gpio@ffec006000 { reg =3D <0xff 0xec006000 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + clocks =3D <&clk CLK_GPIO1>; =20 portb: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; --=20 2.34.1