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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240623-qcom-adreno-dts-bindings-driver-v2-1-9496410de992@linaro.org> References: <20240623-qcom-adreno-dts-bindings-driver-v2-0-9496410de992@linaro.org> In-Reply-To: <20240623-qcom-adreno-dts-bindings-driver-v2-0-9496410de992@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Conor Dooley , Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1071; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=4/9Aq/arFNn+xRSwSsZRPh1izhnXURJa1LwMF+ulWIA=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBmeH+GBCUCUJpJdjHiAhVps4qq/mnaC30VIybMf k4SsU1FP9WJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZnh/hgAKCRDBN2bmhouD 1zJpD/4hFM10qme9VeV2lS5WgpaIGfkSCtPbJ9yqeAmaQunz1ilA8smxq8cdUVXE9gLxmFhU5l1 lQI+Lt85hl+Y5dXEqzVKxzrxeWj7YMdNX//e9a3b76kZPr3OESjU6xFZ8wYcAsFPyTqiKUFh8FU hGD0Cy+ql0nbC4mA3mQSyQDKuDymYy55LJjnruaHgjIx8dE1LugaPIOsIbfgU2tC3TMhLBqkvrw jpIfJu0wJd2iY7blxkFwA2i3gAvo1FHIlj9k0oUMNo/miPH4Bc6NEux0tDGkDftTKM9gn67wz4D 7YdaDJ24YV7g1pckorl4PYZS6cLcJ8+MXl+ovS4oYAf3/21eqYYUiPTCYvLvCjDCh/t+gcki17U b5gZFIG+X7H5IDDEQNk9QWbjP9fNQdqeMkgyEF4p6fF7j10zzpGh4IllsMEO2bY0h91CXKqG+A0 Kkku9mY+F7xAWHFIB38ZkRxZFcP3VicGP8HmGnase3+7GOWNG+xSNnkzUdRhwB9uZH/taKN2e22 v8jUhjV3gEsrLWjXqsrIja17NJDgakeyCKRqJizfHMBJIuE1lkP642irbb2BCnfknwUSdQVhDpM EaiPu+ZJ9ZmllVhplasqbS8nXwQoCwCL8Ct9Mm4dmk7Y3SnKlr8mxcNmqB08LjmKjTkxsEVronl XRvouwunMTYdgig== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B We expect each schema with variable number of clocks, to have the widest constrains in top-level "properties:". This is more readable and also makes binding stricter, if there is no "if:then:" block for given variant. Acked-by: Conor Dooley Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 40b5c6bd11f8..253e68d92779 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -32,9 +32,13 @@ properties: - pattern: '^amd,imageon-200\.[0-1]$' - const: amd,imageon =20 - clocks: true + clocks: + minItems: 2 + maxItems: 7 =20 - clock-names: true + clock-names: + minItems: 2 + maxItems: 7 =20 reg: minItems: 1 --=20 2.43.0 From nobody Mon Feb 9 09:05:23 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D92B185088 for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B All devices should (and actually do) have same order of entries, if possible. That's the case for reg/reg-names, so define the reg-names in top-level to enforce that. Acked-by: Conor Dooley Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 253e68d92779..baea1946c65d 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -46,7 +46,10 @@ properties: =20 reg-names: minItems: 1 - maxItems: 3 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc =20 interrupts: maxItems: 1 --=20 2.43.0 From nobody Mon Feb 9 09:05:23 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63AD412FF7B for ; Sun, 23 Jun 2024 20:03:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Regex for newer Adreno compatibles can be simpler. Suggested-by: Conor Dooley Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index baea1946c65d..03aaced1abda 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -17,7 +17,7 @@ properties: The driver is parsing the compat string for Adreno to figure out the chip-id. items: - - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f= ][0-9a-f][0-9a-f][0-9a-f]$' + - pattern: '^qcom,adreno-[0-9a-f]{8}$' - const: qcom,adreno - description: | The driver is parsing the compat string for Adreno to --=20 2.43.0 From nobody Mon Feb 9 09:05:23 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CABEF185E7B for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B dtschema v2024.4, v2024.5 and maybe earlier do not select device nodes for given binding validation if the schema contains compatible list with pattern and a const fallback. This leads to binding being a no-op - not being applied at all. Issue should be fixed in the dtschema but for now add a work-around do the binding can be used against DTS validation. Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley --- This will uncover issues with DTS, which is expected and fixed in: 1. Incorrect AMD compatible: https://lore.kernel.org/linux-arm-msm/20240623193420.333735-1-krzysztof.= kozlowski@linaro.org/T/#t 2. alwayson clock: https://lore.kernel.org/linux-arm-msm/20240121194221.13513-6-a39.skl@gma= il.com/ --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 03aaced1abda..6ddc72fd85b0 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -10,6 +10,18 @@ title: Adreno or Snapdragon GPUs maintainers: - Rob Clark =20 +# dtschema does not select nodes based on pattern+const, so add custom sel= ect +# as a work-around: +select: + properties: + compatible: + contains: + enum: + - qcom,adreno + - amd,imageon + required: + - compatible + properties: compatible: oneOf: --=20 2.43.0