From nobody Wed Dec 17 13:56:58 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1412216C445; Sat, 22 Jun 2024 16:19:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719073158; cv=none; b=dOD+K4zNhW9D0NsLoqI3YcihpTd1lcbc491lL1LLc+rNbigEoMdy1bJmlsQqrdxsPEdoHKNHrnfCji+dRXjn6OFayuA2FFkN37a9IVrc+TmfVKFLlY/tBnmSdvaWsj4WyoTRyHudQqGPr+81PupnuCbOs7gus0ak5K4kbCNRXY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719073158; c=relaxed/simple; bh=R1fJAxEmEa9+Ogxf/UQa4lVvbvX8kI5YG4jOsFb1HgY=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=P9wyXTvgQQiBpDqOEDoxrKMRzXLGp3rvlglzkCdawAm+v50GROML+y0Onb5qo6u/OxhjUs4SANL9CBdwUBjgOUPdQ8NZ4Z+9O+TohhJz1V/XviZrqrDBM6Zpvt5Dw1Q6IJlNRsijXGFyBFXZsJvbS8+ghvy/5yYFoqsqO0OMs/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=QhdxPuce; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QhdxPuce" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45MGJ4Y2061387; Sat, 22 Jun 2024 11:19:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1719073144; bh=C4RoinTQTtmRn4rV2KwDh6NL62drf5wIG8VbXAUiIrs=; h=From:To:CC:Subject:Date; b=QhdxPuce6CkqLZkLH4MmWW+ybITatONSC13UXT6O6H3swWDOvRBA61845JgNI59Kh C+oi6o0HvCGZNQyfYP3IW9lZWNjJ7B8kF//sDIcsN5dIHY9JomPCxADoa9vavzKnTr 1XwkHnGz64XKQ8CxySEOaxnwFzxAGaxChW11pHyo= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45MGJ4JR001208 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 22 Jun 2024 11:19:04 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 22 Jun 2024 11:19:03 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 22 Jun 2024 11:19:03 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (udit-hp-z2-tower-g9-workstation-desktop-pc.dhcp.ti.com [172.24.227.18]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45MGJ0M1029138; Sat, 22 Jun 2024 11:19:00 -0500 From: Udit Kumar To: , CC: , , , , , , , , Sinthu Raja , Udit Kumar Subject: [PATCH v4] arm64: dts: ti: k3-am68-sk-som: Add support for OSPI flash Date: Sat, 22 Jun 2024 21:48:35 +0530 Message-ID: <20240622161835.3610348-1-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Sinthu Raja AM68 SK has an OSPI NOR flash on its SOM connected to OSPI0 instance. Enable support for the same. Also, describe the OSPI flash partition information through the device tree, according to the offsets in the bootloader. Signed-off-by: Sinthu Raja Signed-off-by: Udit Kumar --- Bootlogs https://gist.github.com/uditkumarti/3a131e3c78f121cf8c2f703d307c02df#file-g= istfile1-txt line 1451 Changes in v4: a. Added bootph properties b. INT pin is not used by flash drivers, so dropping this c. reverting partition 0 offset to 512KB, due to DFU boot failure seen on other K3 SOC with 1MB offset. Changes in v3: a. Fix the make dtbs_check error related to ospi pinctrl b. Increase the partition 0 size to 1MB and update the following partitions start address accordingly. Changes in v2: a. remove pin E20, which is not connected. v3: https://lore.kernel.org/all/20240226095231.35684-1-sinthu.raja@ti.com/ v2: https://lore.kernel.org/linux-arm-kernel/20240219075932.6458-1-sinthu.r= aja@ti.com/ v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240206092= 334.30307-1-sinthu.raja@ti.com/=20 arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 2ebb7daa822f..5c66e0ec6e82 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -131,6 +131,25 @@ rtos_ipc_memory_region: ipc-memories@a8000000 { }; }; =20 +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins { + bootph-all; + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + >; + }; +}; + &wkup_pmx2 { wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins =3D < @@ -153,6 +172,68 @@ eeprom@51 { }; }; =20 +&ospi0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + + partitions { + bootph-all; + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "ospi.tiboot3"; + reg =3D <0x0 0x80000>; + }; + + partition@80000 { + label =3D "ospi.tispl"; + reg =3D <0x80000 0x200000>; + }; + + partition@280000 { + label =3D "ospi.u-boot"; + reg =3D <0x280000 0x400000>; + }; + + partition@680000 { + label =3D "ospi.env"; + reg =3D <0x680000 0x40000>; + }; + + partition@740000 { + label =3D "ospi.env.backup"; + reg =3D <0x740000 0x40000>; + }; + + partition@800000 { + label =3D "ospi.rootfs"; + reg =3D <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label =3D "ospi.phypattern"; + reg =3D <0x3fc0000 0x40000>; + }; + }; + }; +}; + &mailbox0_cluster0 { status =3D "okay"; interrupts =3D <436>; --=20 2.34.1