From nobody Wed Dec 17 07:08:57 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3BE4E1A3BD3 for ; Thu, 20 Jun 2024 09:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718875588; cv=none; b=mkliVNwPWgOySilTFmCJQC+Cl1Zn0xuYHugB6tjpzUQFbDbphuHlQ2xL2uOISmWR63FqUTeGZLpEc34458hVN1oy7NeeeP5yY9Wp2hZzJ+LtyxqtVEogzwNsfNV/FCqeqh+jRStvrg8E6TpAy/qftzv0EkoFc1OwqXgia49La9k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718875588; c=relaxed/simple; bh=tyqWFVMaR+KSJElr8bKCmDSzta5fVmDf1oFmPULqzMc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RdtojD21biZkY5smf1izcp2AdKVzSYjmK+v/J/DFZ9y66qgYkpa+vjf6D4Ve2KE2lWa2Ou7IqhDstFJZH/9Md0N3WtJ3V3IZK18Yf7L6DdhsA1zTbyORLCAPpSrgyHnmIpdgFBg0TwWD9+AXz1c/QUzQiSaFyn6q3UZbiiapiNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D49E1042; Thu, 20 Jun 2024 02:26:46 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 31FB43F6A8; Thu, 20 Jun 2024 02:26:16 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC V2 1/3] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Date: Thu, 20 Jun 2024 14:56:05 +0530 Message-Id: <20240620092607.267132-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620092607.267132-1-anshuman.khandual@arm.com> References: <20240620092607.267132-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds required field details for ID_AA64DFR1_EL1, and also drops dummy ftr_raz[] array which is now redundant. These register fields will be used to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9 later. Cc: Catalin Marinas Cc: Will Deacon cc: Mark Brown Cc: Mark Rutland Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 48e7029f1054..12f0a5181bf2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -527,6 +527,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64dfr1[] =3D { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_AB= L_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_DP= FZS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EB= EP_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_IT= E_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_AB= LE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_PM= ICNTR_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SP= MU_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_CT= X_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_WR= Ps_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_BR= Ps_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SY= SPMUID_SHIFT, 8, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_mvfr0[] =3D { ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_= SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_= SHIFT, 4, 0), @@ -705,10 +720,6 @@ static const struct arm64_ftr_bits ftr_single32[] =3D { ARM64_FTR_END, }; =20 -static const struct arm64_ftr_bits ftr_raz[] =3D { - ARM64_FTR_END, -}; - #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ .sys_id =3D id, \ .reg =3D &(struct arm64_ftr_reg){ \ @@ -781,7 +792,7 @@ static const struct __ftr_reg_entry { =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), - ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), + ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1), =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 6 */ ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), --=20 2.25.1 From nobody Wed Dec 17 07:08:57 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3BE021A3BD2; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8581BDA7; Thu, 20 Jun 2024 02:26:51 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1DA173F6A8; Thu, 20 Jun 2024 02:26:21 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC V2 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Date: Thu, 20 Jun 2024 14:56:06 +0530 Message-Id: <20240620092607.267132-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620092607.267132-1-anshuman.khandual@arm.com> References: <20240620092607.267132-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fine grained trap control for MDSELR_EL1 register needs to be configured in HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 is also present. This adds a new helper __init_el2_fgt2() initializing this new FEAT_FGT2 based fine grained registers. MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and watchpoint exceptions when kernel enters at EL1, but EL2 is also present. This updates __init_el2_debug() as required for FEAT_Debugv8p9. While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet Cc: Marc Zyngier Cc: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual --- Documentation/arch/arm64/booting.rst | 19 +++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 27 +++++++++++++++++++++++++++ arch/arm64/include/asm/kvm_arm.h | 1 + 3 files changed, 47 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index b57776a68f15..e69d972018cf 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. =20 + For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: =20 - If EL3 is present and the kernel is entered at EL2: @@ -319,6 +325,19 @@ Before jumping into the kernel, the following conditio= ns must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. =20 + For CPUs with FEAT_Debugv8p9 extension present: + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 + + - If EL3 is present: + + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 + - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1 + For CPUs with the Scalable Matrix Extension (FEAT_SME): =20 - If EL3 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index fd87c4b8f984..0cb26a9f34c3 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -97,6 +97,14 @@ // to own it. =20 .Lskip_trace_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov x0, #MDCR_EL2_EBWE + orr x2, x2, x0 +.Lskip_dbg_v8p9_\@: msr mdcr_el2, x2 // Configure debug traps .endm =20 @@ -204,6 +212,24 @@ .Lskip_fgt_\@: .endm =20 +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HDFGRTR2_EL2, x0 +.Lskip_dbg_v8p9_\@: +.Lskip_fgt2_\@: +.endm + .macro __init_el2_nvhe_prepare_eret mov x0, #INIT_PSTATE_EL1 msr spsr_el2, x0 @@ -229,6 +255,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 .endm =20 #ifndef __KVM_NVHE_HYPERVISOR__ diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index b3fb368bcadb..8621a278ce25 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -312,6 +312,7 @@ GENMASK(15, 0)) =20 /* Hyp Debug Configuration Register bits */ +#define MDCR_EL2_EBWE (UL(1) << 43) #define MDCR_EL2_E2TB_MASK (UL(0x3)) #define MDCR_EL2_E2TB_SHIFT (UL(24)) #define MDCR_EL2_HPMFZS (UL(1) << 36) --=20 2.25.1 From nobody Wed Dec 17 07:08:57 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 66D5A1A00D5 for ; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A29C6DA7; Thu, 20 Jun 2024 02:26:56 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 607863F6A8; Thu, 20 Jun 2024 02:26:27 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC V2 3/3] arm64/hw_breakpoint: Enable FEAT_Debugv8p9 Date: Thu, 20 Jun 2024 14:56:07 +0530 Message-Id: <20240620092607.267132-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620092607.267132-1-anshuman.khandual@arm.com> References: <20240620092607.267132-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently there can be maximum 16 breakpoints, and 16 watchpoints available on a given platform - as detected from ID_AA64DFR0_EL1.[BRPs|WRPs] register fields. But these breakpoint, and watchpoints can be extended further up to 64 via a new arch feature FEAT_Debugv8p9. This first enables banked access for the breakpoint and watchpoint register set via MDSELR_EL1, extended exceptions via MDSCR_EL1.EMBWE and determining available breakpoints and watchpoints in the platform from ID_AA64DFR1_EL1, when FEAT_Debugv8p9 is enabled. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/debug-monitors.h | 1 + arch/arm64/include/asm/hw_breakpoint.h | 50 ++++++++++++++++++++----- arch/arm64/kernel/debug-monitors.c | 16 ++++++-- arch/arm64/kernel/hw_breakpoint.c | 33 ++++++++++++++++ 4 files changed, 86 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/a= sm/debug-monitors.h index 13d437bcbf58..a14097673ae0 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -20,6 +20,7 @@ #define DBG_MDSCR_KDE (1 << 13) #define DBG_MDSCR_MDE (1 << 15) #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) +#define DBG_MDSCR_EMBWE (1UL << 32) =20 #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) =20 diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/as= m/hw_breakpoint.h index bd81cf17744a..362c4d4a64ac 100644 --- a/arch/arm64/include/asm/hw_breakpoint.h +++ b/arch/arm64/include/asm/hw_breakpoint.h @@ -79,8 +79,8 @@ static inline void decode_ctrl_reg(u32 reg, * Limits. * Changing these will require modifications to the register accessors. */ -#define ARM_MAX_BRP 16 -#define ARM_MAX_WRP 16 +#define ARM_MAX_BRP 64 +#define ARM_MAX_WRP 64 =20 /* Virtual debug register bases. */ #define AARCH64_DBG_REG_BVR 0 @@ -94,13 +94,25 @@ static inline void decode_ctrl_reg(u32 reg, #define AARCH64_DBG_REG_NAME_WVR wvr #define AARCH64_DBG_REG_NAME_WCR wcr =20 +static inline bool is_debug_v8p9_enabled(void) +{ + u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + int dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_D= ebugVer_SHIFT); + + return dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9; +} + /* Accessor macros for the debug registers. */ #define AARCH64_DBG_READ(N, REG, VAL) do {\ VAL =3D read_sysreg(dbg##REG##N##_el1);\ + if (is_debug_v8p9_enabled()) \ + preempt_enable(); \ } while (0) =20 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ write_sysreg(VAL, dbg##REG##N##_el1);\ + if (is_debug_v8p9_enabled()) \ + preempt_enable(); \ } while (0) =20 struct task_struct; @@ -138,19 +150,37 @@ static inline void ptrace_hw_copy_thread(struct task_= struct *task) /* Determine number of BRP registers available. */ static inline int get_num_brps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_BRPs_SHIFT); + u64 dfr0, dfr1; + int dver, brps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_Debug= Ver_SHIFT); + if (dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + brps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_BRPs_SHIFT, 8); + } else { + brps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_BRPs= _SHIFT); + } + return 1 + brps; } =20 /* Determine number of WRP registers available. */ static inline int get_num_wrps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_WRPs_SHIFT); + u64 dfr0, dfr1; + int dver, wrps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_Debug= Ver_SHIFT); + if (dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + wrps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_WRPs_SHIFT, 8); + } else { + wrps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_WRPs= _SHIFT); + } + return 1 + wrps; } =20 #ifdef CONFIG_CPU_PM diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-m= onitors.c index 64f2ecbdfe5c..3299d1e8dc61 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 /* Determine debug architecture. */ u8 debug_monitors_arch(void) @@ -34,7 +35,7 @@ u8 debug_monitors_arch(void) /* * MDSCR access routines. */ -static void mdscr_write(u32 mdscr) +static void mdscr_write(u64 mdscr) { unsigned long flags; flags =3D local_daif_save(); @@ -43,7 +44,7 @@ static void mdscr_write(u32 mdscr) } NOKPROBE_SYMBOL(mdscr_write); =20 -static u32 mdscr_read(void) +static u64 mdscr_read(void) { return read_sysreg(mdscr_el1); } @@ -76,10 +77,11 @@ early_param("nodebugmon", early_debug_disable); */ static DEFINE_PER_CPU(int, mde_ref_count); static DEFINE_PER_CPU(int, kde_ref_count); +static DEFINE_PER_CPU(int, embwe_ref_count); =20 void enable_debug_monitors(enum dbg_active_el el) { - u32 mdscr, enable =3D 0; + u64 mdscr, enable =3D 0; =20 WARN_ON(preemptible()); =20 @@ -90,6 +92,9 @@ void enable_debug_monitors(enum dbg_active_el el) this_cpu_inc_return(kde_ref_count) =3D=3D 1) enable |=3D DBG_MDSCR_KDE; =20 + if (is_debug_v8p9_enabled() && this_cpu_inc_return(embwe_ref_count) =3D= =3D 1) + enable |=3D DBG_MDSCR_EMBWE; + if (enable && debug_enabled) { mdscr =3D mdscr_read(); mdscr |=3D enable; @@ -100,7 +105,7 @@ NOKPROBE_SYMBOL(enable_debug_monitors); =20 void disable_debug_monitors(enum dbg_active_el el) { - u32 mdscr, disable =3D 0; + u64 mdscr, disable =3D 0; =20 WARN_ON(preemptible()); =20 @@ -111,6 +116,9 @@ void disable_debug_monitors(enum dbg_active_el el) this_cpu_dec_return(kde_ref_count) =3D=3D 0) disable &=3D ~DBG_MDSCR_KDE; =20 + if (is_debug_v8p9_enabled() && this_cpu_dec_return(embwe_ref_count) =3D= =3D 0) + disable &=3D ~DBG_MDSCR_EMBWE; + if (disable) { mdscr =3D mdscr_read(); mdscr &=3D disable; diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index 722ac45f9f7b..30156d732284 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -103,10 +103,40 @@ int hw_breakpoint_slots(int type) WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ WRITE_WB_REG_CASE(OFF, 15, REG, VAL) =20 +static int set_bank_index(int n) +{ + int mdsel_bank; + int bank =3D n / 16, index =3D n % 16; + + switch (bank) { + case 0: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_0; + break; + case 1: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_1; + break; + case 2: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_2; + break; + case 3: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_3; + break; + default: + pr_warn("Unknown register bank %d\n", bank); + } + preempt_disable(); + write_sysreg_s(mdsel_bank << MDSELR_EL1_BANK_SHIFT, SYS_MDSELR_EL1); + isb(); + return index; +} + static u64 read_wb_reg(int reg, int n) { u64 val =3D 0; =20 + if (is_debug_v8p9_enabled()) + n =3D set_bank_index(n); + switch (reg + n) { GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); @@ -122,6 +152,9 @@ NOKPROBE_SYMBOL(read_wb_reg); =20 static void write_wb_reg(int reg, int n, u64 val) { + if (is_debug_v8p9_enabled()) + n =3D set_bank_index(n); + switch (reg + n) { GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val= ); GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val= ); --=20 2.25.1