From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 537A644C64 for ; Thu, 20 Jun 2024 06:58:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866706; cv=none; b=mFm9kXl8/iiwBPaBH4mHa4vXa4W+hsnr3g8RnuxKm0YwWRaxitokmowP0LkZNZKB/Yt2Fx6WbVPfM7LRIPiTgcvzqB9ahm39cspbdxhJJrq+PN9albQbhBSkOjp/Yu8MDNJrC0wYCGFxEvCueFBDpxDGNAaPyo1xIaMkYLKziP4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866706; c=relaxed/simple; bh=rAWzQoKLawDmEfaA88cxGcCrCsJwwjtuG5tBfPZ0+gI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AfKN6zR9MjxAPfriTP0VZOlsD6+2fPtzRE5ppTDG++5+Mh/8Hb5N/I9zrwsyrV/gJ0Rs3DtP7Acd1qIl7VewvWPcuLLeSo5zpoTnv15kWf0u5VT81r1JaXa24xHBAt222eroH5pAReeynbXI+QpzAeS2jcykY+USxPLbA318cow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EB01DA7; Wed, 19 Jun 2024 23:58:48 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F29793F73B; Wed, 19 Jun 2024 23:58:18 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 01/10] arm64/sysreg: Update ID_AA64MMFR0_EL1 register Date: Thu, 20 Jun 2024 12:27:58 +0530 Message-Id: <20240620065807.151540-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64MMFR0_EL1.FGT and ID_AA64MMFR0_EL1.PARANGE register fields as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a4c1dd4741a4..b50dd7568c0d 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1556,6 +1556,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1617,6 +1618,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg =20 --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0453941746 for ; Thu, 20 Jun 2024 06:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866711; cv=none; b=QiZwIv2XVxOQkEo1l7F4g01wXcl+L2oVtKFkIy6an02dfwLJpUjAjlG4nT+GbqkPRUAxglDR6Gs5mv0ZSR5foj66gccblCdUcsR/DtLC2K9ehN6nWrWe4tQunrHw+NDKJOe7jV+aKfieFkvLP/fp/CIPkucZdua0r/TcWQTn57s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866711; c=relaxed/simple; bh=xjbJFsh+DNwv7lE4wWk8mOP/meWAocKRf2LzgDRYUqg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=py4K603E9I8AoF1WNEGweSiNI+v3Q8SjJnZAPy3g1PvfcrD4CvcHRovFHAXufehmTJX5tG3kCLqRu3CwdIxXok4lnf3y2vIK0alir4qlJSh1mZpgg5+/vQvG1hKuap3AsNCo4lnVgDATkB5Rn+/d4xGlatKqI5BsEgWgmHhk9uk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3857B1684; Wed, 19 Jun 2024 23:58:53 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7FD533F73B; Wed, 19 Jun 2024 23:58:24 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 02/10] arm64/sysreg: Update ID_AA64DFR0_EL1 register Date: Thu, 20 Jun 2024 12:27:59 +0530 Message-Id: <20240620065807.151540-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64DFR0_EL1.[SEBEP|PMSS|PMUVer] register fields as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b50dd7568c0d..4b44ea5dce7e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1226,9 +1226,15 @@ UnsignedEnum 35:32 PMSVer 0b0101 V1P4 EndEnum Field 31:28 CTX_CMPs -Res0 27:24 +UnsignedEnum 27:24 SEBEP + 0b0000 NI + 0b0001 IMP +EndEnum Field 23:20 WRPs -Res0 19:16 +UnsignedEnum 19:16 PMSS + 0b0000 NI + 0b0001 IMP +EndEnum Field 15:12 BRPs UnsignedEnum 11:8 PMUVer 0b0000 NI @@ -1238,6 +1244,7 @@ UnsignedEnum 11:8 PMUVer 0b0110 V3P5 0b0111 V3P7 0b1000 V3P8 + 0b1001 V3P9 0b1111 IMP_DEF EndEnum UnsignedEnum 7:4 TraceVer --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A440B41C92 for ; Thu, 20 Jun 2024 06:58:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866715; cv=none; b=UtilIa7rcYoYw6OpHtVtTbinN8LEUXeKFB1ae3U9h0YG17Q487Pgd8pjtYKvucN/CaTJzAXMRudzYhn5XwgDPnFwtbOWueukVgYhCgFT1ef9Kk66ozJe9raExfCkkwkk9u0n65R2qNN6xwJHpUEV+FDvvSOKRjgc6o/hAnV1gjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866715; c=relaxed/simple; bh=Mnxp7ulmZhX7evHvfvvrVYDQQD3VnbjXhZM63/SYV50=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nGVzSBz5QLdxzUgzd0TiBNgxcNeeU9oDk39HDC1LCNjaC30sVfVnS1oSanM4zMcHEXpuKBfogjfuZ+nSAZdHaezmvDMYJ1Pprm5p2ELc8alGwdxQ5Fx8ZotyW07/I9J/DtLNmZGDTVUHtMYoh9WDvTuYlDZSD1w7LuVc3nr45pY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D0AE71042; Wed, 19 Jun 2024 23:58:57 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 185A23F73B; Wed, 19 Jun 2024 23:58:28 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 03/10] arm64/sysreg: Add register fields for ID_AA64DFR2_EL1 Date: Thu, 20 Jun 2024 12:28:00 +0530 Message-Id: <20240620065807.151540-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for ID_AA64DFR2_EL1 as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4b44ea5dce7e..df9111d11bc0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1294,6 +1294,19 @@ Field 15:8 BRPs Field 7:0 SYSPMUID EndSysreg =20 +Sysreg ID_AA64DFR2_EL1 3 0 0 5 2 +Res0 63:8 +UnsignedEnum 7:4 BWE + 0b0000 NI + 0b0001 IMP + 0b0010 IMP_WPT +EndEnum +UnsignedEnum 3:0 STEP + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64AFR0_EL1 3 0 0 5 4 Res0 63:32 Field 31:28 IMPDEF7 --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 457D64F602 for ; Thu, 20 Jun 2024 06:58:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866719; cv=none; b=mrM8DvaRCZS3mOiK+UPPWjjEs/ZDlnTH5pkNBH1CQ9FMqpJJqr3Jnbt8NeUJq3uQYcv6UJS2G2/dfGv0+WaAYwEJpH8TbFV5tnIIA4sJmUlhvQTeaPHbZkJSjFx011RCaYfPKwT+qx54fs1MA4hVTlQW7Tg/i1mFUXI4M4zxhOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866719; c=relaxed/simple; bh=ZTyeiuRHtcWkQmrihczn9ugDs9724cnC063ZPOgOofs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LIOpTzkEhYPT7kGaQB2RHyG2O4iB1Iuk2cxVqrRa8b8wYyPanZfTkycXLrN23s2XqPuFfE/nOHAy/a6iGmR2PLFNvQKgVokY68ivh52Ru4CRg7EUPpzUQA+GMGSohbX56+Eln1tIWkwuHxFwaGt5t76Ess65mu8lgWyo26EYnl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84AC4DA7; Wed, 19 Jun 2024 23:59:02 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ABEA13F73B; Wed, 19 Jun 2024 23:58:33 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 04/10] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Date: Thu, 20 Jun 2024 12:28:01 +0530 Message-Id: <20240620065807.151540-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index df9111d11bc0..8b43f99f6779 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2455,6 +2455,34 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:24 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0043144376 for ; Thu, 20 Jun 2024 06:58:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866724; cv=none; b=iBF3UplGd9FHzmaIRUalT3IoSyVUUaUmA0im94kxFjBoAKkExjXQAlNBa2rtfmfpQuYINiqIuuMyjMrvmcJHBfmo726kCe1uxnyfaIY15P7SNB1FViqwdiDqdAqokVQcL2npkBPZ4Vx+1EbavEPBRyUlxrX1cHPD2ssNHp9ZHV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866724; c=relaxed/simple; bh=MaptKQEXggdgTWeJWGD6HqSltEbT8KaW7mxL6990ZwY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kAYmHJcDeLMKcvcqW+jiDy36heSJXBrK7QI3hbs8eXmgG/T5G6oLr9W8wR/uhlSkcC6DXqzvhZ8aZzN6sqNK+A7KS8e1rllvjRZcqM9YEDW/BKGcgxZuls67dzpqBpkkkVYxiYdvgs2Rp4QyKt1m8Lq93UbSEJtlCSDYwXKb0mw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 638E2DA7; Wed, 19 Jun 2024 23:59:07 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 67C443F73B; Wed, 19 Jun 2024 23:58:38 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 05/10] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Date: Thu, 20 Jun 2024 12:28:02 +0530 Message-Id: <20240620065807.151540-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8b43f99f6779..3cd254755cd9 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2483,6 +2483,33 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:24 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BAF8756B79 for ; Thu, 20 Jun 2024 06:58:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866729; cv=none; b=rGvfxev3Ec2SIChmoutpbNZ8knEuFpt8gmbiqQQKarK1wdKpjLErkb+NNX6BEMLEoxGkhNt3L2Sum9NZulJHsxemd+N0EjjgGAzKVRhsrvcBYkWVa4PKU2UxIOziAO9uR1lacGP13UWgCqe78Ae90J3kkrtOp/PR/euQwmXNRFY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866729; c=relaxed/simple; bh=pDi1sPG5NrjjQEVXdhTn0qiICRVyL48r8SlrOeIQbHs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cl9RUNdDbs1aQTZLpORjljZEQnbaFO/XsU4W/z6ZDTok8PDF/GrMvVOC5kVgJL9R2RSFWRh654ckL4aII0XR+Ey4xEwqm+oBDzv+vVS4mI3mQl7mwfXAQHyCgm2/iXTqgCS/MKBhOPAa6BX0Nk5tMiVP9puTz0DKtiSBqOSIPuQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C2F3DA7; Wed, 19 Jun 2024 23:59:12 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5383A3F73B; Wed, 19 Jun 2024 23:58:42 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 06/10] arm64/sysreg: Add register fields for MDSELR_EL1 Date: Thu, 20 Jun 2024 12:28:03 +0530 Message-Id: <20240620065807.151540-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for MDSELR_EL1 as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 3cd254755cd9..0877fb8b4aff 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -93,6 +93,17 @@ Res0 63:32 Field 31:0 DTRTX EndSysreg =20 +Sysreg MDSELR_EL1 2 0 0 4 2 +Res0 63:6 +Enum 5:4 BANK + 0b00 BANK_0 + 0b01 BANK_1 + 0b10 BANK_2 + 0b11 BANK_3 +EndEnum +Res0 3:0 +EndSysreg + Sysreg OSECCR_EL1 2 0 0 6 2 Res0 63:32 Field 31:0 EDECCR --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5A61B4778C for ; Thu, 20 Jun 2024 06:58:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866735; cv=none; b=K2NW6Y+8nzB8YozsRp3QYDb98fLph8MNy3ExswFVcyy4IZBdP8zheJ2Xpd65DIGe4TXokky4ehtmtwTFcbtQSz8auf7POfr1qM7LoDPZ8Km1oYDd834oNoL5JqI8wwYe7mdQGBPaEh8Bj320CqpUnjOYuITGjyF6iLB1x5Ir1ok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866735; c=relaxed/simple; bh=NjW0d2BTZqkoD2r+NTxGFGRQ7rG82gjYc746mGb8O3I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hh9eAhgkZlAHHUWOEWmXBY4H5/4dg8uGwSMBclfe1MjD7LC+inPtSrQA7o1IJqMvck1wucN1XuXlZb/7bJPgtI1NvXCBKzpaj02XkYgFxNIqIRMXgwcIf49rjFpDQA17sbT4e20mq5tclDKuQIwXUKkzAKbFvrEMKHeeoVN8efc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDE24DA7; Wed, 19 Jun 2024 23:59:16 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ECE6E3F73B; Wed, 19 Jun 2024 23:58:47 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 07/10] arm64/sysreg: Add register fields for PMSID_EL1 Date: Thu, 20 Jun 2024 12:28:04 +0530 Message-Id: <20240620065807.151540-8-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMSID_EL1 as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0877fb8b4aff..ee2038f6f3a3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2112,7 +2112,16 @@ Field 15:0 MINLAT EndSysreg =20 Sysreg PMSIDR_EL1 3 0 9 9 7 -Res0 63:25 +Res0 63:33 +Field 32 SME +UnsignedEnum 31:28 ALTCLK + 0b0000 NI + 0b0001 IMP + 0b1111 IMP_DEF +EndEnum +Field 27 FPF +Field 26 EFT +Field 25 CRR Field 24 PBT Field 23:20 FORMAT Enum 19:16 COUNTSIZE @@ -2130,7 +2139,10 @@ Enum 11:8 INTERVAL 0b0111 3072 0b1000 4096 EndEnum -Res0 7 +UnsignedEnum 7 FDS + 0b0 NI + 0b1 IMP +EndEnum Field 6 FnE Field 5 ERND Field 4 LDS --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2BDCD4778C for ; Thu, 20 Jun 2024 06:58:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866739; cv=none; b=sToLkz15pYQ+kVU4ob4z/9xdmcAPXAjgLeWr0QO7c3eAMiR/W4N4jGqpDnXO3AqErLvpwZritBfuv4uE0lk7DRWTwe+XQWK6dxYRpAmtCo1H8nwEnNRl1eUhv42w6EMd4tziX3ZqbzMxI9R9fdqpMBps7fqvutswTk8xtAPPL9I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866739; c=relaxed/simple; bh=QIuJ7eHArijbgqvnVwOF+HA0Sai02Q5aBta+a0jbVjY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GWJrGKSEeqokV5V4Am6oeeak5cTTEaoP0IU28iIjWVv7BB89LVNTibG8OJXURnaoGSJy5AMH5pR5UQUR5cOJt6n14l35Kv32oUcbKMrTNzML1RHyBTbLyfve2XNR7dx8QinqaqnSodqCJ0tgpFS9udYVo8+oFjibS9g6+1GTXXU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FAC6DA7; Wed, 19 Jun 2024 23:59:22 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BEF963F73B; Wed, 19 Jun 2024 23:58:52 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 08/10] arm64/sysreg: Add register fields for TRBIDR_EL1 Date: Thu, 20 Jun 2024 12:28:05 +0530 Message-Id: <20240620065807.151540-9-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for TRBIDR_EL1 as per the definitions based on DDI0601 2024-03. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ee2038f6f3a3..d057e57d74e7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3098,7 +3098,12 @@ Field 31:0 TRG EndSysreg =20 Sysreg TRBIDR_EL1 3 0 9 11 7 -Res0 63:12 +Res0 63:16 +UnsignedEnum 15:12 MPAM + 0b0000 NI + 0b0001 PMG + 0b0010 IMP +EndEnum Enum 11:8 EA 0b0000 NON_DESC 0b0001 IGNORE --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8F9BA48CCD for ; Thu, 20 Jun 2024 06:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866743; cv=none; b=YpZrL0xqPmUzqzeWcZ1YfFcTPlPjLpbHZzsfUCpSiFNEjD0Jm1e0LvKIQOOoAtEseCXLLagu3TTZ9sguOKksa8Xa1JnEDsqrNqKdXDHwhh1RZdtNb0TYI1urPKg6X9iTUU42Nav6D6rXuQ8hgax0F+5oQEjNQiieoZJ7ge7vx/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866743; c=relaxed/simple; bh=8EpJb52t53rNdx7QuGDxDh+upklfkbthTHecW7nbrbA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r2+Ua+ql9VMGz8iMEF31bz0EQSINFlS7ueA/PzgVfqC3DK2ggp1qy8nEdx20sHBkV9nTn0DcfJuMnguqFsH9WyDq9G30O7SRGp5yQOMRFGsHOvSHAUxYDCCP7R8WHTzgRciurZ01fXJG9vY59vAL4O1rDclPIQTpXiN6rUFu4rQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C8A2ADA7; Wed, 19 Jun 2024 23:59:26 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 64DBD3F73B; Wed, 19 Jun 2024 23:58:58 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 09/10] KVM: arm64: nv: Enable HDFGRTR2_EL2 & HDFGWTR2_EL2 access from virtual EL2 Date: Thu, 20 Jun 2024 12:28:06 +0530 Message-Id: <20240620065807.151540-10-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds VNCR-capable HDFGRTR2_EL2 and HDFGWTR2_EL2 registers into enum vcpu_sysreg and also enables their access from virtual EL2 environment. Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/include/asm/vncr_mapping.h | 2 ++ arch/arm64/kvm/sys_regs.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 36b8e97bf49e..7b44e96e7270 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -488,6 +488,9 @@ enum vcpu_sysreg { VNCR(HDFGWTR_EL2), VNCR(HAFGRTR_EL2), =20 + VNCR(HDFGRTR2_EL2), + VNCR(HDFGWTR2_EL2), + VNCR(CNTVOFF_EL2), VNCR(CNTV_CVAL_EL0), VNCR(CNTV_CTL_EL0), diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index df2c47c55972..de9288bc2b84 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -38,6 +38,8 @@ #define VNCR_HFGRTR_EL2 0x1B8 #define VNCR_HFGWTR_EL2 0x1C0 #define VNCR_HFGITR_EL2 0x1C8 +#define VNCR_HDFGRTR2_EL2 0x1A0 +#define VNCR_HDFGWTR2_EL2 0x1B0 #define VNCR_HDFGRTR_EL2 0x1D0 #define VNCR_HDFGWTR_EL2 0x1D8 #define VNCR_ZCR_EL1 0x1E0 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 22b45a15d068..f921af014d0c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2697,6 +2697,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { EL2_REG_VNCR(VTCR_EL2, reset_val, 0), =20 { SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 }, + EL2_REG_VNCR(HDFGRTR2_EL2, reset_val, 0), + EL2_REG_VNCR(HDFGWTR2_EL2, reset_val, 0), EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), --=20 2.25.1 From nobody Thu Dec 18 05:08:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 32C9247F53 for ; Thu, 20 Jun 2024 06:59:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866748; cv=none; b=UaUPPVo6zZz1bpqVuWy7EO8E1UCpvPjSQsc0K9Nc17SI2e+VHxe09qNKDNI1QlO9Y4S5eFl2kz9o22/9J8U06I/iWqprFlwkQx34A1SLgXpY+gD6GG0UFW0y6/ZxVQ0JtLKbsZaR5ogriKUSOCseSBCa0VjcguYYmWi0o9Zqlnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718866748; c=relaxed/simple; bh=t+0mw7qIdwi4qAz260B1ZFG9jYq0w2o/IK8abKs1pXc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XG3fuTOgF4sH5qytfd2ZA3FR51DshienepMOBNG3xWkAiakHs6Xp8bb6/1pkelnT3QSupxwuaFoiHg3MA4jYq2AE1T5N4qSKAiyQhAKg6q9A6vhTcwoPCENsByyieLBriW/fom6C068gUF5ygRrY0uNumcvZwe+0yYlkVxgjvLA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98DF1DA7; Wed, 19 Jun 2024 23:59:31 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.46.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AE5C33F73B; Wed, 19 Jun 2024 23:59:02 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 10/10] KVM: arm64: nv: Add new HDFGRTR2_GROUP & HDFGRTR2_GROUP based FGU handling Date: Thu, 20 Jun 2024 12:28:07 +0530 Message-Id: <20240620065807.151540-11-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240620065807.151540-1-anshuman.khandual@arm.com> References: <20240620065807.151540-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds new HDFGRTR2_GROUP and HDFGWTR2_GROUP groups in enum fgt_group_id for FGU handling managed with HDFGRTR2_EL2 and HDFGWTR2_EL2 registers. Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/kvm_arm.h | 8 +++++ arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/emulate-nested.c | 14 ++++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 10 ++++++ arch/arm64/kvm/nested.c | 36 ++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 45 +++++++++++++++++++++++++ 6 files changed, 115 insertions(+) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index b2adc2c6c82a..b3fb368bcadb 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -354,6 +354,14 @@ #define __HFGRTR_EL2_MASK GENMASK(49, 0) #define __HFGRTR_EL2_nMASK ~(__HFGRTR_EL2_RES0 | __HFGRTR_EL2_MASK) =20 +#define __HDFGRTR2_EL2_RES0 HDFGRTR2_EL2_RES0 +#define __HDFGRTR2_EL2_MASK (GENMASK(22, 22) | GENMASK(20, 0)) +#define __HDFGRTR2_EL2_nMASK ~(__HDFGRTR2_EL2_RES0 | __HDFGRTR2_EL2_MASK) + +#define __HDFGWTR2_EL2_RES0 HDFGWTR2_EL2_RES0 +#define __HDFGWTR2_EL2_MASK (GENMASK(22, 19) | GENMASK(16, 7) | GENMASK(5,= 0)) +#define __HDFGWTR2_EL2_nMASK ~(__HDFGWTR2_EL2_RES0 | __HDFGWTR2_EL2_MASK) + /* * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any * future additions, define __HFGWTR* macros relative to __HFGRTR* ones. diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 7b44e96e7270..d6fbd6ebc32d 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -239,6 +239,8 @@ enum fgt_group_id { HDFGWTR_GROUP =3D HDFGRTR_GROUP, HFGITR_GROUP, HAFGRTR_GROUP, + HDFGRTR2_GROUP, + HDFGWTR2_GROUP =3D HDFGRTR2_GROUP, =20 /* Must be last */ __NR_FGT_GROUP_IDS__ diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 54090967a335..bc5ea1e60a0a 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -1724,6 +1724,9 @@ static const struct encoding_to_trap_config encoding_= to_fgt[] __initconst =3D { SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1), SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1), SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1), + + /* HDFGRTR2_EL2 */ + SR_FGT(SYS_MDSELR_EL1, HDFGRTR2, nMDSELR_EL1, 1), }; =20 static union trap_config get_trap_config(u32 sysreg) @@ -1979,6 +1982,10 @@ static bool check_fgt_bit(struct kvm *kvm, bool is_r= ead, sr =3D is_read ? HDFGRTR_EL2 : HDFGWTR_EL2; break; =20 + case HDFGRTR2_GROUP: + sr =3D is_read ? HDFGRTR2_EL2 : HDFGWTR2_EL2; + break; + case HAFGRTR_GROUP: sr =3D HAFGRTR_EL2; break; @@ -2053,6 +2060,13 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *= sr_index) val =3D __vcpu_sys_reg(vcpu, HDFGWTR_EL2); break; =20 + case HDFGRTR2_GROUP: + if (is_read) + val =3D __vcpu_sys_reg(vcpu, HDFGRTR2_EL2); + else + val =3D __vcpu_sys_reg(vcpu, HDFGWTR2_EL2); + break; + case HAFGRTR_GROUP: val =3D __vcpu_sys_reg(vcpu, HAFGRTR_EL2); break; diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 0c4de44534b7..b5944aa6d9c8 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -89,6 +89,10 @@ static inline void __activate_traps_fpsimd32(struct kvm_= vcpu *vcpu) case HDFGWTR_EL2: \ id =3D HDFGRTR_GROUP; \ break; \ + case HDFGRTR2_EL2: \ + case HDFGWTR2_EL2: \ + id =3D HDFGRTR2_GROUP; \ + break; \ case HAFGRTR_EL2: \ id =3D HAFGRTR_GROUP; \ break; \ @@ -160,6 +164,8 @@ static inline void __activate_traps_hfgxtr(struct kvm_v= cpu *vcpu) CHECK_FGT_MASKS(HDFGWTR_EL2); CHECK_FGT_MASKS(HAFGRTR_EL2); CHECK_FGT_MASKS(HCRX_EL2); + CHECK_FGT_MASKS(HDFGRTR2_EL2); + CHECK_FGT_MASKS(HDFGWTR2_EL2); =20 if (!cpus_have_final_cap(ARM64_HAS_FGT)) return; @@ -171,6 +177,8 @@ static inline void __activate_traps_hfgxtr(struct kvm_v= cpu *vcpu) update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2); update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2); update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR2_EL2); =20 if (cpu_has_amu()) update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2); @@ -200,6 +208,8 @@ static inline void __deactivate_traps_hfgxtr(struct kvm= _vcpu *vcpu) __deactivate_fgt(hctxt, vcpu, kvm, HFGITR_EL2); __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR_EL2); __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR2_EL2); =20 if (cpu_has_amu()) __deactivate_fgt(hctxt, vcpu, kvm, HAFGRTR_EL2); diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index bae8536cbf00..ebe4e3972fed 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -384,6 +384,42 @@ int kvm_init_nv_sysregs(struct kvm *kvm) res0 |=3D HDFGRTR_EL2_nPMSNEVFR_EL1; set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1); =20 + /* HDFG[RW]TR2_EL2 */ + res0 =3D res1 =3D 0; + + /* FEAT_TRBE_MPAM is not exposed to the guest */ + res0 |=3D HDFGRTR2_EL2_nTRBMPAM_EL1; + + /* FEAT_SPE_FDS is not exposed to the guest */ + res0 |=3D HDFGRTR2_EL2_nPMSDSFR_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR2_EL1, STEP, IMP)) + res0 |=3D HDFGRTR2_EL2_nMDSTEPOP_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, ITE, IMP)) + res0 |=3D HDFGRTR2_EL2_nTRCITECR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, SPMU, IMP)) + res0 |=3D (HDFGRTR2_EL2_nSPMDEVAFF_EL1 | HDFGRTR2_EL2_nSPMID | + HDFGRTR2_EL2_nSPMSCR_EL1 | HDFGRTR2_EL2_nSPMACCESSR_EL1 | + HDFGRTR2_EL2_nSPMCR_EL0 | HDFGRTR2_EL2_nSPMOVS | + HDFGRTR2_EL2_nSPMINTEN | HDFGRTR2_EL2_nSPMSELR_EL0 | + HDFGRTR2_EL2_nSPMEVTYPERn_EL0 | HDFGRTR2_EL2_nSPMEVCNTRn_EL0 | + HDFGRTR2_EL2_nPMSSCR_EL1 | HDFGRTR2_EL2_nPMSSDATA); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) + res0 |=3D HDFGRTR2_EL2_nMDSELR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) + res0 |=3D HDFGRTR2_EL2_nPMUACR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMICFILTR_EL0; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMICNTR_EL0; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, SEBEP, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMIAR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, EBEP, IMP) && + !kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMECR_EL1; + set_sysreg_masks(kvm, HDFGRTR2_EL2, res0 | HDFGRTR2_EL2_RES0, res1); + set_sysreg_masks(kvm, HDFGWTR2_EL2, res0 | HDFGWTR2_EL2_RES0, res1); + /* Reuse the bits from the read-side and add the write-specific stuff */ if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) res0 |=3D (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f921af014d0c..8029f408855d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4110,6 +4110,51 @@ void kvm_init_sysreg(struct kvm_vcpu *vcpu) kvm->arch.fgu[HAFGRTR_GROUP] |=3D ~(HAFGRTR_EL2_RES0 | HAFGRTR_EL2_RES1); =20 + /* FEAT_TRBE_MPAM is not exposed to the guest */ + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nTRBMPAM_EL1); + + /* FEAT_SPE_FDS is not exposed to the guest */ + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nPMSDSFR_EL1); + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR2_EL1, STEP, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nMDSTEPOP_EL1); + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, ITE, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nTRCITECR_EL1); + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, SPMU, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nSPMDEVAFF_EL1 | + HDFGRTR2_EL2_nSPMID | + HDFGRTR2_EL2_nSPMSCR_EL1 | + HDFGRTR2_EL2_nSPMACCESSR_EL1 | + HDFGRTR2_EL2_nSPMCR_EL0 | + HDFGRTR2_EL2_nSPMOVS | + HDFGRTR2_EL2_nSPMINTEN | + HDFGRTR2_EL2_nSPMSELR_EL0 | + HDFGRTR2_EL2_nSPMEVTYPERn_EL0 | + HDFGRTR2_EL2_nSPMEVCNTRn_EL0 | + HDFGRTR2_EL2_nPMSSCR_EL1 | + HDFGRTR2_EL2_nPMSSDATA); + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nMDSELR_EL1); + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nPMUACR_EL1); + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nPMICFILTR_EL0); + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nPMICNTR_EL0); + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, SEBEP, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nPMIAR_EL1); + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, EBEP, IMP) && + !kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D ~(HDFGRTR2_EL2_nPMECR_EL1); + set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); out: mutex_unlock(&kvm->arch.config_lock); --=20 2.25.1