From nobody Fri Sep 20 01:38:08 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91BBD154C10 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=umzA3b9CEKRCk44KmUoCm71Q8dnXpmHLnfU4Raqt5u36stL4OLY6AzzR9ZgDv7wetKJleWbxXzGEL1QSUlLgA/RAOb1XneZyMk7zh1dsIrQJxZFgruxNs2eoqN8WQYNs206E3SFy3ZpWYdjyjiXMc9JnTP0p6kLEtlEPayTmB5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=LoleMKilOwuPwLmC/LdhgUqITJ/pdSPdbm3/goCl4Zk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rM0RLCbuPxWP3W/MBPwe05KgPXW4V6akg21Sg1xHGAZnW1BswB5ZzviBJ9Jy6y0Ig0ZrJFa4TU3x6NFaygwwdoR/cLoSP0ue2ndQ0X/dmf7tsC2OBIGaR4l9s+PB3858MR1e73wibs++xhXBuTHXtUFHnzAxibCt+rc5kzdxiFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MiA6dQAK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MiA6dQAK" Received: by smtp.kernel.org (Postfix) with ESMTPS id 240FCC4AF10; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=LoleMKilOwuPwLmC/LdhgUqITJ/pdSPdbm3/goCl4Zk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MiA6dQAKKFE8/L8GOp2PbbOl8Fqn0D1m7JPy8I3B3yTgSTS10Sp0Ky8jAXG6fLDnc CtGUFz25JpC1DTghM49DGLmVD/e/czO0TaoZrzJDVzus4xnacfiaPu9uS105ogwztY mjv6nbSoeEkDNV4+YeEmvRrlyodDYeB0JHw59zsJ2pj5g0UuEJv6o/tVMT3u4uJzLg K4pEAeu59wmhMeyAhMUteYSEwWp+fRmxaqKDEa6VXkw7tCN31BMYFoF/O6k9o6oT2G H7ftSS6aiEuIRdCRmT1Qw5VO12K/5UybrYhh+9VE2uD6Zz1jNXHFsnY9J0cgqLzYmo svdo0axjSQHqQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A899C27C79; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:46 +0800 Subject: [PATCH v3 06/14] drm/mediatek: Turn off the layers with zero width or height Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-6-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=2189; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=wGHwMPExiceXXoh5WbQFEgnsqBfWnXpyjjWHNk3Kpkw=; b=XLNnzT6sqJHD1GumwbjFvt3T+b65qyk5B+bXwuAWyhxztROzKHD+0bf1dU8PKsfSTpvbdzePO 6CCsO4BZCufBmajDGJWy8xG1fvCAQuag6Fq0HEhYoLiHQaWAbYMDPG9 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195") Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 02dd7dcdfedb..2b62d6475918 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 5c52e514ae30..bf5826b7e776 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -160,7 +160,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (idx >=3D 4) return; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZ= E(idx)); return; } --=20 Git-146)