From nobody Fri Sep 20 01:34:58 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6EA15383B for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=K6jWXEo96YWeams7eUJkc5HTcXjTlhZ1a1OV+40AfQpaKld1nImKUOY6JVVtblD7yUI+z7ND4CWamwG6nBX2p6nGNnTLeGoQy/XYjj1tmuR8yAhH8rDd1pgi4u1BqKIWV5uIzPaSsFSIS18Eut/h+cJojIvfDTmMAg7nnqJE5vI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HILV5XvG/KyhrltLj5VuHvVEXYq8kRnLtncec/2dqmw94LkgBpTwUCO6a/JSKhU3moFlibptu+03OhZ9FO71GFJCO/Nak4wwqw9+ij7WhJ0eMulZW/Sz6/ranrU2HMeQsaInuIgCS4S9PWEbD+kbXChKQY22oRQxzwAQSQCRif4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o9I6UWAR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o9I6UWAR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0BB96C4AF0B; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=o9I6UWARKhdQAarnE3m6YUch84ybDp4BeEm27PI45HX+rqb3jBMMzIH8Jhmb/9N40 TMn9s/1qGLUVAT2iJqPDthvSqAWKpL/bwDsWlEIiz4GYSo7bzxbaCpx9FTwJfmbznI RXOdGE/jQhdQ4etIjuATVNnA/8hpz4Z9ca0sAwgXm009zp8i7VQLoXM19wJSwR+RmE 4p0gfvPmsYDh1VrFvf4uEqtjIqYjlE1n7HRzl4ck0cuhEGSzHr4qfhz1K35ANGe9jr aW+Ub066hVO1sz8xnZbtX6awgpNObVsowN9+Hc5Uvo4Y9uyG1UkUH14xeV4dM68pCP L4gFKOOVOTApw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01532C27C53; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:44 +0800 Subject: [PATCH v3 04/14] drm/mediatek: Fix XRGB setting error in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-4-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=1806; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=iVCN8PnNVHs904I6AJ55kOr+V0K7XkkYFUBoVjBPemw=; b=YGUI6RWS0nP5fpjX4gax+ewcdTiGdFlfVwGr3KMmRMoWefuqd/Ov64zpSE37WmTC6fSVlfMee Ual5RWvPhOuAj9ENdQSkMcZOMniEGfqK685rChC26tStrwq1vx0UuNA X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Although the alpha channel in XRGB formats can be ignored, ALPHA_CON must be configured accordingly when using XRGB formats or it will still affects CRC generation. Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index d7d16482c947..5c52e514ae30 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -153,6 +153,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, unsigned int offset =3D (pending->x & 1) << 31 | pending->y << 16 | pendi= ng->x; unsigned int align_width =3D ALIGN_DOWN(pending->width, 2); unsigned int alpha_con =3D 0; + bool replace_src_a =3D false; =20 dev_dbg(dev, "%s+ idx:%d", __func__, idx); =20 @@ -167,7 +168,15 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (state->base.fb && state->base.fb->format->has_alpha) alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, + if (state->base.fb && !state->base.fb->format->has_alpha) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a =3D true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); --=20 Git-146)