From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6AA15382F for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=C7ZwYfRYt4Pi3D0HROGTbijywB180lBZLkWaYl5iEz4dFcSYh+gsCdnlOH7rU6rYOral3SnqwERrzipTMQA6kDmbbt+wBrxsaOnQZeIpQp6GDk6zNO2Fcfg2d6VHCtIGW4n23RUE2fvTyEhRT9ylNTeNw8wwvZa12JUfr/t8dn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=uJgeqwP/exRsycFcCMLfCia6ha45FbjhfAs5Cm1rATQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eIoy4TvL4PTsJgouQGhUCrGGuQ0ddwN60/ZvPzhEqpFsAzxB3Ixqq44AbANPPYyDl3JaNBT4MCI4T3/Z7gIor/qtBjqdtDsnJkTYZoczyKrC30m61v3D+2tffzZ7139ohVB+IGvtml/AEa8Ffr3moGdyKXbvPc3Yr3BIrxIYVfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WHmnph4a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WHmnph4a" Received: by smtp.kernel.org (Postfix) with ESMTPS id DFFD4C4AF07; Wed, 19 Jun 2024 16:38:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815124; bh=uJgeqwP/exRsycFcCMLfCia6ha45FbjhfAs5Cm1rATQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WHmnph4amcaY3GfLeDR1eUYN4FOFsPdlSYYI5hal8Is3/aCkVW7cuW5a4bYjwHard mrhglBL4dxpwBc5dwuYAoW9GYTjhxyUffC20uNUmhJ9sqi0tYki+fAyeTUIwMWD2yx 33PHuKtmvH2cIoEpqQK9JXW2usRXuMaEv8EVF+V5GdaZwrryXCH3afYyBlKs3ICxre y0/9ASkPo5aC1Fp1Z0RGvCNSPEvh9uV7ygtRn6irSkBi/wKLsV9NZhr7CGKE73eGzH 71WpJa/zGdw6tTPpOvhS8XSHny5l2tyXXVjsCdqgzyFbiwlL2s7uTShTtCW4fPl263 +T0NKpyBEx1bw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6946C2BA15; Wed, 19 Jun 2024 16:38:44 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:41 +0800 Subject: [PATCH v3 01/14] drm/mediatek: Add missing plane settings when async update Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-1-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=1161; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=oPP96bMpAu5gtyCGtIUYUgi5lQMG+4ahEDxfcNXlQWw=; b=aMX6/BSIN7JysnkjWbvbGbARLC0zI6CsR4P/4GAqmooXFrLDIkTnz7LfJexu6dNKd54tnNod6 p2L3pPUYAEtBOPm5E9BonxPxZX8LBHmEQDSAJEBM0vDB2NrCIM6tHyl X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Fix an issue that plane coordinate was not saved when calling async update. Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic up= date") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_plane.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 4625deb21d40..a74b26d35985 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -227,6 +227,8 @@ static void mtk_plane_atomic_async_update(struct drm_pl= ane *plane, plane->state->src_y =3D new_state->src_y; plane->state->src_h =3D new_state->src_h; plane->state->src_w =3D new_state->src_w; + plane->state->dst.x1 =3D new_state->dst.x1; + plane->state->dst.y1 =3D new_state->dst.y1; =20 mtk_plane_update_new_state(new_state, new_plane_state); swap(plane->state->fb, new_state->fb); --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B666153820 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=c0NskhdZ+iv0M59jDV3EaGaEQgoA8U6xuzupIUqB+o2YtgFKbLt3Hg8HmxfZ+kwvvDxH5Bnmv3sH3SnzBr33+9ignj6n4hBBMzSpsDhHdjE0TSMm9yz8a4SdzlGOOIBwYvHLXIMTE9qMHgzz/B3I9cU3nO4YSAbC+CXjvKGtVv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=ZJmYvkWyDQXkVIDz4EYMvvkEgoGgO/o3I8+tANsq22s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FGI9wCWTElodbtMxYm2EbRhlhTraX69bnGMKnrkCRc7IQ2dnhAqlLaTPw2wpuc+2tJUyDVm4VGsDWFwZn4bEUsBpsyalCRIiM47gkmcxW1jqYZzK9HTISf4uda7v9vopfHIAYF2O9KMbwssZKZhKI89LzPFppL3c/Q4wZC8U8II= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h4aGWKHG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h4aGWKHG" Received: by smtp.kernel.org (Postfix) with ESMTPS id ECCC9C32786; Wed, 19 Jun 2024 16:38:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=ZJmYvkWyDQXkVIDz4EYMvvkEgoGgO/o3I8+tANsq22s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=h4aGWKHG9lNs8tPkSgbQhaVtmHWxRIY+548H6PRQugZTomVEvRjznLDA3+F4pgshr K+wBMQ4nqE46ZyZ11rDKK3bUSaZmuOeKk+ajaR25cR9/Yz9mnDZcYtlgttrgxYNA0A Yzw6YRvShjDJdFtcm+rCVOOJiOkv+H+6iUh2U/kV1PbGCX/fndVpoDoKdNgAdDRMcI PUTZ4hqEw3vg3NkgaZdG8jkiEEff3UyyOURr5PC7W/zLPKDuPza85IJKGOLCKTMaVq C/PM+DgJ6NesgK+VlEehAMyJq87OcpthdR4x/he2ynZVwkpK8e0CIugtZ6yIfZAkjH Q29oO6zU9hyUA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4A38C2BB85; Wed, 19 Jun 2024 16:38:44 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:42 +0800 Subject: [PATCH v3 02/14] drm/mediatek: Use 8-bit alpha in ETHDR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-2-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=1391; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=7umBnacXHY95A+TiUODUrNhd3bD2WRNrF+DOB/ds4t8=; b=BMG77zft9eH3Te3rgMGiWvej9yoe0q1+9thWcfprzf6tjSNlo1Ze6n2dxH1SlPwrT5Ds80vNk 7dZANunCC3LDuyQwcnlkz8iM7TznwAYRWuGA01zflm7nBwNyx7NYg/4 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung 9-bit alpha (max=3D0x100) is designed for special HDR related calculation, which should be disabled by default. Change the alpha value from 0x100 to 0xff in 8-bit form. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 156c6ff547e8..d7d16482c947 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -50,7 +50,6 @@ =20 #define MIXER_INX_MODE_BYPASS 0 #define MIXER_INX_MODE_EVEN_EXTEND 1 -#define DEFAULT_9BIT_ALPHA 0x100 #define MIXER_ALPHA_AEN BIT(8) #define MIXER_ALPHA 0xff #define ETHDR_CLK_NUM 13 @@ -169,7 +168,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, - DEFAULT_9BIT_ALPHA, + MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); =20 --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B61B15381C for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=V46WqS/RzodaXbKNZ7WovAEXTyG7igF4p1rizRUHtlyVgQb20HpDGNwN3Bo73T6lf0ZybDoLmbc5jdcD45bUu8Zlc333g/dYWqPG2sG0KhUQn1IVGko1KFN5cHwqHdT9bexgrvs6SH2kl3ulTm/0UN0v9R/L1UpCEZiLXz2az7g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=xSG4ggt1RhnwKCcON3d27r3nTFdYl7HIbvQnOx2vw8k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Mjf8d9O/oDTA+5MEROuaW+bNM0LApCGmsjZp59mWhRFDeqzDo/5UnABbJ8c4VEm3LGErlyWzh+iR0JSA9GfoNAb72dv00dimp8GZpt/I+Mt8acvdEPzj56oLzuZzXkEFHT5d2XuUeZZ6seD8r0Gu4hn3DhcmcbNWTdhw5k5GL6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bl3G9snK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bl3G9snK" Received: by smtp.kernel.org (Postfix) with ESMTPS id 00FACC4AF08; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=xSG4ggt1RhnwKCcON3d27r3nTFdYl7HIbvQnOx2vw8k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bl3G9snKqjqTGeG9FX/zecd2iI9EyKYX2189ZAAKN+rF0rfyO5lArarEjXZmAPA8C BKU8oU4S+pWCXQtB0MWJ4W30/Uxvfs4rpH1f+PTytAUZDtQQqN3JUXQH+7grXVc6Cl vrZGNata8beMjsT16beARoNhjTAcT4V2nSFkm3DtNJYovS+Va0qcs3Sa6hUFmzwR86 z3gBwqiZ96qUH2VCzT15engblRFcUcxiSmX8uebE2R18HOamxd8oaY22uRAS/lQmmr wxf2fJvpM5kLZmPcIi4PU+YEcJrQhkf+VRL5u/uVg+cmZkL9pGRkC3vpY2L4MAzOE8 GiTvdNGsP8TcQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3EACC27C79; Wed, 19 Jun 2024 16:38:44 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:43 +0800 Subject: [PATCH v3 03/14] drm/mediatek: Fix XRGB setting error in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-3-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=2960; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=tCYJPhSGMKi5TJvgnmhbxfJqIw69++3CeCs9woVV0N0=; b=Rs83718Z3zztNmQ9WkKuT6TY6jbpWGPvBjC7/cPk3tDc7CIrec9Wdz4JY6hXerbH/+gbiTJvf JK5pXgL8la1B8ik7mEasC4pAfDedsHLR1ioJYc7zSoxax5tcUDwGHb1 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung CONST_BLD must be enabled for XRGB formats although the alpha channel can be ignored, or OVL will still read the value from memory. This error only affects CRC generation. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index b552a02d7eae..bd00e5e85deb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -38,6 +38,7 @@ #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) +#define OVL_CONST_BLEND BIT(28) #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 @@ -407,6 +408,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; union overlay_pitch { @@ -428,6 +430,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, if (state->base.fb && state->base.fb->format->has_alpha) con |=3D OVL_CON_AEN | OVL_CON_ALPHA; =20 + /* CONST_BLD must be enabled for XRGB formats although the alpha channel + * can be ignored, or OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (state->base.fb && !state->base.fb->format->has_alpha) + ignore_pixel_alpha =3D OVL_CONST_BLEND; + if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; addr +=3D (pending->height - 1) * pending->pitch; @@ -443,8 +453,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq= _reg, ovl->regs, - DISP_REG_OVL_PITCH(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pi= xel_alpha, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6EA15383B for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=K6jWXEo96YWeams7eUJkc5HTcXjTlhZ1a1OV+40AfQpaKld1nImKUOY6JVVtblD7yUI+z7ND4CWamwG6nBX2p6nGNnTLeGoQy/XYjj1tmuR8yAhH8rDd1pgi4u1BqKIWV5uIzPaSsFSIS18Eut/h+cJojIvfDTmMAg7nnqJE5vI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HILV5XvG/KyhrltLj5VuHvVEXYq8kRnLtncec/2dqmw94LkgBpTwUCO6a/JSKhU3moFlibptu+03OhZ9FO71GFJCO/Nak4wwqw9+ij7WhJ0eMulZW/Sz6/ranrU2HMeQsaInuIgCS4S9PWEbD+kbXChKQY22oRQxzwAQSQCRif4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o9I6UWAR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o9I6UWAR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0BB96C4AF0B; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=o9I6UWARKhdQAarnE3m6YUch84ybDp4BeEm27PI45HX+rqb3jBMMzIH8Jhmb/9N40 TMn9s/1qGLUVAT2iJqPDthvSqAWKpL/bwDsWlEIiz4GYSo7bzxbaCpx9FTwJfmbznI RXOdGE/jQhdQ4etIjuATVNnA/8hpz4Z9ca0sAwgXm009zp8i7VQLoXM19wJSwR+RmE 4p0gfvPmsYDh1VrFvf4uEqtjIqYjlE1n7HRzl4ck0cuhEGSzHr4qfhz1K35ANGe9jr aW+Ub066hVO1sz8xnZbtX6awgpNObVsowN9+Hc5Uvo4Y9uyG1UkUH14xeV4dM68pCP L4gFKOOVOTApw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01532C27C53; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:44 +0800 Subject: [PATCH v3 04/14] drm/mediatek: Fix XRGB setting error in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-4-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=1806; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=iVCN8PnNVHs904I6AJ55kOr+V0K7XkkYFUBoVjBPemw=; b=YGUI6RWS0nP5fpjX4gax+ewcdTiGdFlfVwGr3KMmRMoWefuqd/Ov64zpSE37WmTC6fSVlfMee Ual5RWvPhOuAj9ENdQSkMcZOMniEGfqK685rChC26tStrwq1vx0UuNA X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Although the alpha channel in XRGB formats can be ignored, ALPHA_CON must be configured accordingly when using XRGB formats or it will still affects CRC generation. Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index d7d16482c947..5c52e514ae30 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -153,6 +153,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, unsigned int offset =3D (pending->x & 1) << 31 | pending->y << 16 | pendi= ng->x; unsigned int align_width =3D ALIGN_DOWN(pending->width, 2); unsigned int alpha_con =3D 0; + bool replace_src_a =3D false; =20 dev_dbg(dev, "%s+ idx:%d", __func__, idx); =20 @@ -167,7 +168,15 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (state->base.fb && state->base.fb->format->has_alpha) alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, + if (state->base.fb && !state->base.fb->format->has_alpha) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a =3D true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 830FE154BE5 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=IYQvWh2DxwCQCFijMvNWMLJLvL7GIYn/NPPoEMBkGPOATu6lwlsneBLL4Ld/zqX6n+1NAixE+Bl7UFkcXox5HlcgHMkk8ZDBb3SO2kigO3/aEXUEns+Q6Xz7C02Dd5E+Bg8PDi+WF/AbGeOXws9CoEIsMaZw3cFBQf4Ep+1TUcI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=QFJzZ2f8/HswaPFNTTO8YkFgvDDXRL8Qp41YYaAOvug=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N8mOKayN2QRpnhRF/sh0bHU8dmkvfbxWf4j/BWry3SHWBGQjk+QgGozPTxziC+vgxx3Fhr96QwTprDl9T4yTyYuZ6yh+xtPxgI2aQwrAJh3sBnCYCycbjGJoEag1mfsDTHtF0wh3+wMc+tiXx2rsbhSuWu1U2XN5L4S2vSiy9J8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MT+yBYIu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MT+yBYIu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1CEB8C4AF0E; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=QFJzZ2f8/HswaPFNTTO8YkFgvDDXRL8Qp41YYaAOvug=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MT+yBYIuVNZ7cmjAI2XU4w5cMbPBYD3vj6rdg0cHG5Dmk7tWYhQUZYSDQjIPeL7Eg Rq0gYVWubH5T+iqTZKYcxbW3/ZWHGzanjNvS5gpjrYOWlTXGHFGz2s492sUdSLRUlG faWngpulACBpUZcrxjA6dM4Zq1pYEuxX9KByHRbyZeB/vrenS+Q0k0aacDiYCsOSsh tAXla22HzGPi/mPSoq2ty0SlNMshf2SXIOCzBYyv/2znfb5neGKoLwz98sEoHTFpsJ XEJeQwC+CJg4/+9pIp0dNo1Kpj5SPiHEso/Aeh1TJ3QQn+ZbwRNiX+DAt6gw8lTwW3 yqUlSaA051y5g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EB5EC2BC81; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:45 +0800 Subject: [PATCH v3 05/14] drm/mediatek: Fix destination alpha error in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-5-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=2135; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=rAChFGdFoC8c4exvZmv1sFfltc3v4bPxNFkorgTlPyw=; b=/nzXSR2LT5b/JzbTE2HsfTlQ/Sm2B6QzhhZM9OPWslO+9oQ2A2nd0ih+48/0SEhG0JZdjIBLk 3pmcNsQCRI9B/t1R4U1FwCFw8IPjG3kbqaZJp18j8KDwqTYzHAeEjFT X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung The formula of Coverage alpha blending is: dst.a =3D dst.a * (0xff - src.a * SCA / 0xff) / 0xff + src.a * SCA / 0xff dst.a: destination alpha src.a: pixel alpha SCA : plane alpha When SCA =3D 0xff, the formula becomes: dst.a =3D dst.a * (0xff - src.a) + src.a This patch is to set the destination alpha (background) to 0xff: - When dst.a =3D 0 (before), dst.a =3D src.a - When dst.a =3D 0xff (after) , dst.a =3D 0xff * (0xff - src.a) + src.a According to the fomula above: - When src.a =3D 0 , dst.a =3D 0 - When src.a =3D 0xff, dst.a =3D 0xff This two cases are just still correct. But when src.a is between 0 and 0xff, the difference starts to appear Fixes: 616443ca577e ("drm/mediatek: Move cmdq_reg info from struct mtk_ddp_= comp to sub driver private data") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index bd00e5e85deb..693560fa34e8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -72,6 +72,8 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) =20 +#define OVL_COLOR_ALPHA GENMASK(31, 24) + static const u32 mt8173_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -274,7 +276,13 @@ void mtk_ovl_config(struct device *dev, unsigned int w, if (w !=3D 0 && h !=3D 0) mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_= OVL_ROI_BGCLR); + + /* + * The background color must be opaque black (ARGB), + * otherwise the alpha blending will have no effect + */ + mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_ROI_BGCLR); =20 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91BBD154C10 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=umzA3b9CEKRCk44KmUoCm71Q8dnXpmHLnfU4Raqt5u36stL4OLY6AzzR9ZgDv7wetKJleWbxXzGEL1QSUlLgA/RAOb1XneZyMk7zh1dsIrQJxZFgruxNs2eoqN8WQYNs206E3SFy3ZpWYdjyjiXMc9JnTP0p6kLEtlEPayTmB5A= ARC-Message-Signature: i=1; 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b=MiA6dQAKKFE8/L8GOp2PbbOl8Fqn0D1m7JPy8I3B3yTgSTS10Sp0Ky8jAXG6fLDnc CtGUFz25JpC1DTghM49DGLmVD/e/czO0TaoZrzJDVzus4xnacfiaPu9uS105ogwztY mjv6nbSoeEkDNV4+YeEmvRrlyodDYeB0JHw59zsJ2pj5g0UuEJv6o/tVMT3u4uJzLg K4pEAeu59wmhMeyAhMUteYSEwWp+fRmxaqKDEa6VXkw7tCN31BMYFoF/O6k9o6oT2G H7ftSS6aiEuIRdCRmT1Qw5VO12K/5UybrYhh+9VE2uD6Zz1jNXHFsnY9J0cgqLzYmo svdo0axjSQHqQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A899C27C79; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:46 +0800 Subject: [PATCH v3 06/14] drm/mediatek: Turn off the layers with zero width or height Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-6-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=2189; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=wGHwMPExiceXXoh5WbQFEgnsqBfWnXpyjjWHNk3Kpkw=; b=XLNnzT6sqJHD1GumwbjFvt3T+b65qyk5B+bXwuAWyhxztROzKHD+0bf1dU8PKsfSTpvbdzePO 6CCsO4BZCufBmajDGJWy8xG1fvCAQuag6Fq0HEhYoLiHQaWAbYMDPG9 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195") Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 02dd7dcdfedb..2b62d6475918 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 5c52e514ae30..bf5826b7e776 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -160,7 +160,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (idx >=3D 4) return; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZ= E(idx)); return; } --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78EAD15442F for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-7-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=1129; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=mOuE7odjWvJz++xtcQ1qyetBOiaSUZbqiZM9+aN0j54=; b=RnVS8lxJ2hbgfxMuJ8FfxIhXzI/RE5/P4ANTqoO+t9BzCLSfR+RUVSyrJvEiMeDYDURJSeBSs 6IjpIle5w6nAl52cP8MESwBMPqE2AKldyXQh93P80Ya8A+xi0vvRB+i X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Add OVL compatible name for MT8195. Without this commit, DRM won't work after modifying the device tree. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index b5f605751b0a..8e047043202b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -743,6 +743,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8192-disp-ovl", .data =3D (void *)MTK_DISP_OVL }, + { .compatible =3D "mediatek,mt8195-disp-ovl", + .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8183-disp-ovl-2l", .data =3D (void *)MTK_DISP_OVL_2L }, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78F30154444 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=D1OR0obSrAsuxci5SA1ZXk7gxs+qiqV28pPjmp5+94jUJ9My6Fi8CllYn2SYsx1DucwMjSeXnNeFCtrZ2tNTALnGBm52tQ/2T9ftF0BC9uOGbqyXH0Eipb3KHxPJsNog0v28AkHg4Rnv2L/NxIE9qqNndRofr1xzERAU9oJDq6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=4LYPNJKhSIVl19gSuHAdj1ek37yibjwzba9sVqoFJcs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jlVbuhve7mrFbL+1r2JywJvcwP9rPUQgtbg20bWp/De82FjZNrtboQD1iJqLTktHZw4nspj96QUikzMhzYv/AZ1LJ03DE45fooolEm+W2+mVjYiX44pYiZ0Xe5e1tYNe9/Mty+gxGPRK3crJFaVkEt0eKJXa4LO6/6Jijce1RYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MRUomzEz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MRUomzEz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3F0B3C4AF0D; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=4LYPNJKhSIVl19gSuHAdj1ek37yibjwzba9sVqoFJcs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MRUomzEz63kXZYNxw79cLwTvHBP6Yzj3lwVmM8Z3CXrNrZDrGQRUryFGWbbIGAJyy iVGWUUAJ++xLDhHF3jtyh5f6DZwfjv7SCesPCUrP2Pp5iHJzYhtHXbnsYz4GpiEwyD nZabFLwscZp98ESaY8hNDNSiD1Yms0lNMxomuZvorTiC6h5dsraEwI51OvvbWBvtcO iwds/km4NakUV+d0saY3s9cU+5oSMYjnuir0RmxYKAK43BPGqgAjzBZr4H6ES6yNDe I4jB3c1fUxR4GilD5IB5cHzIwu/yZEw/pJcCyAiRDCyeBWJuMV+YrZPsmhUxGx1K68 vosXqquaiADQQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35940C2BA15; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:48 +0800 Subject: [PATCH v3 08/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-8-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=3111; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=/M2U/dR6ucdwMKfOXnye/OeldOEgodQx+RADOj27AnI=; b=lsHPefHZqPBKtWAwrhbcX4i0kMY6fYZEiq71EfBUTFzf+fbda0B8CAb7qnpLB2fdVZbqgw6u4 oTGc3WQrEtbB6s7iHsPEAaxvIm2xtpe5xXoa/m1gt1i2cTX9ueJvp40 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Always add DRM_MODE_ROTATE_0 to rotation property to meet IGT's (Intel GPU Tools) requirement. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 6 +++++- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------ drivers/gpu/drm/mediatek/mtk_plane.c | 2 +- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 26236691ce4c..f7fe2e08dc8e 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -192,7 +192,11 @@ unsigned int mtk_ddp_comp_supported_rotations(struct m= tk_ddp_comp *comp) if (comp->funcs && comp->funcs->supported_rotations) return comp->funcs->supported_rotations(comp->dev); =20 - return 0; + /* + * In order to pass IGT tests, DRM_MODE_ROTATE_0 is required when + * rotation is not supported. + */ + return DRM_MODE_ROTATE_0; } =20 static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 693560fa34e8..26b598b9f71f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -305,27 +305,20 @@ int mtk_ovl_layer_check(struct device *dev, unsigned = int idx, struct mtk_plane_state *mtk_state) { struct drm_plane_state *state =3D &mtk_state->base; - unsigned int rotation =3D 0; =20 - rotation =3D drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - rotation &=3D ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) !=3D 0) + /* check if any unsupported rotation is set */ + if (state->rotation & ~mtk_ovl_supported_rotations(dev)) return -EINVAL; =20 /* * TODO: Rotating/reflecting YUV buffers is not supported at this time. * Only RGB[AX] variants are supported. + * Since DRM_MODE_ROTATE_0 means "no rotation", we should not + * reject layers with this property. */ - if (state->fb->format->is_yuv && rotation !=3D 0) + if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) return -EINVAL; =20 - state->rotation =3D rotation; - return 0; } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index a74b26d35985..1723d4333f37 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -338,7 +338,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_p= lane *plane, return err; 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Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:49 +0800 Subject: [PATCH v3 09/14] drm/mediatek: Add new color format MACROs in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-9-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=2232; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=KGjuxOTeaeQJ/coPucc6FKKJb8sUdPSBSXtke+B/fBI=; b=mJ+gW1gLHwshZkTbNUY0XOFyBs9HlcB+VSxqO8CA7iGj7RSicbr/TuWM20n/lxPNEDWvsxfVy O55Q/YzWXewAUBMR/GanirV+8UZWJ5+iI4MiPExVovcW6LwyokP7FIl X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Define new color formats to hide the bit operation in the MACROs to make the switch statement more concise. Change the MACROs to align the naming rule in DRM. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 26b598b9f71f..33c332b29381 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -55,8 +55,10 @@ #define OVL_CON_BYTE_SWAP BIT(24) #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB (1 << 12) -#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) -#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_ARGB8888 (2 << 12) +#define OVL_CON_CLRFMT_RGBA8888 (3 << 12) +#define OVL_CON_CLRFMT_ABGR8888 (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SW= AP) +#define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SW= AP) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -377,18 +379,18 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: - return OVL_CON_CLRFMT_ARGB8888; + return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: case DRM_FORMAT_BGRA1010102: - return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_CLRFMT_BGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ARGB2101010: - return OVL_CON_CLRFMT_RGBA8888; + return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: - return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_CLRFMT_ABGR8888; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5A86155C83 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=M6OUPz7Pvw7+JT+dw3eDcSNkswM+ULCOYA3D25s2+ck78mITGEKdHqgmGwXFCJSZhxm/4KAHcKwpoAfl2TD90CoHCJX/M+dm5z4lTdQUvEv1coCL2lq3lU2dO3zqQTY2PfmGdVUeLCCQqx4bZfTASRrHdSEO0Zn6rimHHXz1gZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=Eu9A0/ITfQbhuHN1wINLeIGnV+BDBlF/kN0wOMMPbDo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A78gih/bEki2dug5/MyWHCYJiBiJmz5mwkUSRngnewNPMcJWNnNegEEebNfn6uZaHg6fQYY2/VbbZVw/3G/EJvxd170Cxcgc7eUsr/sKo9/KqjzzfYJUVJ9ovHaO9vfxkQ0NOWrLtjZbrjBMGJ4O1Anyb+kehgqq5aWPKKjg5Tg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KFSRExqe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KFSRExqe" Received: by smtp.kernel.org (Postfix) with ESMTPS id 572D0C4AF09; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=Eu9A0/ITfQbhuHN1wINLeIGnV+BDBlF/kN0wOMMPbDo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KFSRExqewZrkbfvLAWKo3FSLV4qUKonryLq88DjSbAvNjP1Av5EfjYpW9a4GwD9qz 5RrOtNIGRGyW5xuYhJGCG6madtqt3ndm+AD5qvFkpWHo0AsynlnaVX2syvoM96vbL4 4AcDYNy9y/V9nGb4pEVDef/yEFTcD/EwxfL7dv1U0Ym+O6s/wOsgNeiH9NARVWasrh wFFEz4WJE0Hdv4ME22ALANOnCDxRQXH4L/Z2Ol0XtxYaxJFN914gkp3MTe2tkLJyZu QEBI6vl1798n9u/icoYH3IBLt/7eSrc4KLof4pwFygcUxhQV6d49dOa9cl/VieBH9C uekXWfRi2IRnQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EBDAC2BC81; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:50 +0800 Subject: [PATCH v3 10/14] drm/mediatek: Set DRM mode configs accordingly Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-10-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=3617; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=m0EG3CktaVu4W67UszRONTV4/7xw5TYqkuXRJdICaFc=; b=TMj8/v0fTr1m458crp3qdNkIRDjZE/hOgBhE1U4mPkyPWXfnTsF/rjbzDR+3fY+xHx26Jv5PZ E/Jj6LV9LfqD9A2eNCX8HH3snv4DnANhqhcN6cUx+WKAwVFL1tUpaAn X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Set DRM mode configs limitation according to the hardware capabilities and pass the IGT checks as below: - The test "graphics.IgtKms.kms_plane" requires a frame buffer with width of 4512 pixels (> 4096). - The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is defined, and run the test with cursor size from 1x1 to 512x512. Please notice that the test conditions may change as IGT is updated. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 8e047043202b..c9cad3a82737 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -294,6 +294,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .conn_routes =3D mt8188_mtk_ddp_main_routes, .num_conn_routes =3D ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { @@ -308,6 +311,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 0_driver_data =3D { .main_path =3D mt8195_mtk_ddp_main, .main_len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data =3D { @@ -315,6 +321,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 1_driver_data =3D { .ext_len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), .mmsys_id =3D 1, .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 2, /* 2-pixel align when ethdr is bypassed */ + .min_height =3D 1, }; =20 static const struct of_device_id mtk_drm_of_ids[] =3D { @@ -493,6 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm) for (j =3D 0; j < private->data->mmsys_dev_num; j++) { priv_n =3D private->all_drm_private[j]; =20 + if (priv_n->data->max_width) + drm->mode_config.max_width =3D priv_n->data->max_width; + + if (priv_n->data->min_width) + drm->mode_config.min_width =3D priv_n->data->min_width; + + if (priv_n->data->min_height) + drm->mode_config.min_height =3D priv_n->data->min_height; + if (i =3D=3D CRTC_MAIN && priv_n->data->main_len) { ret =3D mtk_crtc_create(drm, priv_n->data->main_path, priv_n->data->main_len, j, @@ -520,6 +538,10 @@ static int mtk_drm_kms_init(struct drm_device *drm) } } =20 + /* IGT will check if the cursor size is configured */ + drm->mode_config.cursor_width =3D drm->mode_config.max_width; + drm->mode_config.cursor_height =3D drm->mode_config.max_height; + /* Use OVL device for all DMA memory allocations */ crtc =3D drm_crtc_from_index(drm, 0); if (crtc) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 78d698ede1bf..ce897984de51 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,10 @@ struct mtk_mmsys_driver_data { bool shadow_register; unsigned int mmsys_id; unsigned int mmsys_dev_num; + + u16 max_width; + u16 min_width; + u16 min_height; }; =20 struct mtk_drm_private { --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5ACA155C88 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-11-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=2982; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=VYe2wP07/kjaGGRWdu9nnYY2/AwgAqg6ZWQZL457sn0=; b=1J86WIQwN6L5+6SMHDONDSilK4wTfVrjkyNvS+OEgzz5NIkEE0ck/BvrVC++ue3ZHdMkRzh7+ Yp5UQrTfIObBCQY3x4KLY2supMPkkWH3ZGOCQqfF31I8igibu4l9aWY X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support more 10bit formats in OVL. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +++++++++++++++++++++++++++++= --- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 33c332b29381..767338206780 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -76,6 +76,22 @@ =20 #define OVL_COLOR_ALPHA GENMASK(31, 24) =20 +static inline bool is_10bit_rgb(u32 fmt) +{ + switch (fmt) { + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + return true; + } + return false; +} + static const u32 mt8173_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -93,12 +109,18 @@ static const u32 mt8173_formats[] =3D { static const u32 mt8195_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX1010102, DRM_FORMAT_BGRA1010102, DRM_FORMAT_ABGR8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX1010102, + DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, DRM_FORMAT_RGB565, @@ -258,9 +280,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, i= nt idx, u32 format, reg =3D readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); reg &=3D ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); =20 - if (format =3D=3D DRM_FORMAT_RGBA1010102 || - format =3D=3D DRM_FORMAT_BGRA1010102 || - format =3D=3D DRM_FORMAT_ARGB2101010) + if (is_10bit_rgb(format)) bit_depth =3D OVL_CON_CLRFMT_10_BIT; =20 reg |=3D OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); @@ -379,17 +399,23 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_BGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: return OVL_CON_CLRFMT_ABGR8888; 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Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:52 +0800 Subject: [PATCH v3 12/14] drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-12-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=920; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=NNek4fczNw9y3anmAELzLLOsbkQDIWEXnqDftyXPIKc=; b=L4LJnpsi/Uyl4YnnTuIjtET3CKtDN9lZ49OkTJ8RnvZ0VdCUDJh1YFO2FdQg2L5cqKofESSN8 K8dDBj+9NJcD2JgiqzOOnJMviXP0rzs4LVJQkXYUwMszkf4RXCsI2Hs X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support RGBA8888 and RGBX8888 formats in OVL on MT8195. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 767338206780..943db4f1bd6b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -119,6 +119,8 @@ static const u32 mt8195_formats[] =3D { DRM_FORMAT_XBGR8888, DRM_FORMAT_XBGR2101010, DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX1010102, DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2E4A1552E4 for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=dmNl/uW8iwniJrRTZt0YJpRymXs1ezO5MDtfJKSzRjdtOa7GihWAnDfIoY8atrppjd5rcokK3qqBhqjY123Iue8g1I7ITyCApUJPRDsVkH1Ab1cW68JPrPtgRa8V8cxWA2iJaFrb+qtgc5lpt2QskyNYQDcdm01yFqLRfiTf3VY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=Zr9NDsq7PgN7FZcmmMvcG9xbkaiZgoKF0Pjn/kMasDo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AnX6FFBbdk/nRYKW7xwBJdDqu2M/Fx56Hrn3SU3MJlYAFc1fprFfCGKFkoU8XLcyFZ4fs/QFfUWWrrKKHmNlEdrm0ZggxPrRqd6fH+VuFq/4bRz+w7jAlP0QStAHiZ3OKEnlY68QVIOUDXqQlf9C/HfjNC30jm8GRG8pGUcYWkU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fRaKuPxX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fRaKuPxX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 82AE4C4AF1B; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=Zr9NDsq7PgN7FZcmmMvcG9xbkaiZgoKF0Pjn/kMasDo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=fRaKuPxXvGl2Mjo2jeS/peKbK6rxV2eA08bhPkcGigAHdGDP+GbYJWQkhRDiQB8cd jfCLIb/hFfWtSNwPMrE+jtvXrNs0mDIlg2QC4vhvObwxcXPnVXpGzwfBFszQGot3Oo 0z13Zmaop9DP9nF+GMylYiOehmpbqgpTfLa4MeY+DNJihBCFtwjxgBJaf5uhm8939O 3krJy2EBDo/yw2oD9zi5iv0OPQ5bqLm+UApevBvH1jOhSm/c2HFVFsvDQBZIpMUzV2 tT0uLjevctdFO4ssW0Zd6D6oAviISS8U5zthf4x1EH/dOMZu496i3rYvZMnJLIzpmN j2KwENFKeLyCw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77F2BC2BC81; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:53 +0800 Subject: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-13-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=1153; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=yJNhIn0leRAVKcGRNcbL93uhE9Lt8lpjWo3NwzELbK8=; b=ey4V7ZgnVkAT+IPbPvkrrbBhXKhF5T2jheFXSgN7mCj3Yk/HpJxoD+F1ELcHtWB3rR6HZPlHY Y1ToI4iAKc/CUf5K2JaddictYM2RP4QqaOFcclAJNfHYqLhmgjEPIAM X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Set the plane alpha according to DRM plane property. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 943db4f1bd6b..4b370bc0746d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, } =20 con =3D ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |=3D OVL_CON_AEN | OVL_CON_ALPHA; + if (state->base.fb) { + con |=3D OVL_CON_AEN; + con |=3D state->base.alpha & OVL_CON_ALPHA; + } =20 /* CONST_BLD must be enabled for XRGB formats although the alpha channel * can be ignored, or OVL will still read the value from memory. --=20 Git-146) From nobody Thu Sep 19 23:26:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABF7B155C8B for ; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; cv=none; b=u3TgrOrUG8TYSMzaJEDbJQDcoZJXcbQjcfx/85x/fx3ZywKFyKmxcuVa8jxKyUWLTTcwk/ctFpKUBZo4BBoDE/eI6NUTBo4boV21e7Kw6ukfhnu73SYtVrn3rk8VmA1bM6FT3JJpqY+6CJYIWaL+LQYOYRg2p8trlkbhqjEY9aQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718815125; c=relaxed/simple; bh=QoOCchLhAkgR5oT73U1iQHt/xJx1/rjkd6jCZnxGdpg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k5VZYGrCXI+Bx4n5ZiCeBFcSLj3aEkfwapry+aAUqywzgyA7gjXN45J6KUAxz9lYL3z0TH9mReJcMhNQbKzO2bgrC46M907d8cTj2lDuOPOLpEOH7zxxeRiOo8RKzKV6D0EzvJnJjQblb2TqFCU7xnDOD1MOPJcymNvSwDiIqQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g6BGH8MZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g6BGH8MZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8F81AC4AF48; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718815125; bh=QoOCchLhAkgR5oT73U1iQHt/xJx1/rjkd6jCZnxGdpg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=g6BGH8MZkAOoyx5QNoJpfkmO/rd5iBI4QSn3BLJzYdJTl/g2O4kYvv9qEI/urYFkY 09RN+6uJ7Ea+mS/4fHola4WzUiWR2RYvxYVH6EW8+DzqOUC9ejNE+fHi1PPMLOjK84 fDMjVKTTtrknSbWceMTCdnsHQUAirslGQm0pEFPfpkgqW3YfWM92rz5RM0E0RInmA7 guw+aXoEz2dkuS2A5GwjukvWl6shYyUiZPiOyyRVAYvoDJ9WRlL0fn98ZR9WBktcIW bQ50+K2vXfhpOCdDjJHwQctvqCDzBc2SHqFsXUrKYG1usdwi7TckViafzBBhP5HwUW TI5tnDmZ+KgaQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85DB5C27C53; Wed, 19 Jun 2024 16:38:45 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 00:38:54 +0800 Subject: [PATCH v3 14/14] drm/mediatek: Support DRM plane alpha in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-igt-v3-14-a9d62d2e2c7e@mediatek.com> References: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> In-Reply-To: <20240620-igt-v3-0-a9d62d2e2c7e@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , Mao Huang , "Nancy.Lin" Cc: YT Shen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718815123; l=1063; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=Vnu6L7E0FQDG2jpI6hDgdX16IWg1DCeKne1NvT//xQs=; b=oIEoZkfPXwHGxqdBosxBOqRMc/3HWUAjesYMnqVYPGpry/2X/nRyestB8qRDilMKWil2iczZr ohmhFHopQ09CB1Yk1BrckYm9Nv7HSeZ0Uw736E+Hzz/SxMhbQ+77G11 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Set the plane alpha according to DRM plane property. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index bf5826b7e776..36021cb8df62 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -170,8 +170,10 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, return; } =20 - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; + if (state->base.fb) { + alpha_con |=3D MIXER_ALPHA_AEN; + alpha_con |=3D state->base.alpha & MIXER_ALPHA; + } =20 if (state->base.fb && !state->base.fb->format->has_alpha) { /* --=20 Git-146)