From nobody Fri Sep 20 01:32:45 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 794F7339A8 for ; Wed, 19 Jun 2024 17:27:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718818032; cv=none; b=LYjAAgOjdrcW16grpM7aHvCyXU0DfN4PsUlxX5CqFJ03je7QXVtPUY/Hc7U26IwyNkTMmRxlKYZA2+xb0zXnLKOElvbRDV4Y7HxsTnYDA/2814T2EvDTFxPq6kibhNPjEub+twHvh1JedN1RoOh/ieomqniQO9dj1paa478t6HA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718818032; c=relaxed/simple; bh=PmY3gJDFSS+M4IZmgfiRwP+hDg2XPx2rJkkufnFkkdM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SNiv/uZ9lwYpPc72sdlNEl2eInIHylpF5268S18ymKHuLG4PpaZZ/Iqsf9W1GADoRy0+z52ewqBhecPYzt+N0Qm4KhwoBAo2SYSRPUSGwJC+Dby06MoE9UZr/gGH+glOPJsPHlsCg/A+fSGToiLRj2zglFeKj5aT71U70wf5g2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QT1+ZpmP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QT1+ZpmP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 506BFC4AF0A; Wed, 19 Jun 2024 17:27:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718818032; bh=PmY3gJDFSS+M4IZmgfiRwP+hDg2XPx2rJkkufnFkkdM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QT1+ZpmP7KFIZYRmbhKiuhviN0ayIBSyLBJSEfzZEcp1WO0jTQJOatYOj3xZSsS1u w/gWPVurNcaRP5HpDHI9ODu6DIi1CpaznSIZpabs1grc7DAL2MHEr0o0Fdjijhc4kz CWTd1lO/9wFBmr3KLtM1CfzrH1ibZvT5ZBRMvl5oaxSUiTUfW0EqcUPi2KDBcWB+tr E5YotfWYHBOuLBv/qXQ92+4P/zKZPftH+P717uHepQ7EZuLrorq1biTIuskiOER0gJ jjoRLw1c07R9XYmkxGiBtNeCC8ASSewhy0758IR1sD0HkQxJpM9hyCcHi5bgWv7i2y wV6nuOMnx60qA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 418ADC27C79; Wed, 19 Jun 2024 17:27:12 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Thu, 20 Jun 2024 01:27:08 +0800 Subject: [PATCH 3/5] drm/mediatek: Support "Pre-multiplied" blending in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240620-blend-v1-3-72670072ca20@mediatek.com> References: <20240620-blend-v1-0-72670072ca20@mediatek.com> In-Reply-To: <20240620-blend-v1-0-72670072ca20@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718818030; l=3803; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=DavUw+j//lvUyWdRkM3M0/+G2/7MZYehRHdjvtF7ATk=; b=LWKW/d54b/ZZpO3h6Oc9lmFwK+Sj/dMDs9p4n5yrceZyxoQXxu7Vmqo5SS9TRU4A8O/+iB/O8 hkVn5RoFM4qCwDoqN+s79jfBYu++QIQQR9Lz5012yQOSsvofVtspTlb X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support "Pre-multiplied" alpha blending mode on in OVL. Before this patch, only the "coverage" mode is supported. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +++++++++++++++++++++++++----= --- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index ad9228fc4dd9..8e9aae36a289 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -52,8 +52,12 @@ #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) =20 +#define OVL_CON_CLRFMT_MAN BIT(23) #define OVL_CON_BYTE_SWAP BIT(24) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) + +/* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */ +#define OVL_CON_RGB_SWAP BIT(25) + #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_ARGB8888 (2 << 12) #define OVL_CON_CLRFMT_RGBA8888 (3 << 12) @@ -61,6 +65,11 @@ #define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SW= AP) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_CLRFMT_PARGB8888 ((3 << 12) | OVL_CON_CLRFMT_MAN) +#define OVL_CON_CLRFMT_PABGR8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_RGB_S= WAP) +#define OVL_CON_CLRFMT_PBGRA8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_BYTE_= SWAP) +#define OVL_CON_CLRFMT_PRGBA8888 (OVL_CON_CLRFMT_PABGR8888 | OVL_CON_BYTE_= SWAP) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -382,7 +391,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int= idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt) +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, + unsigned int blend_mode) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -403,22 +413,30 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) case DRM_FORMAT_RGBA8888: case DRM_FORMAT_RGBX1010102: case DRM_FORMAT_RGBA1010102: - return OVL_CON_CLRFMT_RGBA8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PRGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: - return OVL_CON_CLRFMT_BGRA8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_BGRA8888 : + OVL_CON_CLRFMT_PBGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - return OVL_CON_CLRFMT_ARGB8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - return OVL_CON_CLRFMT_ABGR8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ABGR8888 : + OVL_CON_CLRFMT_PABGR8888; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: @@ -458,7 +476,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt); + con =3D ovl_fmt_convert(ovl, fmt, blend_mode); if (state->base.fb) { con |=3D OVL_CON_AEN; con |=3D state->base.alpha & OVL_CON_ALPHA; --=20 Git-146)