From nobody Wed Feb 11 22:54:12 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8EDB7C6C1; Wed, 19 Jun 2024 08:37:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718786248; cv=none; b=Y4pMmfkrsRD3EC6uTrF53Vehj48LzovQqrfg4WHzgJrEHhr3Dj7J8dQt3BWIGt1fbzN9mDx0i7xH8gLkqlbMeE4b1ZeD7OXIoXgvWQyvAa/L5kALjn6giBXvYebQDwEbYxRarQFz1Ulo5y/w3POTWYVlGdkXYgKG/yBDFEjRTCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718786248; c=relaxed/simple; bh=3n4ybvOboaWmCPxPYF9JaDhbuBNKJSiOEOAlF18cCao=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XNoAEfaKUERq9X8ZlYLfbZnd9r3+dzx0fZZKPUpExiTmBMCnaQ+UCsQXQKoqeYF8dAVRtxCsLrTAFlmqbfYJuvv9kMBDkZ4XyMY06Z5iGzHDtzZ/OAJ7EWkKXL1ebgVbrbl8rJ/LUp35mNAybJRAnsWJ7xyHJWk+L4TmEsPcK08= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=qfALhzJL; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="qfALhzJL" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45J7SgTo013430; Wed, 19 Jun 2024 10:37:09 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= wRMG4qwA9Dbv46xH+h26yQBQYduRI5IcnQPPuE4Kx50=; b=qfALhzJLj+lkQZum 5lNSNIROaUM38QCtFBIeSo+ceMxPCMGDXc/D1aqxMFzZs8069SrzuadFxVsM9UI9 1p24QSoSfn9FUlS4nBStSz7LdvXCRip5NXjQz6adwKNbxr7atzNaTVZg2s6AsQha IaTo3KqpAOIonqfayXSmIyzGu6aSTjx69st9n17XeDaNW6Vvf9oXwxheSmwX0cus +mSvLx2tGMWJcUiSkkTmaytGGLg/Bd3gdbhxD7DxF9TQTrR9u0gpPW08Y0M724R2 f+iquYLWsnJaaR+QPzbLxZ5QPG38K1a8Av/WoiuJ5kXMR37koHh7lxnVIdnm79Bi OA1QhQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3yuj9ua3b3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jun 2024 10:37:09 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CE1E840048; Wed, 19 Jun 2024 10:37:05 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E873320F554; Wed, 19 Jun 2024 10:36:10 +0200 (CEST) Received: from localhost (10.48.86.232) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 19 Jun 2024 10:36:10 +0200 From: Pascal Paillet To: Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown , , , , CC: , Etienne Carriere Subject: [PATCH 1/4] dt-bindings: add STM32MP25 regulator bindings Date: Wed, 19 Jun 2024 10:35:59 +0200 Message-ID: <20240619083602.33007-2-p.paillet@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619083602.33007-1-p.paillet@foss.st.com> References: <20240619083602.33007-1-p.paillet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-19_02,2024-06-17_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" These bindings will be used for the SCMI voltage domain. Signed-off-by: Pascal Paillet Acked-by: Krzysztof Kozlowski --- .../regulator/st,stm32mp25-regulator.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/regulator/st,stm32mp25-regulator.h diff --git a/include/dt-bindings/regulator/st,stm32mp25-regulator.h b/inclu= de/dt-bindings/regulator/st,stm32mp25-regulator.h new file mode 100644 index 000000000000..3c3d30911dd0 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp25-regulator.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H + +/* SCMI voltage domains identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_VDDIO1 0 +#define VOLTD_SCMI_VDDIO2 1 +#define VOLTD_SCMI_VDDIO3 2 +#define VOLTD_SCMI_VDDIO4 3 +#define VOLTD_SCMI_VDDIO 4 +#define VOLTD_SCMI_UCPD 5 +#define VOLTD_SCMI_USB33 6 +#define VOLTD_SCMI_ADC 7 +#define VOLTD_SCMI_GPU 8 +#define VOLTD_SCMI_VREFBUF 9 + +/* STPMIC2 regulators */ +#define VOLTD_SCMI_STPMIC2_BUCK1 10 +#define VOLTD_SCMI_STPMIC2_BUCK2 11 +#define VOLTD_SCMI_STPMIC2_BUCK3 12 +#define VOLTD_SCMI_STPMIC2_BUCK4 13 +#define VOLTD_SCMI_STPMIC2_BUCK5 14 +#define VOLTD_SCMI_STPMIC2_BUCK6 15 +#define VOLTD_SCMI_STPMIC2_BUCK7 16 +#define VOLTD_SCMI_STPMIC2_LDO1 17 +#define VOLTD_SCMI_STPMIC2_LDO2 18 +#define VOLTD_SCMI_STPMIC2_LDO3 19 +#define VOLTD_SCMI_STPMIC2_LDO4 20 +#define VOLTD_SCMI_STPMIC2_LDO5 21 +#define VOLTD_SCMI_STPMIC2_LDO6 22 +#define VOLTD_SCMI_STPMIC2_LDO7 23 +#define VOLTD_SCMI_STPMIC2_LDO8 24 +#define VOLTD_SCMI_STPMIC2_REFDDR 25 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 26 +#define VOLTD_SCMI_REGU1 27 +#define VOLTD_SCMI_REGU2 28 +#define VOLTD_SCMI_REGU3 29 +#define VOLTD_SCMI_REGU4 30 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H */ --=20 2.34.1 From nobody Wed Feb 11 22:54:12 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 385957CF3A; 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charset="utf-8" Add SCMI regulators description on STM32MP25. Signed-off-by: Pascal Paillet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 96d6de29c14c..18094dadc9c4 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -75,6 +76,40 @@ scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; }; + + scmi_voltd: protocol@17 { + reg =3D <0x17>; + + scmi_regu: regulators { + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_vddio1: regulator@0 { + reg =3D ; + regulator-name =3D "vddio1"; + }; + scmi_vddio2: regulator@1 { + reg =3D ; + regulator-name =3D "vddio2"; + }; + scmi_vddio3: regulator@2 { + reg =3D ; + regulator-name =3D "vddio3"; + }; + scmi_vddio4: regulator@3 { + reg =3D ; + regulator-name =3D "vddio4"; + }; + scmi_vdd33ucpd: regulator@5 { + reg =3D ; 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charset="utf-8" Describe power supplies for stm32mp257f-ev1 board. Signed-off-by: Pascal Paillet --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 43 +++++++++++++++++----- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 18c6266532b2..979847e0ea05 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -7,6 +7,7 @@ /dts-v1/; =20 #include +#include #include "stm32mp257.dtsi" #include "stm32mp25xf.dtsi" #include "stm32mp25-pinctrl.dtsi" @@ -41,14 +42,6 @@ fw@80000000 { no-map; }; }; - - vdd_sdcard: vdd-sdcard { - compatible =3D "regulator-fixed"; - regulator-name =3D "vdd_sdcard"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; }; =20 &arm_wdt { @@ -56,6 +49,37 @@ &arm_wdt { status =3D "okay"; }; =20 +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + scmi_vddcore: regulator@11 { + reg =3D ; + regulator-name =3D "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg =3D ; + regulator-name =3D "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg =3D ; + regulator-name =3D "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg =3D ; + regulator-name =3D "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg =3D ; + regulator-name =3D "vdd3v3_usb"; + }; + scmi_vdd_sdcard: regulator@23 { + reg =3D ; + regulator-name =3D "vdd_sdcard"; + }; +}; + &i2c2 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c2_pins_a>; @@ -85,7 +109,8 @@ &sdmmc1 { disable-wp; st,neg-edge; bus-width =3D <4>; - vmmc-supply =3D <&vdd_sdcard>; + vmmc-supply =3D <&scmi_vdd_sdcard>; + vqmmc-supply =3D <&scmi_vddio1>; status =3D "okay"; }; =20 --=20 2.34.1 From nobody Wed Feb 11 22:54:12 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BB687CF25; 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charset="utf-8" Add SCMI ARM REGULATOR configuration for stm32. Signed-off-by: Pascal Paillet --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a52618073de2..dab964bc70ca 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -312,6 +312,7 @@ config ARCH_STM32 select STM32_EXTI select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL + select REGULATOR_ARM_SCMI select COMMON_CLK_SCMI select STM32_FIREWALL help --=20 2.34.1