From nobody Wed Feb 11 22:54:24 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D52FD13D525; Wed, 19 Jun 2024 07:23:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718781815; cv=none; b=YWCf3aR10i1K3yvHphoETNylaR82PLoLJbHFtGbnvi9qZ6C83fL5hA/vAZlW9bLnokEibXeoirDa1Wb0PdfDQAOpvY+xSvHYlgibtkFCsOJPnHgOOJr4O34tVGb801qrEcwMmgDzDWPA+XPwXIoG1Tody3iQGJqQ1jPhh0mR76Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718781815; c=relaxed/simple; bh=fqaivpLVUYPqyhOF2jg3SFodzPDaRZd2i2dgt24Ws6w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Yw50PNm/5bHAMdhoV42rnTwTuvsbadKcimhGaujxafOgiar9JkVbDlNZp7kXhuM/tvUaynAF3erZmX0TKagprMSL7gmestCntK8bhgJZX/lfNDKCHY7pG1Y15kLTN+eX1bp84eQuePqCRBrsh3uG49FpCbXl7U5Pnzn4CTBPaOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ixHy4W/e; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ixHy4W/e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718781813; x=1750317813; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fqaivpLVUYPqyhOF2jg3SFodzPDaRZd2i2dgt24Ws6w=; b=ixHy4W/eIqc4LvV5alTfRHUt4uPNhto/i7eUTnq1bnpTOnmiNsaogaWu HVZBKNAajPfk13ev8iQOw4VmvT8qRkHTxyFf27EtcnK+YLMpGJZAwLZHP 9pF+Vn5+QjBArR+93RkwEzTyDTj4/HQOkA48lfAI0sTvYU68gMdqZM/4y KaPDvXFE7CYtvlkSPV951mjoFvxVUizcMT7aV3enT/AWQGfItxNzl6lZc 4OkAn6hVp6kAaoSoKenGdcSxT9fVqWdYVaM/xTHJrNj07h0qa7mF9VLQZ m+Tn++R5Zyy2juVz8nYguUsOk3k1+/RKdAvgrsQhuF1RrARVEwthPo4ki g==; X-CSE-ConnectionGUID: Nru8q+MHQyC2PaLNcFE7ig== X-CSE-MsgGUID: GcSQHuCsR36LLSwyAY1N8g== X-IronPort-AV: E=Sophos;i="6.08,249,1712646000"; d="scan'208";a="30691795" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 Jun 2024 00:23:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 19 Jun 2024 00:23:02 -0700 Received: from ROB-ULT-M76677.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 19 Jun 2024 00:22:58 -0700 From: Andrei Simion To: , , , , , , , , CC: , , , , Claudiu Beznea , Andrei Simion Subject: [PATCH 1/3] eeprom: at24: avoid adjusting offset for 24AA025E{48, 64} Date: Wed, 19 Jun 2024 10:22:29 +0300 Message-ID: <20240619072231.6876-2-andrei.simion@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619072231.6876-1-andrei.simion@microchip.com> References: <20240619072231.6876-1-andrei.simion@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The EEPROMs could be used only for MAC storage. In this case the EEPROM areas where MACs resides could be modeled as NVMEM cells (directly via DT bindings) such that the already available networking infrastructure to read properly the MAC addresses (via of_get_mac_address()). The previously available compatibles needs the offset adjustment probably for compatibility w/ old DT bindings. Added "atmel,24mac02e4", "atmel,24mac02e6" compatible for the usage w/ 24AA025E{48, 64} type of EEPROMs. Signed-off-by: Claudiu Beznea Co-developed-by: Andrei Simion Signed-off-by: Andrei Simion --- drivers/misc/eeprom/at24.c | 73 ++++++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 31 deletions(-) diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c index 4bd4f32bcdab..8699a6c585c4 100644 --- a/drivers/misc/eeprom/at24.c +++ b/drivers/misc/eeprom/at24.c @@ -121,17 +121,19 @@ struct at24_chip_data { u32 byte_len; u8 flags; u8 bank_addr_shift; + u8 adjoff; void (*read_post)(unsigned int off, char *buf, size_t count); }; =20 -#define AT24_CHIP_DATA(_name, _len, _flags) \ +#define AT24_CHIP_DATA(_name, _len, _flags, _adjoff) \ static const struct at24_chip_data _name =3D { \ - .byte_len =3D _len, .flags =3D _flags, \ + .byte_len =3D _len, .flags =3D _flags, .adjoff =3D _adjoff, \ } =20 -#define AT24_CHIP_DATA_CB(_name, _len, _flags, _read_post) \ +#define AT24_CHIP_DATA_CB(_name, _len, _flags, _adjoff, _read_post) \ static const struct at24_chip_data _name =3D { \ .byte_len =3D _len, .flags =3D _flags, \ + .adjoff =3D _adjoff, \ .read_post =3D _read_post, \ } =20 @@ -162,53 +164,57 @@ static void at24_read_post_vaio(unsigned int off, cha= r *buf, size_t count) } =20 /* needs 8 addresses as A0-A2 are ignored */ -AT24_CHIP_DATA(at24_data_24c00, 128 / 8, AT24_FLAG_TAKE8ADDR); +AT24_CHIP_DATA(at24_data_24c00, 128 / 8, AT24_FLAG_TAKE8ADDR, 0); /* old variants can't be handled with this generic entry! */ -AT24_CHIP_DATA(at24_data_24c01, 1024 / 8, 0); +AT24_CHIP_DATA(at24_data_24c01, 1024 / 8, 0, 0); AT24_CHIP_DATA(at24_data_24cs01, 16, - AT24_FLAG_SERIAL | AT24_FLAG_READONLY); -AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, 0); + AT24_FLAG_SERIAL | AT24_FLAG_READONLY, 0); +AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, 0, 0); AT24_CHIP_DATA(at24_data_24cs02, 16, - AT24_FLAG_SERIAL | AT24_FLAG_READONLY); + AT24_FLAG_SERIAL | AT24_FLAG_READONLY, 0); AT24_CHIP_DATA(at24_data_24mac402, 48 / 8, - AT24_FLAG_MAC | AT24_FLAG_READONLY); + AT24_FLAG_MAC | AT24_FLAG_READONLY, 1); AT24_CHIP_DATA(at24_data_24mac602, 64 / 8, - AT24_FLAG_MAC | AT24_FLAG_READONLY); + AT24_FLAG_MAC | AT24_FLAG_READONLY, 1); +AT24_CHIP_DATA(at24_data_24mac02e4, 48 / 8, + AT24_FLAG_MAC | AT24_FLAG_READONLY, 0); +AT24_CHIP_DATA(at24_data_24mac02e6, 64 / 8, + AT24_FLAG_MAC | AT24_FLAG_READONLY, 0); /* spd is a 24c02 in memory DIMMs */ AT24_CHIP_DATA(at24_data_spd, 2048 / 8, - AT24_FLAG_READONLY | AT24_FLAG_IRUGO); + AT24_FLAG_READONLY | AT24_FLAG_IRUGO, 0); /* 24c02_vaio is a 24c02 on some Sony laptops */ AT24_CHIP_DATA_CB(at24_data_24c02_vaio, 2048 / 8, - AT24_FLAG_READONLY | AT24_FLAG_IRUGO, + AT24_FLAG_READONLY | AT24_FLAG_IRUGO, 0, at24_read_post_vaio); -AT24_CHIP_DATA(at24_data_24c04, 4096 / 8, 0); +AT24_CHIP_DATA(at24_data_24c04, 4096 / 8, 0, 0); AT24_CHIP_DATA(at24_data_24cs04, 16, - AT24_FLAG_SERIAL | AT24_FLAG_READONLY); + AT24_FLAG_SERIAL | AT24_FLAG_READONLY, 0); /* 24rf08 quirk is handled at i2c-core */ -AT24_CHIP_DATA(at24_data_24c08, 8192 / 8, 0); +AT24_CHIP_DATA(at24_data_24c08, 8192 / 8, 0, 0); AT24_CHIP_DATA(at24_data_24cs08, 16, - AT24_FLAG_SERIAL | AT24_FLAG_READONLY); -AT24_CHIP_DATA(at24_data_24c16, 16384 / 8, 0); + AT24_FLAG_SERIAL | AT24_FLAG_READONLY, 0); +AT24_CHIP_DATA(at24_data_24c16, 16384 / 8, 0, 0); AT24_CHIP_DATA(at24_data_24cs16, 16, - AT24_FLAG_SERIAL | AT24_FLAG_READONLY); -AT24_CHIP_DATA(at24_data_24c32, 32768 / 8, AT24_FLAG_ADDR16); + AT24_FLAG_SERIAL | AT24_FLAG_READONLY, 0); +AT24_CHIP_DATA(at24_data_24c32, 32768 / 8, AT24_FLAG_ADDR16, 0); /* M24C32-D Additional Write lockable page (M24C32-D order codes) */ -AT24_CHIP_DATA(at24_data_24c32d_wlp, 32, AT24_FLAG_ADDR16); +AT24_CHIP_DATA(at24_data_24c32d_wlp, 32, AT24_FLAG_ADDR16, 0); AT24_CHIP_DATA(at24_data_24cs32, 16, - AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY); -AT24_CHIP_DATA(at24_data_24c64, 65536 / 8, AT24_FLAG_ADDR16); + AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY, 0); +AT24_CHIP_DATA(at24_data_24c64, 65536 / 8, AT24_FLAG_ADDR16, 0); /* M24C64-D Additional Write lockable page (M24C64-D order codes) */ -AT24_CHIP_DATA(at24_data_24c64d_wlp, 32, AT24_FLAG_ADDR16); +AT24_CHIP_DATA(at24_data_24c64d_wlp, 32, AT24_FLAG_ADDR16, 0); AT24_CHIP_DATA(at24_data_24cs64, 16, - AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY); -AT24_CHIP_DATA(at24_data_24c128, 131072 / 8, AT24_FLAG_ADDR16); -AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16); -AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16); -AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16); + AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY, 0); +AT24_CHIP_DATA(at24_data_24c128, 131072 / 8, AT24_FLAG_ADDR16, 0); +AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16, 0); +AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16, 0); +AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16, 0); +AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16, 0); AT24_CHIP_DATA_BS(at24_data_24c1025, 1048576 / 8, AT24_FLAG_ADDR16, 2); -AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16); /* identical to 24c08 ? */ -AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0); +AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0, 0); =20 static const struct i2c_device_id at24_ids[] =3D { { "24c00", (kernel_ulong_t)&at24_data_24c00 }, @@ -217,7 +223,9 @@ static const struct i2c_device_id at24_ids[] =3D { { "24c02", (kernel_ulong_t)&at24_data_24c02 }, { "24cs02", (kernel_ulong_t)&at24_data_24cs02 }, { "24mac402", (kernel_ulong_t)&at24_data_24mac402 }, + { "24mac02e4", (kernel_ulong_t)&at24_data_24mac02e4 }, { "24mac602", (kernel_ulong_t)&at24_data_24mac602 }, + { "24mac02e6", (kernel_ulong_t)&at24_data_24mac02e6 }, { "spd", (kernel_ulong_t)&at24_data_spd }, { "24c02-vaio", (kernel_ulong_t)&at24_data_24c02_vaio }, { "24c04", (kernel_ulong_t)&at24_data_24c04 }, @@ -250,7 +258,9 @@ static const struct of_device_id __maybe_unused at24_of= _match[] =3D { { .compatible =3D "atmel,24c02", .data =3D &at24_data_24c02 }, { .compatible =3D "atmel,24cs02", .data =3D &at24_data_24cs02 }, { .compatible =3D "atmel,24mac402", .data =3D &at24_data_24mac402 }, + { .compatible =3D "atmel,24mac02e4", .data =3D &at24_data_24mac02e4 }, { .compatible =3D "atmel,24mac602", .data =3D &at24_data_24mac602 }, + { .compatible =3D "atmel,24mac02e6", .data =3D &at24_data_24mac02e6 }, { .compatible =3D "atmel,spd", .data =3D &at24_data_spd }, { .compatible =3D "atmel,24c04", .data =3D &at24_data_24c04 }, { .compatible =3D "atmel,24cs04", .data =3D &at24_data_24cs04 }, @@ -690,7 +700,8 @@ static int at24_probe(struct i2c_client *client) at24->read_post =3D cdata->read_post; at24->bank_addr_shift =3D cdata->bank_addr_shift; at24->num_addresses =3D num_addresses; - at24->offset_adj =3D at24_get_offset_adj(flags, byte_len); + at24->offset_adj =3D cdata->adjoff ? + at24_get_offset_adj(flags, byte_len) : 0; at24->client_regmaps[0] =3D regmap; =20 at24->vcc_reg =3D devm_regulator_get(dev, "vcc"); --=20 2.34.1 From nobody Wed Feb 11 22:54:24 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE6918249B; Wed, 19 Jun 2024 07:23:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718781813; cv=none; b=NF4brKMm1RFQCCyhxDpV9oNJl9Fulpjzs3drQoA8T79lghCIiuTMjIDtAd/jRz3Q12C+vxfQFERIZAWvSqIa5yUWxzBu3A5TpSDbOR8D89d7jeqtr/n4UiQewIZSLAXlIdWocBjMKAgWhmYupu7fR9Mr/CmPumV/4XtrGXf8Idw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718781813; c=relaxed/simple; bh=5MpWaJAI0rtIb4sA3J2QYApRt6QQBb2cDKxrZCU19SQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VTDk4o9yzz8W7EQAPlDuWcb4i3yOAYSgzYA3l9CmWeIJ7SkHQMf2oQCkkTaOXFPMk+3tIHr2upK0l7RfQpU86TbiUPSRmbyVc0so/L6BheVE1F7fa3GJEhNjMRi25PIeGR+kuexX4gcl01v1j9FHAO8yIv20gcc3gQilwrq7Odg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=aWPwRhzo; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aWPwRhzo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718781810; x=1750317810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5MpWaJAI0rtIb4sA3J2QYApRt6QQBb2cDKxrZCU19SQ=; b=aWPwRhzoGbVg0Rak57u0S8omIusTQHDtWjnrFExTotLyinwR8dqCrSxK PXFCfZb5Q8WGojrR5kTDb12JSdh+T68n0q0yPVAprmAUcX93m8IeIFofb OfTAiJG5eiECDLKJ4CbBtu6kZ16H7X1KqFg3B1amrhzEZOtftcIeprUen JrGsppHTmzexRRJ0QLGEQiwwL3GaQD6a1Szhu2eBVRERr94ySZtf+Tb66 ZNFkWV2zFdTV4ISivK76YGBmcP02rqq74YrQDyra1JmerBwhn6qOk+gKN VFMKzMBm7BTPyPb57VfZpYg0yuysUkAZPnIXKXlcZKadbGqzuu6r0O7VX w==; X-CSE-ConnectionGUID: HPQiKEpwSfeQRjMG7YWokQ== X-CSE-MsgGUID: csf1+pZ1Q8i6yOGT+zZgew== X-IronPort-AV: E=Sophos;i="6.08,249,1712646000"; d="scan'208";a="30691772" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 Jun 2024 00:23:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 19 Jun 2024 00:23:05 -0700 Received: from ROB-ULT-M76677.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 19 Jun 2024 00:23:02 -0700 From: Andrei Simion To: , , , , , , , , CC: , , , , Claudiu Beznea , Andrei Simion Subject: [PATCH 2/3] ARM: dts: at91: at91-sama7g5ek: add EEPROMs Date: Wed, 19 Jun 2024 10:22:30 +0300 Message-ID: <20240619072231.6876-3-andrei.simion@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619072231.6876-1-andrei.simion@microchip.com> References: <20240619072231.6876-1-andrei.simion@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add EEPROMs and nvmem-layout to describe eui48 mac address region. Signed-off-by: Claudiu Beznea Co-developed-by: Andrei Simion Signed-off-by: Andrei Simion --- .../arm/boot/dts/microchip/at91-sama7g5ek.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot= /dts/microchip/at91-sama7g5ek.dts index 20b2497657ae..66e8c8258684 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -403,6 +403,46 @@ i2c8: i2c@600 { i2c-digital-filter; i2c-digital-filter-width-ns =3D <35>; status =3D "okay"; + + eeprom0: eeprom@52 { + compatible =3D "atmel,24mac02e4"; + reg =3D <0x52>; + #address-cells =3D <1>; + #size-cells =3D <1>; + size =3D <256>; + pagesize =3D <16>; + vcc-supply =3D <&vdd_3v3>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + eeprom0_eui48: eui48@fa { + reg =3D <0xfa 0x6>; + }; + }; + }; + + eeprom1: eeprom@53 { + compatible =3D "atmel,24mac02e4"; + reg =3D <0x53>; + #address-cells =3D <1>; + #size-cells =3D <1>; + size =3D <256>; + pagesize =3D <16>; + vcc-supply =3D <&vdd_3v3>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + eeprom1_eui48: eui48@fa { + reg =3D <0xfa 0x6>; + }; + }; + }; }; }; =20 @@ -440,6 +480,8 @@ &pinctrl_gmac0_mdio_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; phy-mode =3D "rgmii-id"; + nvmem-cells =3D <&eeprom0_eui48>; + nvmem-cell-names =3D "mac-address"; status =3D "okay"; =20 ethernet-phy@7 { @@ -457,6 +499,8 @@ &gmac1 { &pinctrl_gmac1_mdio_default &pinctrl_gmac1_phy_irq>; phy-mode =3D "rmii"; + nvmem-cells =3D <&eeprom1_eui48>; + nvmem-cell-names =3D "mac-address"; status =3D "okay"; /* Conflict with pdmc0. */ =20 ethernet-phy@0 { --=20 2.34.1 From nobody Wed Feb 11 22:54:24 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E6FA136664; Wed, 19 Jun 2024 07:23:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718781814; cv=none; b=RHMBAe3hi/kz9S+s6baW4RHMnfRcTgu9OMeHRvFK6x3LyxxTv1nj80upZfPAEXsyLMWNgDz0Yvs7GjmLFCxOaE4d+l4EJlQzhrpeFZGfvJTLyV7Ozfmx5upJyDs05Cyw2omv8oRdf5ZO29rQfumxvDomo465fj1TeTPvnIJwCcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718781814; c=relaxed/simple; bh=p1887b9iD5BlnBSAk0HwLOV/I/hhD4A89kd/poNXHMY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PnbaSOOp3YT+sYhXvpv6s/3uqHyopvpqbJZK9OUwHb15mAKUmP3wrt0le0eA/u2esoHduey2GoFJg8i4Uc9WeUsSgONxBIyAefR79CFrKIjNoDGP1ShggosFdCAKWAPid8vUtFonprGqdcB/tNWCyx4RZ2MnRkJ1UyFq0eModsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=N0hK8mvH; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="N0hK8mvH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718781812; x=1750317812; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p1887b9iD5BlnBSAk0HwLOV/I/hhD4A89kd/poNXHMY=; b=N0hK8mvHL5CjWY6XrYRkZo7uq/APkdirmevYUzVbzEPRXMc7sF6QrOLP QaAQoBtEn3VvhGKxqdutNIV2oJQEXfwSesoncU84/veseqoeP/1KFiTR4 +H6c/a7NV2R7cfDZrWvb1epuvF/6VaJ9CmBzT/OcQ6Lp36xUWwXpN+kDj VJNtrFyF8O3VKxEh3g68f3eDQ3YG5dzXR4hdHuldnsMRm1mb4aXyR0+GG TSq8v0fOO5Q0J+tp8AZz3H7vxyjEbzRMZmzbBTk8Mag5VckqxqknNSeMH gGDBW9IL+eIQnlstiXf8i/2peZnNFsg54YFf7aQOpU9UzKJJ57HVVnuDG g==; X-CSE-ConnectionGUID: HPQiKEpwSfeQRjMG7YWokQ== X-CSE-MsgGUID: i/IVfxG/SvC9fIX3Tzf8CA== X-IronPort-AV: E=Sophos;i="6.08,249,1712646000"; d="scan'208";a="30691781" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 Jun 2024 00:23:26 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 19 Jun 2024 00:23:08 -0700 Received: from ROB-ULT-M76677.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 19 Jun 2024 00:23:05 -0700 From: Andrei Simion To: , , , , , , , , CC: , , , , Andrei Simion Subject: [PATCH 3/3] dt-bindings: eeprom: at24: Add at24,mac02e4 and at24,mac02e6 Date: Wed, 19 Jun 2024 10:22:31 +0300 Message-ID: <20240619072231.6876-4-andrei.simion@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619072231.6876-1-andrei.simion@microchip.com> References: <20240619072231.6876-1-andrei.simion@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update regex check and add pattern to match both EEPROMs. Signed-off-by: Andrei Simion --- Documentation/devicetree/bindings/eeprom/at24.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documenta= tion/devicetree/bindings/eeprom/at24.yaml index 3c36cd0510de..46daa662f6e7 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -18,7 +18,7 @@ select: properties: compatible: contains: - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$" + pattern: "^atmel,(24(c|cs|mac)[0-9]+[a-z0-9]*|spd)$" required: - compatible =20 @@ -37,8 +37,8 @@ properties: - allOf: - minItems: 1 items: - - pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|r= ohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$" - - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$" + - pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|r= ohm|st),(24(c|cs|lc|mac)[0-9]+[a-z0-9]*|spd)$" + - pattern: "^atmel,(24(c|cs|mac)[0-9]+[a-z0-9]*|spd)$" - oneOf: - items: pattern: c00$ @@ -54,6 +54,10 @@ properties: pattern: mac402$ - items: pattern: mac602$ + - items: + pattern: mac02e4$ + - items: + pattern: mac02e6$ - items: pattern: c04$ - items: --=20 2.34.1