From nobody Fri Sep 20 01:21:26 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B760E22619 for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=DU2XzwxdY3fhxmcXbkKae3BE0GyRINqciIk3INYWaeSepTks21nTGsUFHUPinxZh11gidM5p5IPf1jsvxVXpKaMl3UFH/wp74D2VCSvYsit7KqnE095+/5qfDpOgjyXgzU8DgHzJzsriHCyYECAvzGwxm2DdmoFpsmQMNtHBLs4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=nk/C+wqrXVMA9amh6fPshkrHE4xq3UlYmGyCf1hutnA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YAppX+KsB0CcKJhs6lgFnuTDAjEG6vmX8KPfomWgsDirgXPGGIZOokkKmM1wPJ9IEv7HZU+P0fwk+XH67xcGS2h89Y7mYUHz77p6TkjGHzdSqyF3A3uuMqoVk15wXlh3ahblEGpTwV/cMbN1fbAvv8tIh8Q0QumOIDaXAvpa2n4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BP8tPFL3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BP8tPFL3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7F0ECC4AF0D; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=nk/C+wqrXVMA9amh6fPshkrHE4xq3UlYmGyCf1hutnA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BP8tPFL3sF5bndbwmFOYxqr1xPQjGksocrhH4DbNOGYKzeBJFyw9tN1fcv6IX0GqO E3IkEmVK3nfOMJTHhPSAJOhI4zS5IDH2Wvm0nWxo/kBqkeQW9MvRvTzESG14ukJa14 hcwxIzhH2Q9KDVx7MPhc20JfU9DVVR6DiOcjZytYTd24taeb9JvNSFf/kN76L3yPCN 6BbyJ9JMK1hBSGnBiGchuR+9+f1gxplEgKTorZNEZVkWhItEI0K+IYXNDFPtSYnwX/ p1sBAZcWEH+FSBlwODN4laQf3nGQvogWl2DL69VuhuA896lLxIQCBpRUR2kxTXlngb 1Q36jiWI2PLkw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EA1AC27C53; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:46 +0800 Subject: [PATCH v2 05/14] drm/mediatek: Turn off the layers with zero width or height Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-5-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=2110; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=1wAQfpFBsYHGAPuLXbpDgCF0uuBRyet+FxYXId9fMr0=; b=4/WwoVatxWG2vheNbELUaPi42wc85qaLAOkL3Dn5ulQNtClLAgS8OyN5j11wyNvQpAfMJP6Pw qt4nIxA2BGoA5jIJSpwOF4/OmpSyOnhF9fTx4KtCBlS6yBRnl3XFY9k X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195") Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 02dd7dcdfedb..2b62d6475918 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 5c52e514ae30..bf5826b7e776 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -160,7 +160,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (idx >=3D 4) return; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZ= E(idx)); return; } --=20 Git-146)