From nobody Fri Sep 20 01:39:06 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 919B91F956 for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=WzYjbxzwBJchIBeiVjbUnJtkZSQzpQ8qPz1OeuXF1HOAaJpcUOKN3bt8PVxVPk7piVJO+GPbQZg2ztcBWw10b2vzeut/07owtwznKQo1Fl5s/Vt3xpLGm4gBlWKCaHDc32iWTvoCHX0tPSFlz77yhK3cIcJNkzXZojh5zpViFrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IpYBVRpoYH36rxzedojh//lQE3Hrwk8f+YiXFMr9YfiKtsmcdWhOWwrUU8D140ojKte0yYKmitONLkf8dadV/baH3SanqtSZ3aww0pqvAZ1F2rFDZxjEIztaAxFvzF3efqrOuKIi/ly9jKMsVlna8HjTR9s5SUk/IusUATYUoF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AwtOrjFp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AwtOrjFp" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6B26CC4AF0C; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AwtOrjFpZGTO8bfHqaprHnw7Wv1EhZUdblvMILrHdpEYGJsHjWokHIXklVLecdbmV u0zSHy/mnth9/Y4D41yk0CKFSYK00IVp79AuoTC9J8LDcC8ziZNbTOfh2p48hRxll3 MVFhFSqLnDhrdoR13eSxdcY6RBf0wTbM0GQjImMR3MGNrmLXjwzFhnn8w0t8+JcXL4 LdgQ8/sK6NdVmjsEkvT6r2BjaX0XkekDEGOagNIWsYk80zWFuU+VsPgQ5Q5eZ/g3+l abmfBzAn0Qde9eZ4YNfkVr2raVmVh4RUhpi7FBXCcIHVlJIodUQzttzjMxBuhdK3Wi LcF/fm49U/e3Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D999C2BC81; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:45 +0800 Subject: [PATCH v2 04/14] drm/mediatek: Fix XRGB setting error in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-4-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=1806; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=iVCN8PnNVHs904I6AJ55kOr+V0K7XkkYFUBoVjBPemw=; b=zbO/9yDD3WrlwV9aQXD6T+LzL1cDtdTW68MZGIuRnNbMqkjeBif3cfxVoBAvkCBbMTkAfPGVb Mu0y7+d2FJ9CemdbDBflMXCNL+97grlHDtu7EiQ0+/4OM90yy+o56jq X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Although the alpha channel in XRGB formats can be ignored, ALPHA_CON must be configured accordingly when using XRGB formats or it will still affects CRC generation. Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index d7d16482c947..5c52e514ae30 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -153,6 +153,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, unsigned int offset =3D (pending->x & 1) << 31 | pending->y << 16 | pendi= ng->x; unsigned int align_width =3D ALIGN_DOWN(pending->width, 2); unsigned int alpha_con =3D 0; + bool replace_src_a =3D false; =20 dev_dbg(dev, "%s+ idx:%d", __func__, idx); =20 @@ -167,7 +168,15 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (state->base.fb && state->base.fb->format->has_alpha) alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, + if (state->base.fb && !state->base.fb->format->has_alpha) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a =3D true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); --=20 Git-146)