From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F11F1F934 for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=iy/LfpAvk7GYLYSVjwE+aii5jl6N5FDDaNz6W/PCojergcU6vqim1bZGEs67eP0LMORs5WKLEfwj09rdhI7beB2672SXg1/Ob1TumtgACZ/REBotLrpEySXs1GDJGXQMDAyB2m6QhVx4vOknQWiuiddttJrGJlmIjTCtuImC1lQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=ooFwSoVJ9N3sXdcV4iug2DcGs+ehRHDEPEzbrAfyAEI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=isnO2o1OSs58jgUntJdtmylr9F3pkoYbrWjUn79HgHGbAECH7yb1Q/V0WO7R/Vo+eDSz6GSyiFfAIN8t8WCr20pVACWqV2qUyAvVwV0SGD70N8gHiVOAjSoeI5K8qXaLYbKhpn9bd0FfQVhbSNZqiles2zQEbakuXXCSNXmIEu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oejyAPu2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oejyAPu2" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3F552C2BBFC; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=ooFwSoVJ9N3sXdcV4iug2DcGs+ehRHDEPEzbrAfyAEI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=oejyAPu2JXl8kl9zvH+6wmfbH/zgNTpnVQS3xP9/HtTUHm1hVGnEPinDmIXJmqZED OBBiTGv69W2b2W9IdzeWOIuXSLXbCYtJ5A/PNM7T3fwyASyE/Lbe6ndY5BAWbHSYhc HU3FMYPRLlCRoYd1fp1cBAwKPLcFTiM2P7J39TsVH3sdtVwJrIOk2oVrrj06ODPlvo wzQMIzYRHt4Wasst8wG+xBz7259/rN2LfIVe6AJEvPOeifAf1yNTq9l389xChktcYU QA7H65p3zZLyjVg9QusI9fcy2Y5uQBiqKvzc3pKWvtxglIuSOvu18htzyh0jnLo7uI mlBHP5tQn3Ncw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 294E5C2BA15; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:42 +0800 Subject: [PATCH v2 01/14] drm/mediatek: Add missing plane settings when async update Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-1-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=1082; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=ADiZlSVJT5s2sH18XbsNK2Wsb8sGtAwURKhvCjHjtzc=; b=gfNppxTA+mVrfrBvf5D7MJe0paBA2cf2WEfnKLHt5WTwPXCRiUEncV+qSTR2nzFgM60Hr96T1 tmWaMMjutARD9u9VKIGLeiFj60u/Eayszwxm0DgYRouHJEmN5VHa8tQ X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Fix an issue that plane coordinate was not saved when calling async update. Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic up= date") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_plane.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 4625deb21d40..a74b26d35985 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -227,6 +227,8 @@ static void mtk_plane_atomic_async_update(struct drm_pl= ane *plane, plane->state->src_y =3D new_state->src_y; plane->state->src_h =3D new_state->src_h; plane->state->src_w =3D new_state->src_w; + plane->state->dst.x1 =3D new_state->dst.x1; + plane->state->dst.y1 =3D new_state->dst.y1; =20 mtk_plane_update_new_state(new_state, new_plane_state); swap(plane->state->fb, new_state->fb); --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F0E61DA23 for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=W3PfMvVtImBLllcmU8Krh6TNYQc5NS4pwvNFDOLWx5Fj3FMJddD5GjKRNSzSCPFHODjMSRuRFK3BxqxRYCJoi/ZR27JEsuTTZbxMqNyJ3qJsT77zhn151gykjeXnqt7XQbnbY3xiGzek9CG6W5adNs2A/lJLyGbnv1DuaLQzQZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=nDauC53RPLl+Q/BbbOdZCjz+Z3uB4YVnDVwiZtsyjyI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uZbwJp/tP7KEY/zzhQR9BxD30fbZFpFwNCU3b6JxmaEBXjyHpEyMdhc/BT3Sjku61OYVGYuEkRw/vD8ZHLqjXX842YPv3hYuJL9G4+zrCauiDIu8VwSEfLnaToqCp+crrKI4wAqezNI+ASukfj8tUCHBBjfDK13FIYDbwy0/Xc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hLZP0Nm3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hLZP0Nm3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4B557C4AF08; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=nDauC53RPLl+Q/BbbOdZCjz+Z3uB4YVnDVwiZtsyjyI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hLZP0Nm3CCq7u0QNm3dsEW6z2DfRBa4g1HvFboR76ytNF+Lf3bDUBJnEyzTtZSKYX G7z8Hfxcemm9E56oC+CgocLU5ErVpwz+ntcnofBdG2IUz706CfRS8lAvr0jZlsKlWg OxZ7l2ib0vBgis4ziP2aA1fKGFDoio6CwFOyadttTks4UZ4caHJAAhvLPzgKJ2Gq2W 0cn0EPe7ke/2rfugJ6Eif+w3Kq2J+N0/5MJs6uSwgn8xrROgpFPhttsSD1Bt9DmMhP 1lBaht3NEKN1aUove0+jsCix8WMRqGEUFrp+5RYfp2t9mTnnTRKrnZIOqJHCUoi+w9 xjsYcFw+90hSQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C325C2BB85; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:43 +0800 Subject: [PATCH v2 02/14] drm/mediatek: Disable 9-bit alpha in ETHDR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-2-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=1465; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=6fbUX6KRvCRN0DJcJEcVUjxpKT4VpT1Y9qernMaYSKY=; b=rAjWRftMXK7ta3qYwsbvYnPDZglASvzGpDwQeQXLRflRp641iLxiTpYr355ls8TTAKEmmQQOi HUcBl+QvWPICO6GFX5hgSHOQYglYtF6BCNYAltDFsfJv+eHhahwnzPi X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung When 9-bit alpha is enabled, its value will be converted from 0-255 to 0-256 (255 =3D not defined). This is designed for special HDR related calculation, which should be disabled by default, otherwise, alpha blending will not work correctly. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 156c6ff547e8..d7d16482c947 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -50,7 +50,6 @@ =20 #define MIXER_INX_MODE_BYPASS 0 #define MIXER_INX_MODE_EVEN_EXTEND 1 -#define DEFAULT_9BIT_ALPHA 0x100 #define MIXER_ALPHA_AEN BIT(8) #define MIXER_ALPHA 0xff #define ETHDR_CLK_NUM 13 @@ -169,7 +168,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, - DEFAULT_9BIT_ALPHA, + MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); =20 --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D04E1381AD for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=SeV597wuny2aT2XajpkZQaHvbGXtUlEFmkku7nza5N5HEVaQvEO+ReBkiFVUPKp5CfD5en8/9ylAEJCzE0NDqh2pDhVr81MnCmhwm4NnF9taWlqIaLJa06mHqNraMyKEprr55sAJXRUxv3Y/Ahpm0Ea0W6PFiSmrv9W80FUzd/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=xSG4ggt1RhnwKCcON3d27r3nTFdYl7HIbvQnOx2vw8k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hvw3H07Ged4grL9wqRUBAhgiQiaxjD1dTdgekT/28kV/2S/qGRyEKCCKnuOMrF0NgoAJbqA92NQJwKAJFkTxddebZ5QzgIfhRnEquk0dshlBDBbQI7teoSewc0hhTY83hYPV4wluyvaLmB1XjlMCdyeHIL5GuZVAE17OS6Ou/m4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WVRZVFYI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WVRZVFYI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 66706C4AF0B; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=xSG4ggt1RhnwKCcON3d27r3nTFdYl7HIbvQnOx2vw8k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WVRZVFYIxv0xJ8hL4m6bjZNR6TVmK6ROMXs2LNq8bFQ4qWcrP67raxQZ1Xt9Z48FB Ppa6q6uWFYrZymrBL/Q5/5x6Q+b0sAcd3zhQBjWUTpf2/3X4Ox5RoiVPU/xgIYgCGt MSrKwezeKRTIrCAJaMdvOiU7cQ8JDrY9BCbD+LDqLOjosFXByCM4L1RzOv6H6wJKXy a06J4nrjkSuKqeY/YD1E1tbrxccTaqhVP8lw1kFKKAFzDTNtGmSv5aB2o/aXo0BDq0 ATA8uR5SCcjsZZxoGziHMCPy4mVsXOBrYVOC//Mn6sPCyTeKpoQ0MjWBPsPiuhmXEf gsyjpINDQlZLQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D037C27C79; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:44 +0800 Subject: [PATCH v2 03/14] drm/mediatek: Fix XRGB setting error in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-3-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=2960; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=tCYJPhSGMKi5TJvgnmhbxfJqIw69++3CeCs9woVV0N0=; b=pUAHlvinKKjzgS181sqboo/x/W3xdQvnPjuGlVgWHaQXIl3b1l0MFVjYkBQ6dEIXlYUTsumct Ru7FgzaieZ1Bc2NNdp5Pd2WieXj/v2PR5ncTSQk7LYc0HllQe+cc1as X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung CONST_BLD must be enabled for XRGB formats although the alpha channel can be ignored, or OVL will still read the value from memory. This error only affects CRC generation. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index b552a02d7eae..bd00e5e85deb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -38,6 +38,7 @@ #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) +#define OVL_CONST_BLEND BIT(28) #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 @@ -407,6 +408,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; union overlay_pitch { @@ -428,6 +430,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, if (state->base.fb && state->base.fb->format->has_alpha) con |=3D OVL_CON_AEN | OVL_CON_ALPHA; =20 + /* CONST_BLD must be enabled for XRGB formats although the alpha channel + * can be ignored, or OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (state->base.fb && !state->base.fb->format->has_alpha) + ignore_pixel_alpha =3D OVL_CONST_BLEND; + if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; addr +=3D (pending->height - 1) * pending->pitch; @@ -443,8 +453,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq= _reg, ovl->regs, - DISP_REG_OVL_PITCH(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pi= xel_alpha, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 919B91F956 for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=WzYjbxzwBJchIBeiVjbUnJtkZSQzpQ8qPz1OeuXF1HOAaJpcUOKN3bt8PVxVPk7piVJO+GPbQZg2ztcBWw10b2vzeut/07owtwznKQo1Fl5s/Vt3xpLGm4gBlWKCaHDc32iWTvoCHX0tPSFlz77yhK3cIcJNkzXZojh5zpViFrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IpYBVRpoYH36rxzedojh//lQE3Hrwk8f+YiXFMr9YfiKtsmcdWhOWwrUU8D140ojKte0yYKmitONLkf8dadV/baH3SanqtSZ3aww0pqvAZ1F2rFDZxjEIztaAxFvzF3efqrOuKIi/ly9jKMsVlna8HjTR9s5SUk/IusUATYUoF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AwtOrjFp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AwtOrjFp" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6B26CC4AF0C; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=GMUTsruzzAYn0n7hmwAGt8zwytpi3KhL2H6cMAMOTwM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AwtOrjFpZGTO8bfHqaprHnw7Wv1EhZUdblvMILrHdpEYGJsHjWokHIXklVLecdbmV u0zSHy/mnth9/Y4D41yk0CKFSYK00IVp79AuoTC9J8LDcC8ziZNbTOfh2p48hRxll3 MVFhFSqLnDhrdoR13eSxdcY6RBf0wTbM0GQjImMR3MGNrmLXjwzFhnn8w0t8+JcXL4 LdgQ8/sK6NdVmjsEkvT6r2BjaX0XkekDEGOagNIWsYk80zWFuU+VsPgQ5Q5eZ/g3+l abmfBzAn0Qde9eZ4YNfkVr2raVmVh4RUhpi7FBXCcIHVlJIodUQzttzjMxBuhdK3Wi LcF/fm49U/e3Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D999C2BC81; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:45 +0800 Subject: [PATCH v2 04/14] drm/mediatek: Fix XRGB setting error in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-4-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=1806; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=iVCN8PnNVHs904I6AJ55kOr+V0K7XkkYFUBoVjBPemw=; b=zbO/9yDD3WrlwV9aQXD6T+LzL1cDtdTW68MZGIuRnNbMqkjeBif3cfxVoBAvkCBbMTkAfPGVb Mu0y7+d2FJ9CemdbDBflMXCNL+97grlHDtu7EiQ0+/4OM90yy+o56jq X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Although the alpha channel in XRGB formats can be ignored, ALPHA_CON must be configured accordingly when using XRGB formats or it will still affects CRC generation. Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index d7d16482c947..5c52e514ae30 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -153,6 +153,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, unsigned int offset =3D (pending->x & 1) << 31 | pending->y << 16 | pendi= ng->x; unsigned int align_width =3D ALIGN_DOWN(pending->width, 2); unsigned int alpha_con =3D 0; + bool replace_src_a =3D false; =20 dev_dbg(dev, "%s+ idx:%d", __func__, idx); =20 @@ -167,7 +168,15 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (state->base.fb && state->base.fb->format->has_alpha) alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, + if (state->base.fb && !state->base.fb->format->has_alpha) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a =3D true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B760E22619 for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=DU2XzwxdY3fhxmcXbkKae3BE0GyRINqciIk3INYWaeSepTks21nTGsUFHUPinxZh11gidM5p5IPf1jsvxVXpKaMl3UFH/wp74D2VCSvYsit7KqnE095+/5qfDpOgjyXgzU8DgHzJzsriHCyYECAvzGwxm2DdmoFpsmQMNtHBLs4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=nk/C+wqrXVMA9amh6fPshkrHE4xq3UlYmGyCf1hutnA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YAppX+KsB0CcKJhs6lgFnuTDAjEG6vmX8KPfomWgsDirgXPGGIZOokkKmM1wPJ9IEv7HZU+P0fwk+XH67xcGS2h89Y7mYUHz77p6TkjGHzdSqyF3A3uuMqoVk15wXlh3ahblEGpTwV/cMbN1fbAvv8tIh8Q0QumOIDaXAvpa2n4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BP8tPFL3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BP8tPFL3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7F0ECC4AF0D; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=nk/C+wqrXVMA9amh6fPshkrHE4xq3UlYmGyCf1hutnA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BP8tPFL3sF5bndbwmFOYxqr1xPQjGksocrhH4DbNOGYKzeBJFyw9tN1fcv6IX0GqO E3IkEmVK3nfOMJTHhPSAJOhI4zS5IDH2Wvm0nWxo/kBqkeQW9MvRvTzESG14ukJa14 hcwxIzhH2Q9KDVx7MPhc20JfU9DVVR6DiOcjZytYTd24taeb9JvNSFf/kN76L3yPCN 6BbyJ9JMK1hBSGnBiGchuR+9+f1gxplEgKTorZNEZVkWhItEI0K+IYXNDFPtSYnwX/ p1sBAZcWEH+FSBlwODN4laQf3nGQvogWl2DL69VuhuA896lLxIQCBpRUR2kxTXlngb 1Q36jiWI2PLkw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EA1AC27C53; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:46 +0800 Subject: [PATCH v2 05/14] drm/mediatek: Turn off the layers with zero width or height Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-5-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=2110; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=1wAQfpFBsYHGAPuLXbpDgCF0uuBRyet+FxYXId9fMr0=; b=4/WwoVatxWG2vheNbELUaPi42wc85qaLAOkL3Dn5ulQNtClLAgS8OyN5j11wyNvQpAfMJP6Pw qt4nIxA2BGoA5jIJSpwOF4/OmpSyOnhF9fTx4KtCBlS6yBRnl3XFY9k X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195") Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 02dd7dcdfedb..2b62d6475918 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 5c52e514ae30..bf5826b7e776 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -160,7 +160,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (idx >=3D 4) return; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZ= E(idx)); return; } --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D16E538FB0 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-6-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=1050; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=BgdlkkD28fU8kVaiXpAjJEsbIm8CSiJsfkQTGRrkbL8=; b=nrDkN0T+6iVl3vSI8cuh8yGey8rxcZiI+R/SBD2LO/UWpIp5k8KvBn9DoKkxLtnGXScDdjCdR 9WiQWMBlLzyB7oKGHHKHZ8uTDkqxcfl5HpKekKi7m+2sPczpep5f8HX X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Add OVL compatible name for MT8195. Without this commit, DRM won't work after modifying the device tree. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index b5f605751b0a..8e047043202b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -743,6 +743,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8192-disp-ovl", .data =3D (void *)MTK_DISP_OVL }, + { .compatible =3D "mediatek,mt8195-disp-ovl", + .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8183-disp-ovl-2l", .data =3D (void *)MTK_DISP_OVL_2L }, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7AA82261D for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=Q0WvhIIHsRbpMDtLI6zlcnw+y6r1JYQjaZUSOQrhhPSYf0FXM5ZKhCb8LFqADkV4nBlCwyM7vOaVnxZiQ4EDpbyl9mJsOspk57ZoqE4mWtCfsCWdtWsHgGs07np/oEPMFDL8whSHnQKWg1v0ykEwOdfe3fI8gWVny+cTDnV5unk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; bh=3aWzivexV5OnPdHVvbgtL9q6cZA0n9TwnH6JwwcATE4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rUMpMG6tRx3yIYDUTXyrN9qaRKgttVJi2txzXyZcADa0RCt718Qf50V5LBQb7SF9yUwxAqYhP8gdGDzErDDHU8ZJcnbXkvu8bHJvWOlQzqOfLZIGcG590RIWKNy7bmEAOvOqaZvkGccD64aNwfLp4+jAYJHHDNbSuaqslfQvJXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ULgFEi/I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ULgFEi/I" Received: by smtp.kernel.org (Postfix) with ESMTPS id A662BC4AF0E; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807534; bh=3aWzivexV5OnPdHVvbgtL9q6cZA0n9TwnH6JwwcATE4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ULgFEi/IAO27gYLvrIVQrMwdiwXE5ksvrBvLu3yVvdX6PRPWdFcOctdW6q45Fewkg mxbCO24QwntMSjIu8QbCxp7FmNmkAJuHqyxQeQpRGhnZzvKy5NBlfSa4d4hfzmB0yR 0wk7ZLD6N4IjU2/82Es+XEVq/b91WC3s2v3MSiPz2Br5nTQrTTTLmOM3maA9SH9cy5 iJ4YAck6+kR33FAt0XT6Y9ejZ1xJ+kTjFg8HWwk2CjYBPmzH4XHUBAYNu/R/Zmf5za 5z8JJI7W+/e/9I0N/yxqREdqhqHdvCtkGNFIhTEg/vdB8dowaIyFkml2bCH5qznJec bDdWT7Wz3KUyg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BEF2C27C79; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:48 +0800 Subject: [PATCH v2 07/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-7-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=3032; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=Rr3Cn0zcHA1tgf1aiwUMCaOAX6oP85JESJH6W+QO72g=; b=X89nl0hoD9/fxKLIjA9LXFs1fIXdKluqoGGwHoFrQZBrBCJIcnaoO9Y3h78jYD05f3OBcoyQl qYLesDX019rAOtwzWEl8wD/sEsN/BhOWVltvLMMBytdVIgz+qWA85IP X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Always add DRM_MODE_ROTATE_0 to rotation property to meet IGT's (Intel GPU Tools) requirement. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 6 +++++- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------ drivers/gpu/drm/mediatek/mtk_plane.c | 2 +- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 26236691ce4c..f7fe2e08dc8e 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -192,7 +192,11 @@ unsigned int mtk_ddp_comp_supported_rotations(struct m= tk_ddp_comp *comp) if (comp->funcs && comp->funcs->supported_rotations) return comp->funcs->supported_rotations(comp->dev); =20 - return 0; + /* + * In order to pass IGT tests, DRM_MODE_ROTATE_0 is required when + * rotation is not supported. + */ + return DRM_MODE_ROTATE_0; } =20 static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index bd00e5e85deb..880ef61ccc92 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -297,27 +297,20 @@ int mtk_ovl_layer_check(struct device *dev, unsigned = int idx, struct mtk_plane_state *mtk_state) { struct drm_plane_state *state =3D &mtk_state->base; - unsigned int rotation =3D 0; =20 - rotation =3D drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - rotation &=3D ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) !=3D 0) + /* check if any unsupported rotation is set */ + if (state->rotation & ~mtk_ovl_supported_rotations(dev)) return -EINVAL; =20 /* * TODO: Rotating/reflecting YUV buffers is not supported at this time. * Only RGB[AX] variants are supported. + * Since DRM_MODE_ROTATE_0 means "no rotation", we should not + * reject layers with this property. */ - if (state->fb->format->is_yuv && rotation !=3D 0) + if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) return -EINVAL; =20 - state->rotation =3D rotation; - return 0; } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index a74b26d35985..1723d4333f37 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -338,7 +338,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_p= lane *plane, return err; } =20 - if (supported_rotations & ~DRM_MODE_ROTATE_0) { + if (supported_rotations) { err =3D drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, supported_rotations); --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD58A3B182 for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; cv=none; b=G4baNlz4GjjwGU+6qiEsPo68IlpinWY/EntyuhGko/GFWiwyQCdAz7lvdQbnXgEc7M+Gx4hYqm144HU6W33pqPSCRmfjFI9szaBUCrfdbBhdg+tSGRoQcCNVbITIWwHhOI9+OXELGj/6K4f+eBhD/lwfMUUr3l+isLq1jrLy2Mo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807534; c=relaxed/simple; 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Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:49 +0800 Subject: [PATCH v2 08/14] drm/mediatek: Add new color format MACROs in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-8-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=2232; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=oUVv7apF4+nnjxXV56NKRfwr0Y4AFgBqQp/J41EVF8c=; b=CurnOUQgY9U6U5M2zMATgsFC1vs0x2x3pnYy8evYWtiNqeVJKwC9GAWJg9+fl9t91UoRWXXQu C1C7qcO6aT0AMidpUF7y6DA+NhN+R6yOWP+msh/CWnG2qQLIHQbVxMp X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Define new color formats to hide the bit operation in the MACROs to make the switch statement more concise. Change the MACROs to align the naming rule in DRM. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 880ef61ccc92..3724f77c5b6b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -55,8 +55,10 @@ #define OVL_CON_BYTE_SWAP BIT(24) #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB (1 << 12) -#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) -#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_ARGB8888 (2 << 12) +#define OVL_CON_CLRFMT_RGBA8888 (3 << 12) +#define OVL_CON_CLRFMT_ABGR8888 (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SW= AP) +#define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SW= AP) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -369,18 +371,18 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: - return OVL_CON_CLRFMT_ARGB8888; + return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: case DRM_FORMAT_BGRA1010102: - return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_CLRFMT_BGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ARGB2101010: - return OVL_CON_CLRFMT_RGBA8888; + return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: - return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_CLRFMT_ABGR8888; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB9022262B for ; Wed, 19 Jun 2024 14:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-9-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=3538; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=rS4Xgj0LEBxL5IBSK6SfigvQYUwjVgXB9N8a+kyhjQ0=; b=Fp9AGslx+lI67r6rismPXijrPNV9pFijNLIzOFu3BRWE8mAciFgSXIpAswNVyRzNxbrwPu8AR DjN5b5VtzDBAKBc6UGiYaOQxEtfq3GLca1s9p8+AdNY94AONyYSulbh X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Set DRM mode configs limitation according to the hardware capabilities and pass the IGT checks as below: - The test "graphics.IgtKms.kms_plane" requires a frame buffer with width of 4512 pixels (> 4096). - The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is defined, and run the test with cursor size from 1x1 to 512x512. Please notice that the test conditions may change as IGT is updated. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 8e047043202b..c9cad3a82737 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -294,6 +294,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .conn_routes =3D mt8188_mtk_ddp_main_routes, .num_conn_routes =3D ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { @@ -308,6 +311,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 0_driver_data =3D { .main_path =3D mt8195_mtk_ddp_main, .main_len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data =3D { @@ -315,6 +321,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 1_driver_data =3D { .ext_len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), .mmsys_id =3D 1, .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 2, /* 2-pixel align when ethdr is bypassed */ + .min_height =3D 1, }; =20 static const struct of_device_id mtk_drm_of_ids[] =3D { @@ -493,6 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm) for (j =3D 0; j < private->data->mmsys_dev_num; j++) { priv_n =3D private->all_drm_private[j]; =20 + if (priv_n->data->max_width) + drm->mode_config.max_width =3D priv_n->data->max_width; + + if (priv_n->data->min_width) + drm->mode_config.min_width =3D priv_n->data->min_width; + + if (priv_n->data->min_height) + drm->mode_config.min_height =3D priv_n->data->min_height; + if (i =3D=3D CRTC_MAIN && priv_n->data->main_len) { ret =3D mtk_crtc_create(drm, priv_n->data->main_path, priv_n->data->main_len, j, @@ -520,6 +538,10 @@ static int mtk_drm_kms_init(struct drm_device *drm) } } =20 + /* IGT will check if the cursor size is configured */ + drm->mode_config.cursor_width =3D drm->mode_config.max_width; + drm->mode_config.cursor_height =3D drm->mode_config.max_height; + /* Use OVL device for all DMA memory allocations */ crtc =3D drm_crtc_from_index(drm, 0); if (crtc) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 78d698ede1bf..ce897984de51 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,10 @@ struct mtk_mmsys_driver_data { bool shadow_register; unsigned int mmsys_id; unsigned int mmsys_dev_num; + + u16 max_width; + u16 min_width; + u16 min_height; }; =20 struct mtk_drm_private { --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 080BE3E47E for ; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-10-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=3007; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=mrSvvVZ/mFrWd71ZaekcuPkD1pvqPrfCwDLvo7/MQM0=; b=m1P49byuk48IKl42u3xDxi+FR7/4d7bKlfXD7KFC0FQozyD/EWnb7AIOi/PtZRvjHtNrnifNN 2BK6KgEjQ5nCr+VyCmA9f5W8XZDoZUsrQMk4yr7XRGVVOTi9CeX6s+0 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support more 10bit formats in OVL. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +++++++++++++++++++++++++++++= --- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 3724f77c5b6b..671b1258d9c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -74,6 +74,22 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) =20 +static inline bool is_10bit_rgb(u32 fmt) +{ + switch (fmt) { + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + return true; + } + return false; +} + static const u32 mt8173_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -91,12 +107,18 @@ static const u32 mt8173_formats[] =3D { static const u32 mt8195_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX1010102, DRM_FORMAT_BGRA1010102, DRM_FORMAT_ABGR8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX1010102, + DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, DRM_FORMAT_RGB565, @@ -256,9 +278,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, i= nt idx, u32 format, reg =3D readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); reg &=3D ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); =20 - if (format =3D=3D DRM_FORMAT_RGBA1010102 || - format =3D=3D DRM_FORMAT_BGRA1010102 || - format =3D=3D DRM_FORMAT_ARGB2101010) + if (is_10bit_rgb(format)) bit_depth =3D OVL_CON_CLRFMT_10_BIT; =20 reg |=3D OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); @@ -371,17 +391,23 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_BGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: return OVL_CON_CLRFMT_ABGR8888; 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Wed, 19 Jun 2024 14:32:14 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:52 +0800 Subject: [PATCH v2 11/14] drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-11-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=841; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=UFfbnC0Pk+UyDIilXA9CBuArzD2VEBaxjen+ZQRfSQA=; b=PSTLyTlCrPco9xY23+obmFFokEvg7Hv7ZDW/+98AnpFtFaL1N2wbvIJpIUrm41sonE2UBa7Wp 39Ay5MhUleDCvuEHdepP3AugZ4dlViRy1hq7lnDwbtUfaLoZ1Qc+EsM X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support RGBA8888 and RGBX8888 formats in OVL on MT8195. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 671b1258d9c8..33b58da15ba4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -117,6 +117,8 @@ static const u32 mt8195_formats[] =3D { DRM_FORMAT_XBGR8888, DRM_FORMAT_XBGR2101010, DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX1010102, DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F68A446B4 for ; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807535; cv=none; b=OWScMAetXb1TOKuW1O/OGfeE/mC6H7Qu/NKM2p8QPhmkCSho3xdz5yWbxqdw8bl+Sd25HylbKEC26YraMCdEPxO1DZAIGR0cweYxGFECtSqq8Wy65sfE93nYF1c8RWUm5aZr6KgwlhuB3BmAix8NNwfvdJEPiKOTzwKWd5xAESQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807535; c=relaxed/simple; bh=H/xL/aaPV6K8CRmLwrIEXZNxCXF2qf6RiWqeP4TRBnQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OTR3JBDnXzEH52B0THtPOAy99vX+NsestvKb54eQMrA4EXA+P0PtIMVL8n+/KMi/ZlRswxeoHhaXVWazcqxBaos32qjNVI3P35hCE4tXi2w7Gr1dBKG2HK3S77nvPGGr2MxXjx6nIkZfesrNmXscWcZxHsvxabbt5J8odoWH8MM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EegmEYte; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EegmEYte" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0F808C4AF4D; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807535; bh=H/xL/aaPV6K8CRmLwrIEXZNxCXF2qf6RiWqeP4TRBnQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EegmEYteY1gHWVTtILoHw2PhGPJPHuKz4aAZQgy2nze85EQ9az7z1XZM+LypdeUrv BvWWORmmE96Kv9ZYuzRqcfVkng/0rMiwDoCo76ERlFzMYC3dnDqh9kIh0qUp4+ojxh D96IKmuj8eO0oGw/X+/MuUGc0TPApNCksgCWxFKIJTn5nmNRSoy0hnF2ahK7gw2H9C elYmMishTalT4VP09fjVplHVkI+1liiMJK/AyZXj2/iJqqiRSvgchYbI6+RIQcOqEC VnlqNKemyO+ZRppHQEJSV32WPIdC7JN4QmNG4//FU8IQEW66q/roi1mtDn8xmJaDdH fADzNVB7IeG0g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05DC8C27C53; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:53 +0800 Subject: [PATCH v2 12/14] drm/mediatek: Support DRM plane alpha in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-12-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=1074; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=A1tCyNili9ONVchgKYjd+o0ng6Y8jo6rrmL1JAOqRUE=; b=rnRBBesRm9lrD0ENLA6aPqPsEUWcRgvzTppHIxL520esIcoOx43LOqcoP3OpMUIS4DG1zkvNQ oG/KM2onM+1AeTIJYBt2+umWJhT9AypTPKce2GGgN/shhjiC+8ZdNyA X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Set the plane alpha according to DRM plane property. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 33b58da15ba4..f358dbfed5e3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -450,8 +450,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, } =20 con =3D ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |=3D OVL_CON_AEN | OVL_CON_ALPHA; + if (state->base.fb) { + con |=3D OVL_CON_AEN; + con |=3D state->base.alpha & OVL_CON_ALPHA; + } =20 /* CONST_BLD must be enabled for XRGB formats although the alpha channel * can be ignored, or OVL will still read the value from memory. --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41BF645BEF for ; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807535; cv=none; b=bdWo4z+0mx3KC9ig9rHPrXCe0Tp6+MU6IHiuP9VLOO6yzcdIRyh7rF6+4bv0Pi6ct1ymG9DMaISZ7psT20fE3D8gwGXPC1Xykth8KUTUaJLh1GhP9IcU5/5EY2UBpk8co4yBn1KidJD6CaIrA4ci4glgd6ySOlLcCSQE0q6EUjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807535; c=relaxed/simple; bh=7I8aImA7pkdTjSfDGsH5pzBGFaEl5gU0gk3Hz8BCIzM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rVHCE6HUQaD6x5nv9c5h8Bytf7fJ+gUdo0ILSkDZ3Mt9RcX9IxgSPmPPG5fRqMeXTpmh2mN+cvY4WJpAIVWb/HcCNqL1oe35HBxIInnIq2K5nQ80HU3XQDkPKhZLLTv9/0ODbIYGJAu0V7U4zdo7dOoV3ZVF8jDx0itK5zJVB5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HNpuobnk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HNpuobnk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 21F20C4AF5F; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807535; bh=7I8aImA7pkdTjSfDGsH5pzBGFaEl5gU0gk3Hz8BCIzM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HNpuobnklSoOj6aoufKEc5UePTl0BWcI/G/ndpkPM9zPy5kj3U2LDjds5ybUlp75S 8fnLhqeQ8t6DWJbl8zF1D6Sf51KoN/4KPDsykjLTRurzzE3tbohiHoGajXwD9b7P9X 9uwhUlPOVYE4e04JaQdiUX4CCL8eFoqk2i+jQzAtFk6yDymQNpmU2RGs4/WRyQ/SUf myWdceJQIhMTa3tr3ld/0GdrZBOnclo8lbLJr1Bxor0+CwYt2kBvo7nbXDGLGUL7YQ 9UipZRzs9uSXx9lAvq+Oa6XFRGrJqvFwf16yAlzMy8NA1Np8Mr+4TVI4GSpIgt4g1q HTGTjPhv/9bYg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19BE9C27C79; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:54 +0800 Subject: [PATCH v2 13/14] drm/mediatek: Support DRM plane alpha in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-13-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=984; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=wRuukHEj6ar3MzrXsZ6wMBC1YWkwtR1Cd5NiPWkH4fQ=; b=mXffXrDFXrHd8s/MoUIUUbt/P7yp7KbzAnh4zOUemxlxHfiBroL5wHk35yF0/DMHdRIAWLfR2 d4oOEUBWMpeA2jzbQDTSaw/jhwFjI+xMSQDX1+voFSDc/N3erHWWKGS X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Set the plane alpha according to DRM plane property. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index bf5826b7e776..36021cb8df62 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -170,8 +170,10 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, return; } =20 - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; + if (state->base.fb) { + alpha_con |=3D MIXER_ALPHA_AEN; + alpha_con |=3D state->base.alpha & MIXER_ALPHA; + } =20 if (state->base.fb && !state->base.fb->format->has_alpha) { /* --=20 Git-146) From nobody Thu Sep 19 23:04:59 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CCC147779 for ; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807535; cv=none; b=CmyFzcUC0r5wV4H3AAyPLynuVWX3pSl9xTvBqXpGd37gqNonllaxEGxCDvqwWwrxPtZ0NtGZqVHh1UOnHB3nBJo0mb3s9BldBDwRAMcXoK4nwS1bLvlK/TnzQS5M7V1P2GNyqlPaWwgOaO60tzpUk7n+X+WRNdFlZjPFGjk55UY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718807535; c=relaxed/simple; bh=683XBBTcCjvNlqsnqsvC5qU2ha2+uSLRYzWNbExOTr8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YTq8AS0nQXU/2aFiX92HvJnw/8LysLpUg64n04aC071wzG4rW/NRZQIU/jEZIMV2PsKZvrzq2kAE3mpUMyFgftS1ekRlY94+j+Q4KNadZ8z+hGhI6C3UvR/+Ip/RmqlLP3kinNBqUAM7prcU3o4dZ1RI0KpTQ9kPN5IWCmq74xM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=txRLZHMw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="txRLZHMw" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2E9F4C4AF61; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718807535; bh=683XBBTcCjvNlqsnqsvC5qU2ha2+uSLRYzWNbExOTr8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=txRLZHMwbTzif/kI0RBsVhAlpzzjw9EWMOsJ9pKS338xPVGTcpoHA9P92VGa1x8pe edXEu1CoLeViLtW9T21Wpt5qvUz0HiFNnsWx7wUV2ZD8knp6Dce+ndPKqpw7mL3DP4 Q82EvBG/TZJ0OPYK+ilzq2ltYFU3jD/mNXFNTA1r/AWG09f4kiwiCBqowERGpsJ6A2 ZxN7jNjBpuCt8Doq9GFQGyYaitABO7OH8pujajqz+aV++tlNEV6YmGXBPRIHuU1/WK KiTq8jlqyML52lKrIXYFW/bJVv5mA+gRmF0YqoF7n6GlQZN6e2e2y1NPooMLZjFxV0 l4uDZkimFW3eQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2743AC27C53; Wed, 19 Jun 2024 14:32:15 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 19 Jun 2024 22:30:55 +0800 Subject: [PATCH v2 14/14] drm/mediatek: Fix XRGB setting error in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240619-mediatek-drm-next-v2-14-abf68f46f8d2@mediatek.com> References: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> In-Reply-To: <20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718807531; l=1547; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=N+q+J8F01q3+w5AJm23nX2Ta3bBWa72KPt0JkxnFDyM=; b=UGkb80MLoatE4rhTH91SKYMfduSoEsuHwJOGEjgG5YhEsMiyJ77CyrZu85rwXyMZq3lSE0pKP BuGab+SbGDVCkdRv1qaDjrNhTvABHv31tqQubuZZIXknz7+ZNzsYWPw X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung CONST_BLD must be enabled for XRGB formats although the alpha channel can be ignored, or OVL will still read the value from memory. This error only affects CRC generation. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.= ") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index f358dbfed5e3..6abefc338045 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -455,6 +455,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, con |=3D state->base.alpha & OVL_CON_ALPHA; } =20 + /* CONST_BLD must be enabled for XRGB formats although the alpha channel + * can be ignored, or OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (state->base.fb && !state->base.fb->format->has_alpha) + ignore_pixel_alpha =3D OVL_CONST_BLEND; + /* CONST_BLD must be enabled for XRGB formats although the alpha channel * can be ignored, or OVL will still read the value from memory. * For RGB888 related formats, whether CONST_BLD is enabled or not won't --=20 Git-146)