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Rename the binding doc to reflect that fact and make the naming more precise. Signed-off-by: Sam Protsenko --- .../{samsung,exynos5250-trng.yaml =3D> samsung,exynos-trng.yaml} | 2 +- MAINTAINERS | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/rng/{samsung,exynos5250-trng.yaml= =3D> samsung,exynos-trng.yaml} (91%) diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.= yaml b/Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml similarity index 91% rename from Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.y= aml rename to Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml index 765d9f9edd6e..99c382d25c11 100644 --- a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml +++ b/Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/rng/samsung,exynos5250-trng.yaml# +$id: http://devicetree.org/schemas/rng/samsung,exynos-trng.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Samsung Exynos SoC True Random Number Generator diff --git a/MAINTAINERS b/MAINTAINERS index 4f09bdb5657e..511939a4c3f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19878,7 +19878,7 @@ SAMSUNG EXYNOS TRUE RANDOM NUMBER GENERATOR (TRNG) = DRIVER M: =C5=81ukasz Stelmach L: linux-samsung-soc@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml +F: Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml F: drivers/char/hw_random/exynos-trng.c =20 SAMSUNG FRAMEBUFFER DRIVER --=20 2.39.2 From nobody Wed Dec 17 06:30:02 2025 Received: from mail-oo1-f52.google.com (mail-oo1-f52.google.com [209.85.161.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26D5B4C6D for ; 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Mon, 17 Jun 2024 17:37:45 -0700 (PDT) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5bd5e19e943sm1229935eaf.23.2024.06.17.17.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 17:37:44 -0700 (PDT) From: Sam Protsenko To: =?UTF-8?q?=C5=81ukasz=20Stelmach?= , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Olivia Mackall , Herbert Xu , Alim Akhtar , linux-samsung-soc@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: rng: Add Exynos850 support to exynos-trng Date: Mon, 17 Jun 2024 19:37:38 -0500 Message-Id: <20240618003743.2975-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240618003743.2975-1-semen.protsenko@linaro.org> References: <20240618003743.2975-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TRNG block in Exynos850 is pretty much the same as in Exynos5250, but there are two clocks that has to be controlled to make it work: 1. Functional (operating) clock: called ACLK in Exynos850, the same as "secss" clock in Exynos5250 2. Interface (bus) clock: called PCLK in Exynos850. It has to be enabled in order to access TRNG registers Document Exynos850 compatible and the related clock changes, and provide a corresponding example for Exynos850 TRNG node with ACLK and PCLK clocks. Signed-off-by: Sam Protsenko --- .../bindings/rng/samsung,exynos-trng.yaml | 49 +++++++++++++++++-- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml= b/Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml index 99c382d25c11..e57310fa89c7 100644 --- a/Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml +++ b/Documentation/devicetree/bindings/rng/samsung,exynos-trng.yaml @@ -12,14 +12,17 @@ maintainers: =20 properties: compatible: - const: samsung,exynos5250-trng + enum: + - samsung,exynos5250-trng + - samsung,exynos850-trng =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - items: - - const: secss + minItems: 1 + maxItems: 2 =20 reg: maxItems: 1 @@ -30,6 +33,35 @@ required: - clock-names - reg =20 +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos850-trng + + then: + properties: + clocks: + items: + - description: SSS (Security Sub System) operating clock + - description: SSS (Security Sub System) bus clock + + clock-names: + items: + - const: secss + - const: pclk + + else: + properties: + clocks: + items: + - description: SSS (Security Sub System) operating clock + + clock-names: + items: + - const: secss + additionalProperties: false =20 examples: @@ -42,3 +74,12 @@ examples: clocks =3D <&clock CLK_SSS>; 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Mon, 17 Jun 2024 17:37:45 -0700 (PDT) From: Sam Protsenko To: =?UTF-8?q?=C5=81ukasz=20Stelmach?= , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Olivia Mackall , Herbert Xu , Alim Akhtar , linux-samsung-soc@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] hwrng: exynos: Improve coding style Date: Mon, 17 Jun 2024 19:37:39 -0500 Message-Id: <20240618003743.2975-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240618003743.2975-1-semen.protsenko@linaro.org> References: <20240618003743.2975-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Fix obvious style issues. Some of those were found with checkpatch, and some just contradict the kernel coding style guide. No functional change. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- drivers/char/hw_random/exynos-trng.c | 61 +++++++++++++--------------- 1 file changed, 29 insertions(+), 32 deletions(-) diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/= exynos-trng.c index 0ed5d22fe667..88a5088ed34d 100644 --- a/drivers/char/hw_random/exynos-trng.c +++ b/drivers/char/hw_random/exynos-trng.c @@ -23,45 +23,41 @@ #include #include =20 -#define EXYNOS_TRNG_CLKDIV (0x0) - -#define EXYNOS_TRNG_CTRL (0x20) -#define EXYNOS_TRNG_CTRL_RNGEN BIT(31) - -#define EXYNOS_TRNG_POST_CTRL (0x30) -#define EXYNOS_TRNG_ONLINE_CTRL (0x40) -#define EXYNOS_TRNG_ONLINE_STAT (0x44) -#define EXYNOS_TRNG_ONLINE_MAXCHI2 (0x48) -#define EXYNOS_TRNG_FIFO_CTRL (0x50) -#define EXYNOS_TRNG_FIFO_0 (0x80) -#define EXYNOS_TRNG_FIFO_1 (0x84) -#define EXYNOS_TRNG_FIFO_2 (0x88) -#define EXYNOS_TRNG_FIFO_3 (0x8c) -#define EXYNOS_TRNG_FIFO_4 (0x90) -#define EXYNOS_TRNG_FIFO_5 (0x94) -#define EXYNOS_TRNG_FIFO_6 (0x98) -#define EXYNOS_TRNG_FIFO_7 (0x9c) -#define EXYNOS_TRNG_FIFO_LEN (8) -#define EXYNOS_TRNG_CLOCK_RATE (500000) - +#define EXYNOS_TRNG_CLKDIV 0x0 + +#define EXYNOS_TRNG_CTRL 0x20 +#define EXYNOS_TRNG_CTRL_RNGEN BIT(31) + +#define EXYNOS_TRNG_POST_CTRL 0x30 +#define EXYNOS_TRNG_ONLINE_CTRL 0x40 +#define EXYNOS_TRNG_ONLINE_STAT 0x44 +#define EXYNOS_TRNG_ONLINE_MAXCHI2 0x48 +#define EXYNOS_TRNG_FIFO_CTRL 0x50 +#define EXYNOS_TRNG_FIFO_0 0x80 +#define EXYNOS_TRNG_FIFO_1 0x84 +#define EXYNOS_TRNG_FIFO_2 0x88 +#define EXYNOS_TRNG_FIFO_3 0x8c +#define EXYNOS_TRNG_FIFO_4 0x90 +#define EXYNOS_TRNG_FIFO_5 0x94 +#define EXYNOS_TRNG_FIFO_6 0x98 +#define EXYNOS_TRNG_FIFO_7 0x9c +#define EXYNOS_TRNG_FIFO_LEN 8 +#define EXYNOS_TRNG_CLOCK_RATE 500000 =20 struct exynos_trng_dev { - struct device *dev; - void __iomem *mem; - struct clk *clk; - struct hwrng rng; + struct device *dev; + void __iomem *mem; + struct clk *clk; + struct hwrng rng; }; =20 static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max, bool wait) { - struct exynos_trng_dev *trng; + struct exynos_trng_dev *trng =3D (struct exynos_trng_dev *)rng->priv; int val; =20 max =3D min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4)); - - trng =3D (struct exynos_trng_dev *)rng->priv; - writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL); val =3D readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val, val =3D=3D 0, 200, 1000000); @@ -122,7 +118,7 @@ static int exynos_trng_probe(struct platform_device *pd= ev) =20 trng->rng.init =3D exynos_trng_init; trng->rng.read =3D exynos_trng_do_read; - trng->rng.priv =3D (unsigned long) trng; + trng->rng.priv =3D (unsigned long)trng; =20 platform_set_drvdata(pdev, trng); trng->dev =3D &pdev->dev; @@ -175,7 +171,7 @@ static int exynos_trng_probe(struct platform_device *pd= ev) =20 static void exynos_trng_remove(struct platform_device *pdev) { - struct exynos_trng_dev *trng =3D platform_get_drvdata(pdev); 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charset="utf-8" Some SoCs like Exynos850 might require the SSS bus clock (PCLK) to be enabled in order to access TRNG registers. Add and handle optional PCLK clock accordingly to make it possible. Signed-off-by: Sam Protsenko --- drivers/char/hw_random/exynos-trng.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/= exynos-trng.c index 88a5088ed34d..4520a280134c 100644 --- a/drivers/char/hw_random/exynos-trng.c +++ b/drivers/char/hw_random/exynos-trng.c @@ -47,7 +47,8 @@ struct exynos_trng_dev { struct device *dev; void __iomem *mem; - struct clk *clk; + struct clk *clk; /* operating clock */ + struct clk *pclk; /* bus clock */ struct hwrng rng; }; =20 @@ -141,10 +142,23 @@ static int exynos_trng_probe(struct platform_device *= pdev) goto err_clock; } =20 + trng->pclk =3D devm_clk_get_optional(&pdev->dev, "pclk"); + if (IS_ERR(trng->pclk)) { + ret =3D dev_err_probe(&pdev->dev, PTR_ERR(trng->pclk), + "cannot get pclk"); + goto err_clock; + } + + ret =3D clk_prepare_enable(trng->pclk); + if (ret) { + dev_err(&pdev->dev, "Could not enable the pclk.\n"); + goto err_clock; + } + ret =3D clk_prepare_enable(trng->clk); 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Mon, 17 Jun 2024 17:37:47 -0700 (PDT) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-6fb5afab833sm1686856a34.10.2024.06.17.17.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 17:37:46 -0700 (PDT) From: Sam Protsenko To: =?UTF-8?q?=C5=81ukasz=20Stelmach?= , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Olivia Mackall , Herbert Xu , Alim Akhtar , linux-samsung-soc@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] hwrng: exynos: Add SMC based TRNG operation Date: Mon, 17 Jun 2024 19:37:41 -0500 Message-Id: <20240618003743.2975-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240618003743.2975-1-semen.protsenko@linaro.org> References: <20240618003743.2975-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On some Exynos chips like Exynos850 the access to Security Sub System (SSS) registers is protected with TrustZone, and therefore only possible from EL3 monitor software. The Linux kernel is running in EL1, so the only way for the driver to obtain TRNG data is via SMC calls to EL3 monitor. Implement such SMC operation and use it when QUIRK_SMC is set in the corresponding chip driver data. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- drivers/char/hw_random/exynos-trng.c | 130 ++++++++++++++++++++++++--- 1 file changed, 120 insertions(+), 10 deletions(-) diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/= exynos-trng.c index 4520a280134c..98b7a8ebb909 100644 --- a/drivers/char/hw_random/exynos-trng.c +++ b/drivers/char/hw_random/exynos-trng.c @@ -10,6 +10,7 @@ * Krzysztof Koz=C5=82owski */ =20 +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include =20 #define EXYNOS_TRNG_CLKDIV 0x0 =20 @@ -44,16 +46,40 @@ #define EXYNOS_TRNG_FIFO_LEN 8 #define EXYNOS_TRNG_CLOCK_RATE 500000 =20 +#define QUIRK_SMC BIT(0) + +#define EXYNOS_SMC_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, \ + func_num) + +/* SMC command for DTRNG access */ +#define SMC_CMD_RANDOM EXYNOS_SMC_CALL_VAL(0x1012) + +/* SMC_CMD_RANDOM: arguments */ +#define HWRNG_INIT 0x0 +#define HWRNG_EXIT 0x1 +#define HWRNG_GET_DATA 0x2 +#define HWRNG_RESUME 0x3 + +/* SMC_CMD_RANDOM: return values */ +#define HWRNG_RET_OK 0x0 +#define HWRNG_RET_RETRY_ERROR 0x2 + +#define HWRNG_MAX_TRIES 100 + struct exynos_trng_dev { struct device *dev; void __iomem *mem; struct clk *clk; /* operating clock */ struct clk *pclk; /* bus clock */ struct hwrng rng; + unsigned long quirks; }; =20 -static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max, - bool wait) +static int exynos_trng_do_read_reg(struct hwrng *rng, void *data, size_t m= ax, + bool wait) { struct exynos_trng_dev *trng =3D (struct exynos_trng_dev *)rng->priv; int val; @@ -70,7 +96,40 @@ static int exynos_trng_do_read(struct hwrng *rng, void *= data, size_t max, return max; } =20 -static int exynos_trng_init(struct hwrng *rng) +static int exynos_trng_do_read_smc(struct hwrng *rng, void *data, size_t m= ax, + bool wait) +{ + struct arm_smccc_res res; + u32 *buf =3D data; + unsigned int copied =3D 0; + int tries =3D 0; + + while (copied < max) { + arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_GET_DATA, 0, 0, 0, 0, 0, 0, + &res); + switch (res.a0) { + case HWRNG_RET_OK: + *buf++ =3D res.a2; + *buf++ =3D res.a3; + copied +=3D 8; + tries =3D 0; + break; + case HWRNG_RET_RETRY_ERROR: + if (!wait) + return copied; + if (++tries >=3D HWRNG_MAX_TRIES) + return copied; + cond_resched(); + break; + default: + return -EIO; + } + } + + return copied; +} + +static int exynos_trng_init_reg(struct hwrng *rng) { struct exynos_trng_dev *trng =3D (struct exynos_trng_dev *)rng->priv; unsigned long sss_rate; @@ -103,6 +162,17 @@ static int exynos_trng_init(struct hwrng *rng) return 0; } =20 +static int exynos_trng_init_smc(struct hwrng *rng) +{ + struct arm_smccc_res res; + + arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_INIT, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 !=3D HWRNG_RET_OK) + return -EIO; + + return 0; +} + static int exynos_trng_probe(struct platform_device *pdev) { struct exynos_trng_dev *trng; @@ -112,21 +182,29 @@ static int exynos_trng_probe(struct platform_device *= pdev) if (!trng) return ret; =20 + platform_set_drvdata(pdev, trng); + trng->dev =3D &pdev->dev; + + trng->quirks =3D (unsigned long)device_get_match_data(&pdev->dev); + trng->rng.name =3D devm_kstrdup(&pdev->dev, dev_name(&pdev->dev), GFP_KERNEL); if (!trng->rng.name) return ret; =20 - trng->rng.init =3D exynos_trng_init; - trng->rng.read =3D exynos_trng_do_read; trng->rng.priv =3D (unsigned long)trng; =20 - platform_set_drvdata(pdev, trng); - trng->dev =3D &pdev->dev; + if (trng->quirks & QUIRK_SMC) { + trng->rng.init =3D exynos_trng_init_smc; + trng->rng.read =3D exynos_trng_do_read_smc; + } else { + trng->rng.init =3D exynos_trng_init_reg; + trng->rng.read =3D exynos_trng_do_read_reg; =20 - trng->mem =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(trng->mem)) - return PTR_ERR(trng->mem); + trng->mem =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(trng->mem)) + return PTR_ERR(trng->mem); + } =20 pm_runtime_enable(&pdev->dev); ret =3D pm_runtime_resume_and_get(&pdev->dev); @@ -190,6 +268,13 @@ static void exynos_trng_remove(struct platform_device = *pdev) { struct exynos_trng_dev *trng =3D platform_get_drvdata(pdev); =20 + if (trng->quirks & QUIRK_SMC) { + struct arm_smccc_res res; + + arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_EXIT, 0, 0, 0, 0, 0, 0, + &res); + } + clk_disable_unprepare(trng->clk); clk_disable_unprepare(trng->pclk); =20 @@ -199,6 +284,16 @@ static void exynos_trng_remove(struct platform_device = *pdev) =20 static int exynos_trng_suspend(struct device *dev) { + struct exynos_trng_dev *trng =3D dev_get_drvdata(dev); + struct arm_smccc_res res; + + if (trng->quirks & QUIRK_SMC) { + arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_EXIT, 0, 0, 0, 0, 0, 0, + &res); + if (res.a0 !=3D HWRNG_RET_OK) + return -EIO; + } + pm_runtime_put_sync(dev); =20 return 0; @@ -206,6 +301,7 @@ static int exynos_trng_suspend(struct device *dev) =20 static int exynos_trng_resume(struct device *dev) { + struct exynos_trng_dev *trng =3D dev_get_drvdata(dev); int ret; =20 ret =3D pm_runtime_resume_and_get(dev); @@ -214,6 +310,20 @@ static int exynos_trng_resume(struct device *dev) return ret; } =20 + if (trng->quirks & QUIRK_SMC) { + struct arm_smccc_res res; + + arm_smccc_smc(SMC_CMD_RANDOM, HWRNG_RESUME, 0, 0, 0, 0, 0, 0, + &res); + if (res.a0 !=3D HWRNG_RET_OK) + return -EIO; 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charset="utf-8" Add Exynos850 compatible and its driver data. It's only possible to access TRNG block via SMC calls in Exynos850, so specify that fact using QUIRK_SMC in the driver data. Signed-off-by: Sam Protsenko --- drivers/char/hw_random/exynos-trng.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/= exynos-trng.c index 98b7a8ebb909..3368a08df9ce 100644 --- a/drivers/char/hw_random/exynos-trng.c +++ b/drivers/char/hw_random/exynos-trng.c @@ -333,6 +333,9 @@ static DEFINE_SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exy= nos_trng_suspend, static const struct of_device_id exynos_trng_dt_match[] =3D { { .compatible =3D "samsung,exynos5250-trng", + }, { + .compatible =3D "samsung,exynos850-trng", + .data =3D (void *)QUIRK_SMC, }, { }, }; --=20 2.39.2 From nobody Wed Dec 17 06:30:02 2025 Received: from mail-oo1-f43.google.com (mail-oo1-f43.google.com [209.85.161.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7C2B1CFA8 for ; Tue, 18 Jun 2024 00:37:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 17 Jun 2024 17:37:48 -0700 (PDT) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5bd5e19a4e7sm1320770eaf.20.2024.06.17.17.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 17:37:48 -0700 (PDT) From: Sam Protsenko To: =?UTF-8?q?=C5=81ukasz=20Stelmach?= , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Olivia Mackall , Herbert Xu , Alim Akhtar , linux-samsung-soc@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: exynos850: Enable TRNG Date: Mon, 17 Jun 2024 19:37:43 -0500 Message-Id: <20240618003743.2975-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240618003743.2975-1-semen.protsenko@linaro.org> References: <20240618003743.2975-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add True Random Number Generator (TRNG) node to Exynos850 SoC dtsi. Signed-off-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index 0706c8534ceb..f1c8b4613cbc 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -416,6 +416,14 @@ pinctrl_core: pinctrl@12070000 { interrupts =3D ; }; =20 + trng: rng@12081400 { + compatible =3D "samsung,exynos850-trng"; + reg =3D <0x12081400 0x100>; + clocks =3D <&cmu_core CLK_GOUT_SSS_ACLK>, + <&cmu_core CLK_GOUT_SSS_PCLK>; + clock-names =3D "secss", "pclk"; + }; + pinctrl_hsi: pinctrl@13430000 { compatible =3D "samsung,exynos850-pinctrl"; reg =3D <0x13430000 0x1000>; --=20 2.39.2