From nobody Thu Dec 18 05:07:31 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D534C1922D0; Mon, 17 Jun 2024 21:56:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718661388; cv=none; b=uVMMeMsubQ/1bMAEbB59ecB/tdhEOYsD6wB6z6CTJMzKYE22bmwA0X2SCU8TzjLLJ8qiy71wpo1zkPPW2jdFOkiRZvL3X9olXwldYP1bdNM4Z/lHbHShNGrXwzqwzUCDkxJq2Dti5Qi0KxRXKNHVkpz+3QaZEq1PkhJe2BWQdD0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718661388; c=relaxed/simple; bh=/Tf0+9ywBhA2xu+ay36C238U4Xe6QDQ8N9Bh//pwcvs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZsVawYCsOniw6FbkVbXkugjvbDAWvD5lOCjOChoCeC66Z4dCMYUM/MqKO6/nNz8TqNrqHHwRYX39cQhD8GVSiOkl/YlTfb23Ak6C33exbrtjXOCl1nvOFsLTU8iXe8UPodBK24MGP4Ne2lZgZDp53l9s/v3Vm+HqWiSZ0RJdR4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QV0bLGs7; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QV0bLGs7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1718661385; bh=/Tf0+9ywBhA2xu+ay36C238U4Xe6QDQ8N9Bh//pwcvs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QV0bLGs7qU2pkEZQLaP496J4V1YrlQbHD8hWAmNmhZ3GEkb4VXHglTeN2oCBpy1mu ydj29ucf2/hYmidGOuxRPSCfQ7NzbMjYAlEXqd+/zyd4FMxDx534cIfGAMVjTuJH8E mE50zko6BfRUTdmrSqe37skUuprD51mchRAXbCTfDxUwtqKl4BIe71oyoAeEmHUEP2 DUP99T1SzRgWoe5AHeTju+UGT146e4dOIy6XH+GQ3OjmxlkjarI5etGlmE7IFJ+RCE 8b1U+EI2vfIb7c1pd3pkCi/EbSoLXKTRt/JB3E5Tr8daLJ/63QVm2QYIS9eHx80fNh kE5BdmsKwXxKQ== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id B49313782167; Mon, 17 Jun 2024 21:56:24 +0000 (UTC) From: Cristian Ciocaltea Date: Tue, 18 Jun 2024 00:48:09 +0300 Subject: [PATCH 1/4] phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240618-rk3588-hdmiphy-clkprov-v1-1-80e4aa12177e@collabora.com> References: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> In-Reply-To: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14-dev-f7c49 Driver makes use of helpers from pm_runtime.h, but relies on the header file being implicitly included. Explicitly pull the header in to avoid potential build failures in some configurations. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea Reviewed-by: Heiko Stuebner --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 946c01210ac8..3bd9b62b23dc 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include --=20 2.45.2 From nobody Thu Dec 18 05:07:31 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE5181991BB; Mon, 17 Jun 2024 21:56:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718661389; cv=none; b=TbKTntFB8dgX1L2aGBE8Jz17ICVCYrMA/HKCaipTm5Ls1HIBROiWPnAeosAuDLa1hej2SBLPk66XVmCXjIIqoryJ6VX/EeUSb/zhwJ+T+u6Od718bOv+ooLBVkcU9EW1ye/hgh8VO8/nTZ6d+jGUEBpYGA26aF8gUHzIJjkf49g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718661389; c=relaxed/simple; bh=d56lcRS9votQ6p3L/XnDZhcIMYXkAPNI+mcNCM8luyo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZGw9VrSFRSu++6+mnbAuTqojf6ixSZQ0ohcPH+DPBkLuVhhwR0zYZ8VBdUV1gU3XR6jKlFQCo8pR+8wzZWfNMxW5Sem9c25wGdJly8puVRtxBLlUDy2ANPuOgK2Q8bd2iV1GM47HezoivcTF38WWeTAru87cuGGn1tLSczDWEDM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=j44IjBFW; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="j44IjBFW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1718661386; bh=d56lcRS9votQ6p3L/XnDZhcIMYXkAPNI+mcNCM8luyo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=j44IjBFW6DTUSrued99+CdSkmWIRLOOinXULQUn7u4R+JU/sa1XJR+xUyY3W6dwWD VZqjcvr7IFlC9OQpwSGZ5sRwrlMbqbfKSBAfdV9X9MRi7aEsrtLAPQEgq9GyGQvhHb Toil5v19Mt4hC+mBuPlWq0zg0EdiDDGWOhyFx3q2UxyqFkE37o1b6x6/hJC0K3/+Np Joi8XUCIbYTs/LiRA5IJTgl4eEtP/EP6uvv95ONsGU6RBuUcsBhnG3bE1FK5gPdRwZ ZKD0irEaslfqXEHIfdc0rw+8D+nomkbwWNcwrnZpNRyUzgegfHWBcsIZg/1Sin04zS rvJLjDGN+nVPg== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id E703E3782169; Mon, 17 Jun 2024 21:56:25 +0000 (UTC) From: Cristian Ciocaltea Date: Tue, 18 Jun 2024 00:48:10 +0300 Subject: [PATCH 2/4] phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core level Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240618-rk3588-hdmiphy-clkprov-v1-2-80e4aa12177e@collabora.com> References: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> In-Reply-To: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14-dev-f7c49 When a new PHY is created via [devm_]phy_create(), the runtime PM for it is not enabled unless the parent device (which creates the PHY) has its own runtime PM already enabled. Move the call to devm_pm_runtime_enable() before devm_phy_create() to enable runtime PM at PHY core level. With this change the ->power_on() and ->power_off() callbacks do not require explicit runtime PM management anymore, since the PHY core handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and phy_power_off() are invoked. Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and pm_runtime_put() helpers. Signed-off-by: Cristian Ciocaltea Reviewed-by: Heiko Stuebner --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 24 ++++++-------------= ---- 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 3bd9b62b23dc..72de287282eb 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -860,7 +860,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hd= ptx_phy *hdptx, static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); - int ret, bus_width =3D phy_get_bus_width(hdptx->phy); + int bus_width =3D phy_get_bus_width(hdptx->phy); /* * FIXME: Temporary workaround to pass pixel_clk_rate * from the HDMI bridge driver until phy_configure_opts_hdmi @@ -871,17 +871,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) dev_dbg(hdptx->dev, "%s bus_width=3D%x rate=3D%u\n", __func__, bus_width, rate); =20 - ret =3D pm_runtime_resume_and_get(hdptx->dev); - if (ret) { - dev_err(hdptx->dev, "Failed to resume phy: %d\n", ret); - return ret; - } - - ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx, rate); - if (ret) - pm_runtime_put(hdptx->dev); - - return ret; + return rk_hdptx_ropll_tmds_mode_config(hdptx, rate); } =20 static int rk_hdptx_phy_power_off(struct phy *phy) @@ -894,8 +884,6 @@ static int rk_hdptx_phy_power_off(struct phy *phy) if (ret =3D=3D 0 && (val & HDPTX_O_PLL_LOCK_DONE)) rk_hdptx_phy_disable(hdptx); =20 - pm_runtime_put(hdptx->dev); - return ret; } =20 @@ -977,6 +965,10 @@ static int rk_hdptx_phy_probe(struct platform_device *= pdev) return dev_err_probe(dev, PTR_ERR(hdptx->grf), "Could not get GRF syscon\n"); =20 + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + hdptx->phy =3D devm_phy_create(dev, NULL, &rk_hdptx_phy_ops); if (IS_ERR(hdptx->phy)) return dev_err_probe(dev, PTR_ERR(hdptx->phy), @@ -986,10 +978,6 @@ static int rk_hdptx_phy_probe(struct platform_device *= pdev) phy_set_drvdata(hdptx->phy, hdptx); phy_set_bus_width(hdptx->phy, 8); =20 - ret =3D devm_pm_runtime_enable(dev); - if (ret) - return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); - phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); if (IS_ERR(phy_provider)) return dev_err_probe(dev, PTR_ERR(phy_provider), --=20 2.45.2 From nobody Thu Dec 18 05:07:31 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24155199250; Mon, 17 Jun 2024 21:56:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718661390; cv=none; b=ggiXsj1hkoPdH6NJG2wbCSsNWG2/FxwNorcGNq6fLY7DL/p9r7PclexCRCXSpQOFJYD8NZSdg2zaHoCfA2qndLOfk3tobfuz7IBkMq1ZxZ+c7oTrf52w0Xy1N+t7Dnwx/ao0m0sGhjFTgWS1x+NEKlfc/mnDpEB2Qd/gqEZflyE= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240618-rk3588-hdmiphy-clkprov-v1-3-80e4aa12177e@collabora.com> References: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> In-Reply-To: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14-dev-f7c49 The HDMI PHY can be used as a clock provider on RK3588 SoC, hence add the necessary '#clock-cells' property. Signed-off-by: Cristian Ciocaltea Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 3 += ++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-ph= y.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.ya= ml index 54e822c715f3..84fe59dbcf48 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml @@ -27,6 +27,9 @@ properties: - const: ref - const: apb =20 + "#clock-cells": + const: 0 + "#phy-cells": const: 0 =20 --=20 2.45.2 From nobody Thu Dec 18 05:07:31 2025 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7105B199E80; Mon, 17 Jun 2024 21:56:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718661392; cv=none; b=bforn0Qr3YC5kNr64qXYFMVyZJrXv6GIUkgVYnAWNFfWJcjTH3jSoEocP1QnJp+TFfvWmD2UvkvQhGRF/8Oi766ea43b/10n/nx4AEhpuhqv4QC8MwMf9e41an2AIn0ILK3MbqbX0MYOHNonwA+HwO+fkWueyCr52+0QMP9tSxw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718661392; c=relaxed/simple; bh=PJqnn1xMk/vyTcI7+A/mSlNl/s10hJkFyTUCDiHLlLQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ftze+aIgtXZ8A9V3ZrewyMzU7muOd5Uzwicz6o3P+3358KkTShSTOeNOzb48AJQE+SKiCqjZ79gfFiklC6s6G16yIaJbU6mcXejplzRNrhIlBjnI7xeVtovUhCECJM0p/J82GK3HI4ri+vAz4MwyZJaMQVQeCg0WZCkaOuQR97o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EoeSEaXH; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EoeSEaXH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1718661388; bh=PJqnn1xMk/vyTcI7+A/mSlNl/s10hJkFyTUCDiHLlLQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EoeSEaXHD95nl/EmSAh75MlfIbNTFm82Mb1sQmIwwLYLI4KBbYwt1Lpd0GvJ3omZ+ czgo+iO1EDSLl3wEYGVlkrvzwP4pHW4YPlgIvc3SBHVJ+7SMTvTsVO4bfS0kIfBrjy /eHVDWyHTB2/6wtHQUrH5CFedrSe8vog/CotNbGkg4UUH28nDenoh+n9gnw4wHjd7M 3u/FP+++Iqs+WQfQICWyMYvjDRAoX7i0B8CcQ+oWOAua7QQ0NVCa2hQ5pbu9FG3FVt Ynbcm+t2lxP8EatqDlcT0sb9l+DoKOBYTyFBGQC1vm9efLFde+BqI6pt2r0B62iq2o KBBc7inHUqzLw== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 5A56D378217B; Mon, 17 Jun 2024 21:56:28 +0000 (UTC) From: Cristian Ciocaltea Date: Tue, 18 Jun 2024 00:48:12 +0300 Subject: [PATCH 4/4] phy: phy-rockchip-samsung-hdptx: Add clock provider support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240618-rk3588-hdmiphy-clkprov-v1-4-80e4aa12177e@collabora.com> References: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> In-Reply-To: <20240618-rk3588-hdmiphy-clkprov-v1-0-80e4aa12177e@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14-dev-f7c49 The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC CRU. It provides more accurate clock rates required by VOP2 to improve existing support for display modes handling, which is known to be problematic when dealing with non-integer refresh rates, among others. It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 189 ++++++++++++++++++= +--- 1 file changed, 167 insertions(+), 22 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 72de287282eb..ad3fd4084377 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -8,6 +8,7 @@ */ #include #include +#include #include #include #include @@ -191,6 +192,8 @@ #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) =20 +#define HDMI20_MAX_RATE 600000000 + struct lcpll_config { u32 bit_rate; u8 lcvco_mode_en; @@ -273,6 +276,12 @@ struct rk_hdptx_phy { struct clk_bulk_data *clks; int nr_clks; struct reset_control_bulk_data rsts[RST_MAX]; + + /* clk provider */ + struct clk_hw hw; + unsigned long rate; + + atomic_t usage_count; }; =20 static const struct ropll_config ropll_tmds_cfg[] =3D { @@ -760,6 +769,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdp= tx_phy *hdptx, struct ropll_config rc =3D {0}; int i; =20 + hdptx->rate =3D rate * 100; + for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) if (rate =3D=3D ropll_tmds_cfg[i].bit_rate) { cfg =3D &ropll_tmds_cfg[i]; @@ -823,19 +834,6 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hd= ptx_phy *hdptx, static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, unsigned int rate) { - u32 val; - int ret; - - ret =3D regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); - if (ret) - return ret; - - if (!(val & HDPTX_O_PLL_LOCK_DONE)) { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); - if (ret) - return ret; - } - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); @@ -857,10 +855,66 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_= hdptx_phy *hdptx, return rk_hdptx_post_enable_lane(hdptx); } =20 +static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, + unsigned int rate) +{ + u32 status; + int ret; + + if (atomic_inc_return(&hdptx->usage_count) > 1) + return 0; + + ret =3D regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); + if (ret) + goto dec_usage; + + if (status & HDPTX_O_PLL_LOCK_DONE) + dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n"); + + if (rate) { + ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); + if (ret) + goto dec_usage; + } + + return 0; + +dec_usage: + atomic_dec(&hdptx->usage_count); + return ret; +} + +static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx) +{ + u32 status; + int ret; + + ret =3D atomic_dec_return(&hdptx->usage_count); + if (ret > 0) + return 0; + + if (ret < 0) { + dev_warn(hdptx->dev, "Usage count underflow!\n"); + ret =3D -EINVAL; + } else { + ret =3D regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); + if (!ret) { + if (status & HDPTX_O_PLL_LOCK_DONE) + rk_hdptx_phy_disable(hdptx); + return 0; + } + } + + atomic_inc(&hdptx->usage_count); + return ret; +} + static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); int bus_width =3D phy_get_bus_width(hdptx->phy); + int ret; + /* * FIXME: Temporary workaround to pass pixel_clk_rate * from the HDMI bridge driver until phy_configure_opts_hdmi @@ -871,20 +925,18 @@ static int rk_hdptx_phy_power_on(struct phy *phy) dev_dbg(hdptx->dev, "%s bus_width=3D%x rate=3D%u\n", __func__, bus_width, rate); =20 - return rk_hdptx_ropll_tmds_mode_config(hdptx, rate); + ret =3D rk_hdptx_phy_consumer_get(hdptx, rate); + if (!ret) + ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx, rate); + + return ret; } =20 static int rk_hdptx_phy_power_off(struct phy *phy) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); - u32 val; - int ret; - - ret =3D regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); - if (ret =3D=3D 0 && (val & HDPTX_O_PLL_LOCK_DONE)) - rk_hdptx_phy_disable(hdptx); =20 - return ret; + return rk_hdptx_phy_consumer_put(hdptx); } =20 static const struct phy_ops rk_hdptx_phy_ops =3D { @@ -893,6 +945,99 @@ static const struct phy_ops rk_hdptx_phy_ops =3D { .owner =3D THIS_MODULE, }; =20 +static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw) +{ + return container_of(hw, struct rk_hdptx_phy, hw); +} + +static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) +{ + struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + + return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100); +} + +static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) +{ + struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + + rk_hdptx_phy_consumer_put(hdptx); +} + +static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + + return hdptx->rate; +} + +static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, + unsigned long *parent_rate) +{ + u32 bit_rate =3D rate / 100; + int i; + + if (rate > HDMI20_MAX_RATE) + return rate; + + for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) + if (bit_rate =3D=3D ropll_tmds_cfg[i].bit_rate) + break; + + if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && + !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) + return -EINVAL; + + return rate; +} + +static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + + return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); +} + +static const struct clk_ops hdptx_phy_clk_ops =3D { + .prepare =3D rk_hdptx_phy_clk_prepare, + .unprepare =3D rk_hdptx_phy_clk_unprepare, + .recalc_rate =3D rk_hdptx_phy_clk_recalc_rate, + .round_rate =3D rk_hdptx_phy_clk_round_rate, + .set_rate =3D rk_hdptx_phy_clk_set_rate, +}; + +static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx) +{ + struct device *dev =3D hdptx->dev; + const char *name, *pname; + struct clk *refclk; + int ret, id; + + refclk =3D devm_clk_get(dev, "ref"); + if (IS_ERR(refclk)) + return dev_err_probe(dev, PTR_ERR(refclk), + "Failed to get ref clock\n"); + + id =3D of_alias_get_id(dev->of_node, "hdptxphy"); + name =3D id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0"; + pname =3D __clk_get_name(refclk); + + hdptx->hw.init =3D CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops, + CLK_GET_RATE_NOCACHE); + + ret =3D devm_clk_hw_register(dev, &hdptx->hw); + if (ret) + return dev_err_probe(dev, ret, "Failed to register clock\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw= ); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register clk provider\n"); + return 0; +} + static int rk_hdptx_phy_runtime_suspend(struct device *dev) { struct rk_hdptx_phy *hdptx =3D dev_get_drvdata(dev); @@ -987,7 +1132,7 @@ static int rk_hdptx_phy_probe(struct platform_device *= pdev) reset_control_deassert(hdptx->rsts[RST_CMN].rstc); reset_control_deassert(hdptx->rsts[RST_INIT].rstc); =20 - return 0; + return rk_hdptx_phy_clk_register(hdptx); } =20 static const struct dev_pm_ops rk_hdptx_phy_pm_ops =3D { --=20 2.45.2