From nobody Thu Feb 12 05:11:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2A78E194ADD for ; Mon, 17 Jun 2024 11:18:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718623135; cv=none; b=Es5gzlcoYISkq96VsX4ksqlIkuIemLSnAw5hig8tiL3O5aG6sqEXv78/qbWZFD0rtwadlB8UEGzStflOu7TfygH1ccrHpP1Jvbbr4+d4p9KjUUkT3sh663YyLsE45T68+kvSA9kLb8DKkf4YMdJ8LtIf3JTOviwSALTAf3K+CPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718623135; c=relaxed/simple; bh=XW0ey+7Xr49sNv7VbTaZiBIsgkjNPz9CoFlLYmIURkU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oxonyZE679mYY88Sljspq/v9ssVskwHN5jzWVeEgfMAkDQQViq3lmZWJT9yclfMIIQ9GevcGz1FaRdnZvF86oG3U1pzSW0KL5wqZHZs3ddc37+sA+F79kD/D0Qdc6nSrKKoUy1U1WljNBKKQhy34t1fQRvE7qK3HYWzb1+2E8qY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 455DE1516; Mon, 17 Jun 2024 04:19:17 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8BA913F6A8; Mon, 17 Jun 2024 04:18:51 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: alexandru.elisei@arm.com, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, mark.rutland@arm.com, maz@kernel.org, tglx@linutronix.de, will@kernel.org Subject: [PATCH v2 2/5] irqchip/gic-common: Remove sync_access callback Date: Mon, 17 Jun 2024 12:18:38 +0100 Message-Id: <20240617111841.2529370-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240617111841.2529370-1-mark.rutland@arm.com> References: <20240617111841.2529370-1-mark.rutland@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The gic_configure_irq(), gic_dist_config(), and gic_cpu_config() functions each take an optional "sync_access" callback, but in almost all cases this is not used. The only user is the GICv3 driver's gic_cpu_init() function, which uses gic_redist_wait_for_rwp() as the "sync_access" callback for gic_cpu_config(). It would be simpler and clearer to remove the callback and have the GICv3 driver call gic_redist_wait_for_rwp() explicitly after gic_cpu_config(). Remove the "sync_access" callback, and call gic_redist_wait_for_rwp() explicitly in the GICv3 driver. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Alexandru Elisei Cc: Catalin Marinas Cc: Marc Zyngier Cc: Thomas Gleixner Cc: Will Deacon Reviewed-by: Marc Zyngier Tested-by: Marc Zyngier --- drivers/irqchip/irq-gic-common.c | 16 +++------------- drivers/irqchip/irq-gic-common.h | 7 +++---- drivers/irqchip/irq-gic-v3.c | 7 ++++--- drivers/irqchip/irq-gic.c | 6 +++--- drivers/irqchip/irq-hip04.c | 6 +++--- 5 files changed, 16 insertions(+), 26 deletions(-) diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-com= mon.c index afd6a1841715a..4ed17620dc4d7 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -45,7 +45,7 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *= quirks, } =20 int gic_configure_irq(unsigned int irq, unsigned int type, - void __iomem *base, void (*sync_access)(void)) + void __iomem *base) { u32 confmask =3D 0x2 << ((irq % 16) * 2); u32 confoff =3D (irq / 16) * 4; @@ -84,14 +84,10 @@ int gic_configure_irq(unsigned int irq, unsigned int ty= pe, =20 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); =20 - if (sync_access) - sync_access(); - return ret; } =20 -void gic_dist_config(void __iomem *base, int gic_irqs, - void (*sync_access)(void)) +void gic_dist_config(void __iomem *base, int gic_irqs) { unsigned int i; =20 @@ -118,12 +114,9 @@ void gic_dist_config(void __iomem *base, int gic_irqs, writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ENABLE_CLEAR + i / 8); } - - if (sync_access) - sync_access(); } =20 -void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void)) +void gic_cpu_config(void __iomem *base, int nr) { int i; =20 @@ -144,7 +137,4 @@ void gic_cpu_config(void __iomem *base, int nr, void (*= sync_access)(void)) for (i =3D 0; i < nr; i +=3D 4) writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i * 4 / 4); - - if (sync_access) - sync_access(); } diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-com= mon.h index f407cce9ecaaa..c230175dd584c 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -20,10 +20,9 @@ struct gic_quirk { }; =20 int gic_configure_irq(unsigned int irq, unsigned int type, - void __iomem *base, void (*sync_access)(void)); -void gic_dist_config(void __iomem *base, int gic_irqs, - void (*sync_access)(void)); -void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void)); + void __iomem *base); +void gic_dist_config(void __iomem *base, int gic_irqs); +void gic_cpu_config(void __iomem *base, int nr); void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, void *data); void gic_enable_of_quirks(const struct device_node *np, diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 6fb276504bcc8..d95dda2383fb5 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -670,7 +670,7 @@ static int gic_set_type(struct irq_data *d, unsigned in= t type) =20 offset =3D convert_offset_index(d, GICD_ICFGR, &index); =20 - ret =3D gic_configure_irq(index, type, base + offset, NULL); + ret =3D gic_configure_irq(index, type, base + offset); if (ret && (range =3D=3D PPI_RANGE || range =3D=3D EPPI_RANGE)) { /* Misconfigured PPIs are usually not fatal */ pr_warn("GIC: PPI INTID%ld is secure or misconfigured\n", irq); @@ -940,7 +940,7 @@ static void __init gic_dist_init(void) writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); =20 /* Now do the common stuff */ - gic_dist_config(base, GIC_LINE_NR, NULL); + gic_dist_config(base, GIC_LINE_NR); =20 val =3D GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { @@ -1282,7 +1282,8 @@ static void gic_cpu_init(void) for (i =3D 0; i < gic_data.ppi_nr + SGI_NR; i +=3D 32) writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); =20 - gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR, gic_redist_wait_for_rwp); + gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR); + gic_redist_wait_for_rwp(); =20 /* initialise system registers */ gic_cpu_sys_reg_init(); diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 98aa383e39db1..87255bde960fc 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -303,7 +303,7 @@ static int gic_set_type(struct irq_data *d, unsigned in= t type) type !=3D IRQ_TYPE_EDGE_RISING) return -EINVAL; =20 - ret =3D gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); + ret =3D gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG); if (ret && gicirq < 32) { /* Misconfigured PPIs are usually not fatal */ pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16); @@ -479,7 +479,7 @@ static void gic_dist_init(struct gic_chip_data *gic) for (i =3D 32; i < gic_irqs; i +=3D 4) writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); =20 - gic_dist_config(base, gic_irqs, NULL); + gic_dist_config(base, gic_irqs); =20 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); } @@ -516,7 +516,7 @@ static int gic_cpu_init(struct gic_chip_data *gic) gic_cpu_map[i] &=3D ~cpu_mask; } =20 - gic_cpu_config(dist_base, 32, NULL); + gic_cpu_config(dist_base, 32); =20 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); gic_cpu_if_up(gic); diff --git a/drivers/irqchip/irq-hip04.c b/drivers/irqchip/irq-hip04.c index 46161f6ff289d..5285150fd9096 100644 --- a/drivers/irqchip/irq-hip04.c +++ b/drivers/irqchip/irq-hip04.c @@ -130,7 +130,7 @@ static int hip04_irq_set_type(struct irq_data *d, unsig= ned int type) =20 raw_spin_lock(&irq_controller_lock); =20 - ret =3D gic_configure_irq(irq, type, base + GIC_DIST_CONFIG, NULL); + ret =3D gic_configure_irq(irq, type, base + GIC_DIST_CONFIG); if (ret && irq < 32) { /* Misconfigured PPIs are usually not fatal */ pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16); @@ -260,7 +260,7 @@ static void __init hip04_irq_dist_init(struct hip04_irq= _data *intc) for (i =3D 32; i < nr_irqs; i +=3D 2) writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); =20 - gic_dist_config(base, nr_irqs, NULL); + gic_dist_config(base, nr_irqs); =20 writel_relaxed(1, base + GIC_DIST_CTRL); } @@ -287,7 +287,7 @@ static void hip04_irq_cpu_init(struct hip04_irq_data *i= ntc) if (i !=3D cpu) hip04_cpu_map[i] &=3D ~cpu_mask; =20 - gic_cpu_config(dist_base, 32, NULL); + gic_cpu_config(dist_base, 32); =20 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); writel_relaxed(1, base + GIC_CPU_CTRL); --=20 2.30.2