From nobody Thu Feb 12 05:12:10 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39176181BBB for ; Mon, 17 Jun 2024 10:53:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718621629; cv=none; b=tXg9q52SiQBs66X5NMqWDVZ/exVgubVK4iWXKmXNeXahDP3ibwxJQXjxl/g8nRfbRDX2VBKyjnAWLEWHPJ5TK+6qRreZrPkgBbuPvAK8ymrMXMGcR6ZOclPfTCNWt5xpGdTW9oLWszhr9ujfadozH+P10wiHnwwxXEcE5hd/tBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718621629; c=relaxed/simple; bh=q72P490XSvjhQqt0/MTc0V24jaUtaSI3r2eQjIKRVo0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=odtVQyNbg+rBHi3/2e9mYpEAMerKFIke4ppJhCOd5FSB7GgTdIJr/Moyq82pJFHaL828VCYJBkqj3T4Gy3tIXhYr3l8SVI2CXjFZoOTfq9fTNxL11UlfzWRNieHukb+JSHmU+3fDC6k2Mc4M47tBTFGPbLvA7snAw5/6d9mozxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=oLukaRq5; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oLukaRq5" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45HArHQn061384; Mon, 17 Jun 2024 05:53:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718621597; bh=o5wG54oHAcp8t7FU4H5j+XKlq4EeECM+G2XW18HGS7I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oLukaRq5biyg7P4HX2HB7FiGUCqurut10NjKY4lvdOqIetlKBYXSxol0qme/wrxHx nBiObPZ0sqFepa2wJui5/KyobBEiCS40mdaHlmU+e0H4BssD/G735r14IhguBz9Num SD0lqfTBIR0BqIn1TBe7S7k9cSW5Jmyi4QpgIql4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45HArHBW032604 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 17 Jun 2024 05:53:17 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 17 Jun 2024 05:53:17 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 17 Jun 2024 05:53:17 -0500 Received: from localhost (uda0496377.dhcp.ti.com [172.24.227.31]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45HArGEA015838; Mon, 17 Jun 2024 05:53:17 -0500 From: Aradhya Bhatia To: Dmitry Baryshkov , Tomi Valkeinen , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Jyri Sarha , Thomas Zimmermann , David Airlie , Daniel Vetter CC: DRI Development List , Linux Kernel List , Dominik Haller , Sam Ravnborg , Thierry Reding , Kieran Bingham , Nishanth Menon , Vignesh Raghavendra , Praneeth Bajjuri , Udit Kumar , Devarsh Thakkar , Jayesh Choudhary , Jai Luthra , Aradhya Bhatia Subject: [PATCH v3 03/10] drm/bridge: cdns-dsi: Fix the link and phy init order Date: Mon, 17 Jun 2024 16:23:04 +0530 Message-ID: <20240617105311.1587489-4-a-bhatia1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617105311.1587489-1-a-bhatia1@ti.com> References: <20240617105311.1587489-1-a-bhatia1@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The order of init of DSI link and DSI phy is wrong. The DSI link needs to be configured before the DSI phy is getting configured. Otherwise, the D-Phy is unable to lock in on the incoming PLL Reference clock[0]. Fix the order of inits. [0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E SoC TRM TRM Link: http://www.ti.com/lit/pdf/spruil1 Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework") Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/d= rm/bridge/cadence/cdns-dsi-core.c index 42565e253b2d..371a3453970c 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -775,8 +775,8 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *b= ridge) =20 WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false)); =20 - cdns_dsi_hs_init(dsi); cdns_dsi_init_link(dsi); + cdns_dsi_hs_init(dsi); =20 writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa), dsi->regs + VID_HSIZE1); --=20 2.34.1