From nobody Thu Dec 18 15:06:43 2025 Received: from mail-oa1-f42.google.com (mail-oa1-f42.google.com [209.85.160.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 432C91C6881 for ; Mon, 17 Jun 2024 13:50:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718632223; cv=none; b=I9Fx/nBh1eRAYE+NzQL209iUl7XI+CDuTkBCuYbE6RqOCFf5wmeCCp6mZIxSMMcO5rH6YtPzup+gJ+VuNXcyl/sNFcv4sNBIWByQU1qCtizTtvO3wUCM+9qvYGkToAtiWedIbKOt4i1Q0FE67rwL/+fnIq5OCB+p+yASxqvQHtQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718632223; c=relaxed/simple; bh=iX/O4thw4u8jxmjQXCGvy7+RStVKhiFFxFMRaqR3WK0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u58Xj5VtkRjJ1dHzeTIVMBa4vBLVd5Y2zqI1zBRCT7cf4niEdHL/SJm95XRDspizxmGcZZJTx2wnyzsf6PNoKgJlE5LR9a3GI3IiJPtDuFPP+ln7af1gxu2CvRUMlyaUvrER8dWeftRaJWSRYVoUzfFeGYu8jfQtRKPLbFILaYU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=yVl15yCM; arc=none smtp.client-ip=209.85.160.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="yVl15yCM" Received: by mail-oa1-f42.google.com with SMTP id 586e51a60fabf-254e42df409so2771069fac.0 for ; Mon, 17 Jun 2024 06:50:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1718632221; x=1719237021; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pghOqqoUrgqxulm8czqYmTg2ejQ+jCMFTS9OcdLe8gI=; b=yVl15yCMx8Rq/yn6JRv0Mo+5clGun24H2X3e8y0JsohuP7YFeLbjUgh9HBDNbFDlj5 4gDa36qo8A9rV0LK6MXn4bT4zitpJcoA3L5KD3A5ea5uHcaiiaOM52Yz3+GUKe4YPGoN y26OSFMb/+ZFJDSX8cvcy10F6Mm8S4AE7u8X46xtjsfgN1PU6ICW9BqanAZbmrWZI3vS 0AGwqBkdrjzF9pchQ4ar3F9+QM/M3FkigDqdQuM2xmRNWX7vMvgoWFMtemzlbpGfGGJY XGwFcfqW/zvgbajkMK4ioRFBQ4DWDK29gKr9RMZd4jKTJDPwme9dGXMU4R7HIDqWFHK6 EhMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718632221; x=1719237021; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pghOqqoUrgqxulm8czqYmTg2ejQ+jCMFTS9OcdLe8gI=; b=S9WW9Lm1yNFuQw4rDzIUd0tSQ6hKJtTWGTQNQXw/hiohEdzMN7iNL6ASQLOD1xTQ46 XnUE7iJ4ejlL0FBTqpKpDTCFT0QJn/FB2RGInF2v+AuP/nZsFINKxNkSXjM5G8ND6Jg9 M4VaRTE+aAKFc6loRcxwMagm9ghYCYaLjRlFAGznAkxNF8hPDm2hpL5GyHcYvK7qh2rH FQwqOuQivpE1VeuV+PtgQHJp5QNDsquFPgRanBCA9K3h+OjcZjXfAFMd7ylOMnVMpojg vQUzeW64Y5JEK4jrbYHyR+Y9AjglW64s/mfHjKZss1btcz9QQK4KSz5SYAuy2/GdTIC9 GMrg== X-Forwarded-Encrypted: i=1; AJvYcCUsKVRFKdM7FJydK4y20pGM9eOJ2H7rxikYmHe1jqJ4gkrKc4Hdu1xzYJI54FmhBiCsrvmLELqBzB1RgFAtdxFghhnVmGHHM5gXRspk X-Gm-Message-State: AOJu0YyaT+BIKioCPa8MUQcjtMG6G33ec1cv3XIPfZXH515Z9SAqeURI F7uo9MzPMosXOpSM9Qqy3GNfSLWcXwSeTGv1YQqInMAnd1I1aapfmpWTuxoiX0c= X-Google-Smtp-Source: AGHT+IHPRFjhQJMl5A95ZWgXFtrQQKsMmXYW6RVDp9V1gMjS9xuHYY98wxPGrZXsyYueeiP6Xe3wcg== X-Received: by 2002:a05:6871:5c9:b0:254:94a4:35d2 with SMTP id 586e51a60fabf-25842b7af81mr10339918fac.45.1718632221358; Mon, 17 Jun 2024 06:50:21 -0700 (PDT) Received: from megalith.oryx-coho.ts.net (d24-150-219-207.home.cgocable.net. [24.150.219.207]) by smtp.gmail.com with ESMTPSA id af79cd13be357-798aaecc004sm432892285a.31.2024.06.17.06.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 06:50:21 -0700 (PDT) From: Trevor Gamblin Date: Mon, 17 Jun 2024 09:49:57 -0400 Subject: [PATCH v3 17/41] iio: adc: sc27xx_adc: make use of regmap_clear_bits(), regmap_set_bits() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240617-review-v3-17-88d1338c4cca@baylibre.com> References: <20240617-review-v3-0-88d1338c4cca@baylibre.com> In-Reply-To: <20240617-review-v3-0-88d1338c4cca@baylibre.com> To: Jonathan Cameron , Lars-Peter Clausen , Dmitry Rokosov , Michael Hennerich , Cosmin Tanislav , Chen-Yu Tsai , Hans de Goede , Ray Jui , Scott Branden , Broadcom internal kernel review list , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Saravanan Sekar , Orson Zhai , Baolin Wang , Chunyan Zhang , Maxime Coquelin , Alexandre Torgue , =?utf-8?q?Nuno_S=C3=A1?= , Linus Walleij , Jean-Baptiste Maneyrol , Crt Mori Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Trevor Gamblin X-Mailer: b4 0.13.0 Instead of using regmap_update_bits() and passing the mask twice, use regmap_set_bits(). Instead of using regmap_update_bits() and passing val =3D 0, use regmap_clear_bits(). Suggested-by: Uwe Kleine-K=C3=B6nig Reviewed-by: Baolin Wang Signed-off-by: Trevor Gamblin --- drivers/iio/adc/sc27xx_adc.c | 41 ++++++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index b4a2e057d80f..2535c2c3e60b 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -508,13 +508,13 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *da= ta, int channel, } } =20 - ret =3D regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, - SC27XX_ADC_EN, SC27XX_ADC_EN); + ret =3D regmap_set_bits(data->regmap, data->base + SC27XX_ADC_CTL, + SC27XX_ADC_EN); if (ret) goto regulator_restore; =20 - ret =3D regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, - SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR); + ret =3D regmap_set_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, + SC27XX_ADC_IRQ_CLR); if (ret) goto disable_adc; =20 @@ -537,8 +537,8 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *data= , int channel, if (ret) goto disable_adc; =20 - ret =3D regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, - SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN); + ret =3D regmap_set_bits(data->regmap, data->base + SC27XX_ADC_CTL, + SC27XX_ADC_CHN_RUN); if (ret) goto disable_adc; =20 @@ -559,8 +559,8 @@ static int sc27xx_adc_read(struct sc27xx_adc_data *data= , int channel, value &=3D SC27XX_ADC_DATA_MASK; =20 disable_adc: - regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, - SC27XX_ADC_EN, 0); + regmap_clear_bits(data->regmap, data->base + SC27XX_ADC_CTL, + SC27XX_ADC_EN); regulator_restore: if ((data->var_data->set_volref) && (channel =3D=3D 30 || channel =3D=3D = 31)) { ret_volref =3D regulator_set_voltage(data->volref, @@ -765,15 +765,14 @@ static int sc27xx_adc_enable(struct sc27xx_adc_data *= data) { int ret; =20 - ret =3D regmap_update_bits(data->regmap, data->var_data->module_en, - SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN); + ret =3D regmap_set_bits(data->regmap, data->var_data->module_en, + SC27XX_MODULE_ADC_EN); if (ret) return ret; =20 /* Enable ADC work clock and controller clock */ - ret =3D regmap_update_bits(data->regmap, data->var_data->clk_en, - SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, - SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); + ret =3D regmap_set_bits(data->regmap, data->var_data->clk_en, + SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); if (ret) goto disable_adc; =20 @@ -789,11 +788,11 @@ static int sc27xx_adc_enable(struct sc27xx_adc_data *= data) return 0; =20 disable_clk: - regmap_update_bits(data->regmap, data->var_data->clk_en, - SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); + regmap_clear_bits(data->regmap, data->var_data->clk_en, + SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); disable_adc: - regmap_update_bits(data->regmap, data->var_data->module_en, - SC27XX_MODULE_ADC_EN, 0); + regmap_clear_bits(data->regmap, data->var_data->module_en, + SC27XX_MODULE_ADC_EN); =20 return ret; } @@ -803,11 +802,11 @@ static void sc27xx_adc_disable(void *_data) struct sc27xx_adc_data *data =3D _data; =20 /* Disable ADC work clock and controller clock */ - regmap_update_bits(data->regmap, data->var_data->clk_en, - SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0); + regmap_clear_bits(data->regmap, data->var_data->clk_en, + SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN); =20 - regmap_update_bits(data->regmap, data->var_data->module_en, - SC27XX_MODULE_ADC_EN, 0); + regmap_clear_bits(data->regmap, data->var_data->module_en, + SC27XX_MODULE_ADC_EN); } =20 static const struct sc27xx_adc_variant_data sc2731_data =3D { --=20 2.45.2