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Acked-by: Conor Dooley Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 6d185d09cb6a..5c9014087c17 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1275,6 +1275,12 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 =20 + - description: i.MX95 based Boards + items: + - enum: + - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - const: fsl,imx95 + - description: i.MXRT1050 based Boards items: - enum: --=20 2.37.1 From nobody Fri Dec 19 16:05:44 2025 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2088.outbound.protection.outlook.com [40.107.6.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09AD7433B3; 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This patch is to add a minimal dtsi, with cpu cores, scmi, gic, uart, mu, sdhc, lpi2c added. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95-clock.h | 187 +++++ arch/arm64/boot/dts/freescale/imx95-pinfunc.h | 865 ++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx95-power.h | 47 ++ arch/arm64/boot/dts/freescale/imx95.dtsi | 1042 +++++++++++++++++++++= ++++ 4 files changed, 2141 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/= dts/freescale/imx95-clock.h new file mode 100644 index 000000000000..e1f91203e794 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-clock.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024 NXP + */ + +#ifndef __CLOCK_IMX95_H +#define __CLOCK_IMX95_H + +/* The index should match i.MX95 SCMI Firmware */ +#define IMX95_CLK_32K 1 +#define IMX95_CLK_24M 2 +#define IMX95_CLK_FRO 3 +#define IMX95_CLK_SYSPLL1_VCO 4 +#define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX95_CLK_SYSPLL1_PFD0 6 +#define IMX95_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX95_CLK_SYSPLL1_PFD1 9 +#define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX95_CLK_SYSPLL1_PFD2 12 +#define IMX95_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX95_CLK_AUDIOPLL1_VCO 14 +#define IMX95_CLK_AUDIOPLL1 15 +#define IMX95_CLK_AUDIOPLL2_VCO 16 +#define IMX95_CLK_AUDIOPLL2 17 +#define IMX95_CLK_VIDEOPLL1_VCO 18 +#define IMX95_CLK_VIDEOPLL1 19 +#define IMX95_CLK_RESERVED20 20 +#define IMX95_CLK_RESERVED21 21 +#define IMX95_CLK_RESERVED22 22 +#define IMX95_CLK_RESERVED23 23 +#define IMX95_CLK_ARMPLL_VCO 24 +#define IMX95_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX95_CLK_ARMPLL_PFD0 26 +#define IMX95_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX95_CLK_ARMPLL_PFD1 28 +#define IMX95_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX95_CLK_ARMPLL_PFD2 30 +#define IMX95_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX95_CLK_ARMPLL_PFD3 32 +#define IMX95_CLK_DRAMPLL_VCO 33 +#define IMX95_CLK_DRAMPLL 34 +#define IMX95_CLK_HSIOPLL_VCO 35 +#define IMX95_CLK_HSIOPLL 36 +#define IMX95_CLK_LDBPLL_VCO 37 +#define IMX95_CLK_LDBPLL 38 +#define IMX95_CLK_EXT1 39 +#define IMX95_CLK_EXT2 40 + +#define IMX95_CCM_NUM_CLK_SRC 41 + +#define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0) +#define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1) +#define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2) +#define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3) +#define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4) +#define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5) +#define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6) +#define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7) +#define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8) +#define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9) +#define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10) +#define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11) +#define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12) +#define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13) +#define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14) +#define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15) +#define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16) +#define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17) +#define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18) +#define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19) +#define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20) +#define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21) +#define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22) +#define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23) +#define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24) +#define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25) +#define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26) +#define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27) +#define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28) +#define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29) +#define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30) +#define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31) +#define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32) +#define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33) +#define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34) +#define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35) +#define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36) +#define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37) +#define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38) +#define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39) +#define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40) +#define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41) +#define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42) +#define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43) +#define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44) +#define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45) +#define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46) +#define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47) +#define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48) +#define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49) +#define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50) +#define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51) +#define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52) +#define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53) +#define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54) +#define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55) +#define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56) +#define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57) +#define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58) +#define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59) +#define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60) +#define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61) +#define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62) +#define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63) +#define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64) +#define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65) +#define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66) +#define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67) +#define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68) +#define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69) +#define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70) +#define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71) +#define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72) +#define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73) +#define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74) +#define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75) +#define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76) +#define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77) +#define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78) +#define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79) +#define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80) +#define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81) +#define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82) +#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83) +#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84) +#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85) +#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86) +#define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87) +#define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88) +#define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89) +#define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90) +#define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91) +#define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92) +#define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93) +#define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94) +#define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95) +#define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96) +#define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97) +#define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98) +#define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99) +#define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100) +#define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101) +#define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102) +#define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103) +#define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104) +#define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105) +#define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106) +#define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107) +#define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108) +#define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109) +#define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110) +#define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111) +#define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112) +#define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113) +#define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114) +#define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115) +#define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116) +#define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117) +#define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118) +#define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119) +#define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120) +#define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121) +#define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122) +#define IMX95_CLK_SEL_EXT (IMX95_CCM_NUM_CLK_SRC + 123 + = 0) +#define IMX95_CLK_SEL_A55C0 (IMX95_CCM_NUM_CLK_SRC + 123 + = 1) +#define IMX95_CLK_SEL_A55C1 (IMX95_CCM_NUM_CLK_SRC + 123 + = 2) +#define IMX95_CLK_SEL_A55C2 (IMX95_CCM_NUM_CLK_SRC + 123 + = 3) +#define IMX95_CLK_SEL_A55C3 (IMX95_CCM_NUM_CLK_SRC + 123 + = 4) +#define IMX95_CLK_SEL_A55C4 (IMX95_CCM_NUM_CLK_SRC + 123 + = 5) +#define IMX95_CLK_SEL_A55C5 (IMX95_CCM_NUM_CLK_SRC + 123 + = 6) +#define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + = 7) +#define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + = 8) +#define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + = 9) + +#endif /* __CLOCK_IMX95_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-pinfunc.h b/arch/arm64/boo= t/dts/freescale/imx95-pinfunc.h new file mode 100644 index 000000000000..9f614eea7c86 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-pinfunc.h @@ -0,0 +1,865 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DTS_IMX95_PINFUNC_H +#define __DTS_IMX95_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x00= 00 0x0204 0x0610 0x00 0x00 +#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x00= 00 0x0204 0x0000 0x01 0x00 +#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x00= 00 0x0204 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TDI__CAN2_TX 0x00= 00 0x0204 0x0000 0x03 0x00 +#define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x00= 00 0x0204 0x0000 0x04 0x00 +#define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x00= 00 0x0204 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TDI__LPUART5_RX 0x00= 00 0x0204 0x0570 0x06 0x00 + +#define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x00= 04 0x0208 0x0614 0x00 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x00= 04 0x0208 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x00= 04 0x0208 0x0000 0x04 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29 0x00= 04 0x0208 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x00= 04 0x0208 0x0000 0x06 0x00 + +#define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x00= 08 0x020C 0x060C 0x00 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX 0x00= 08 0x020C 0x044C 0x02 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30 0x00= 08 0x020C 0x0460 0x04 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30 0x00= 08 0x020C 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x00= 08 0x020C 0x056C 0x06 0x00 + +#define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x00= 0C 0x0210 0x0000 0x00 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x00= 0C 0x0210 0x0000 0x01 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM 0x00= 0C 0x0210 0x0000 0x02 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x00= 0C 0x0210 0x0444 0x03 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31 0x00= 0C 0x0210 0x0464 0x04 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31 0x00= 0C 0x0210 0x0000 0x05 0x00 +#define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x00= 0C 0x0210 0x0574 0x06 0x00 + +#define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x00= 10 0x0214 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x00= 10 0x0214 0x0504 0x11 0x00 +#define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0 0x00= 10 0x0214 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO00__LPUART5_TX 0x00= 10 0x0214 0x0574 0x05 0x01 +#define IMX95_PAD_GPIO_IO00__LPI2C5_SDA 0x00= 10 0x0214 0x0514 0x16 0x00 +#define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0 0x00= 10 0x0214 0x0468 0x07 0x00 + +#define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1 0x00= 14 0x0218 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x00= 14 0x0218 0x0500 0x11 0x00 +#define IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x00= 14 0x0218 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO01__LPUART5_RX 0x00= 14 0x0218 0x0570 0x05 0x01 +#define IMX95_PAD_GPIO_IO01__LPI2C5_SCL 0x00= 14 0x0218 0x0510 0x16 0x00 +#define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1 0x00= 14 0x0218 0x046C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x00= 18 0x021C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO02__LPI2C4_SDA 0x00= 18 0x021C 0x050C 0x11 0x00 +#define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x00= 18 0x021C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x00= 18 0x021C 0x056C 0x05 0x01 +#define IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x00= 18 0x021C 0x051C 0x16 0x00 +#define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2 0x00= 18 0x021C 0x0470 0x07 0x00 + +#define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x00= 1C 0x0220 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO03__LPI2C4_SCL 0x00= 1C 0x0220 0x0508 0x11 0x00 +#define IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x00= 1C 0x0220 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x00= 1C 0x0220 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x00= 1C 0x0220 0x0518 0x16 0x00 +#define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3 0x00= 1C 0x0220 0x0474 0x07 0x00 + +#define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x00= 20 0x0224 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO04__TPM3_CH0 0x00= 20 0x0224 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x00= 20 0x0224 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO04__CAN4_TX 0x00= 20 0x0224 0x0000 0x03 0x00 +#define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 0x00= 20 0x0224 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO04__LPUART6_TX 0x00= 20 0x0224 0x0580 0x05 0x01 +#define IMX95_PAD_GPIO_IO04__LPI2C6_SDA 0x00= 20 0x0224 0x051C 0x16 0x01 +#define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4 0x00= 20 0x0224 0x0478 0x07 0x00 + +#define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5 0x00= 24 0x0228 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO05__TPM4_CH0 0x00= 24 0x0228 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x00= 24 0x0228 0x040C 0x02 0x01 +#define IMX95_PAD_GPIO_IO05__CAN4_RX 0x00= 24 0x0228 0x044C 0x03 0x01 +#define IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x00= 24 0x0228 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO05__LPUART6_RX 0x00= 24 0x0228 0x057C 0x05 0x01 +#define IMX95_PAD_GPIO_IO05__LPI2C6_SCL 0x00= 24 0x0228 0x0518 0x16 0x01 +#define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5 0x00= 24 0x0228 0x047C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x00= 28 0x022C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO06__TPM5_CH0 0x00= 28 0x022C 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x00= 28 0x022C 0x0410 0x02 0x01 +#define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x00= 28 0x022C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 0x00= 28 0x022C 0x0578 0x05 0x01 +#define IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x00= 28 0x022C 0x0524 0x16 0x00 +#define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6 0x00= 28 0x022C 0x0480 0x07 0x00 + +#define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x00= 2C 0x0230 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1 0x00= 2C 0x0230 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x00= 2C 0x0230 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x00= 2C 0x0230 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x00= 2C 0x0230 0x0520 0x16 0x00 +#define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7 0x00= 2C 0x0230 0x0484 0x07 0x00 + +#define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x00= 30 0x0234 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 0x00= 30 0x0234 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO08__TPM6_CH0 0x00= 30 0x0234 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO08__LPUART7_TX 0x00= 30 0x0234 0x0588 0x05 0x01 +#define IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x00= 30 0x0234 0x0524 0x16 0x01 +#define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8 0x00= 30 0x0234 0x0488 0x07 0x00 + +#define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x00= 34 0x0238 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x00= 34 0x0238 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK 0x00= 34 0x0238 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO09__LPUART7_RX 0x00= 34 0x0238 0x0584 0x05 0x01 +#define IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x00= 34 0x0238 0x0520 0x16 0x01 +#define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9 0x00= 34 0x0238 0x048C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x00= 38 0x023C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x00= 38 0x023C 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK 0x00= 38 0x023C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x00= 38 0x023C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x00= 38 0x023C 0x052C 0x16 0x00 +#define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10 0x00= 38 0x023C 0x0490 0x07 0x00 + +#define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x00= 3C 0x0240 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x00= 3C 0x0240 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK 0x00= 3C 0x0240 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x00= 3C 0x0240 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x00= 3C 0x0240 0x0528 0x16 0x00 +#define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11 0x00= 3C 0x0240 0x0494 0x07 0x00 + +#define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x00= 40 0x0244 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO12__TPM3_CH2 0x00= 40 0x0244 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x00= 40 0x0244 0x0414 0x02 0x00 +#define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12 0x00= 40 0x0244 0x0498 0x03 0x00 +#define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0 0x00= 40 0x0244 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO12__LPUART8_TX 0x00= 40 0x0244 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x00= 40 0x0244 0x052C 0x16 0x01 +#define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC 0x00= 40 0x0244 0x0590 0x07 0x00 + +#define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x00= 44 0x0248 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO13__TPM4_CH2 0x00= 44 0x0248 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x00= 44 0x0248 0x0418 0x02 0x00 +#define IMX95_PAD_GPIO_IO13__LPSPI8_SIN 0x00= 44 0x0248 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO13__LPUART8_RX 0x00= 44 0x0248 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x00= 44 0x0248 0x0528 0x16 0x01 +#define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13 0x00= 44 0x0248 0x049C 0x07 0x00 + +#define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x00= 48 0x024C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART3_TX 0x00= 48 0x024C 0x055C 0x01 0x01 +#define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT 0x00= 48 0x024C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x00= 48 0x024C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO14__LPUART4_TX 0x00= 48 0x024C 0x0568 0x06 0x01 +#define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14 0x00= 48 0x024C 0x04A0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15 0x00= 4C 0x0250 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART3_RX 0x00= 4C 0x0250 0x0558 0x01 0x01 +#define IMX95_PAD_GPIO_IO15__LPSPI8_SCK 0x00= 4C 0x0250 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x00= 4C 0x0250 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO15__LPUART4_RX 0x00= 4C 0x0250 0x0564 0x06 0x01 +#define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15 0x00= 4C 0x0250 0x04A4 0x07 0x00 + +#define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x00= 50 0x0254 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x00= 50 0x0254 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x00= 50 0x0254 0x0414 0x02 0x01 +#define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x00= 50 0x0254 0x0554 0x04 0x01 +#define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2 0x00= 50 0x0254 0x0538 0x05 0x01 +#define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B 0x00= 50 0x0254 0x0560 0x06 0x01 +#define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16 0x00= 50 0x0254 0x04A8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x00= 54 0x0258 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x00= 54 0x0258 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x00= 54 0x0258 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1 0x00= 54 0x0258 0x0534 0x05 0x01 +#define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B 0x00= 54 0x0258 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17 0x00= 54 0x0258 0x04AC 0x07 0x00 + +#define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x00= 58 0x025C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x00= 58 0x025C 0x058C 0x01 0x00 +#define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0 0x00= 58 0x025C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 0x00= 58 0x025C 0x0530 0x05 0x01 +#define IMX95_PAD_GPIO_IO18__TPM5_CH2 0x00= 58 0x025C 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18 0x00= 58 0x025C 0x04B0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x00= 5C 0x0260 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x00= 5C 0x0260 0x0590 0x01 0x01 +#define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x00= 5C 0x0260 0x0418 0x02 0x01 +#define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19 0x00= 5C 0x0260 0x04B4 0x03 0x00 +#define IMX95_PAD_GPIO_IO19__LPSPI5_SIN 0x00= 5C 0x0260 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x00= 5C 0x0260 0x0540 0x05 0x01 +#define IMX95_PAD_GPIO_IO19__TPM6_CH2 0x00= 5C 0x0260 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x00= 5C 0x0260 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x00= 60 0x0264 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x00= 60 0x0264 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x00= 60 0x0264 0x040C 0x02 0x02 +#define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT 0x00= 60 0x0264 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x00= 60 0x0264 0x0544 0x05 0x01 +#define IMX95_PAD_GPIO_IO20__TPM3_CH1 0x00= 60 0x0264 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20 0x00= 60 0x0264 0x04B8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x00= 64 0x0268 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x00= 64 0x0268 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x00= 64 0x0268 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21 0x00= 64 0x0268 0x04BC 0x03 0x00 +#define IMX95_PAD_GPIO_IO21__LPSPI5_SCK 0x00= 64 0x0268 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x00= 64 0x0268 0x053C 0x05 0x01 +#define IMX95_PAD_GPIO_IO21__TPM4_CH1 0x00= 64 0x0268 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK 0x00= 64 0x0268 0x058C 0x07 0x01 + +#define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x00= 68 0x026C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO22__USDHC3_CLK 0x00= 68 0x026C 0x05C8 0x01 0x00 +#define IMX95_PAD_GPIO_IO22__SPDIF_IN 0x00= 68 0x026C 0x0454 0x02 0x02 +#define IMX95_PAD_GPIO_IO22__CAN5_TX 0x00= 68 0x026C 0x0000 0x03 0x00 +#define IMX95_PAD_GPIO_IO22__TPM5_CH1 0x00= 68 0x026C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK 0x00= 68 0x026C 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x00= 68 0x026C 0x0514 0x16 0x01 +#define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22 0x00= 68 0x026C 0x04C0 0x07 0x00 + +#define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x00= 6C 0x0270 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO23__USDHC3_CMD 0x00= 6C 0x0270 0x05CC 0x01 0x00 +#define IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x00= 6C 0x0270 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO23__CAN5_RX 0x00= 6C 0x0270 0x0450 0x03 0x00 +#define IMX95_PAD_GPIO_IO23__TPM6_CH1 0x00= 6C 0x0270 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x00= 6C 0x0270 0x0510 0x16 0x01 +#define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23 0x00= 6C 0x0270 0x04C4 0x07 0x00 + +#define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x00= 70 0x0274 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO24__USDHC3_DATA0 0x00= 70 0x0274 0x05D0 0x01 0x00 +#define IMX95_PAD_GPIO_IO24__TPM3_CH3 0x00= 70 0x0274 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO 0x00= 70 0x0274 0x0000 0x05 0x00 +#define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1 0x00= 70 0x0274 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24 0x00= 70 0x0274 0x04C8 0x07 0x00 + +#define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x00= 74 0x0278 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO25__USDHC3_DATA1 0x00= 74 0x0278 0x05D4 0x01 0x00 +#define IMX95_PAD_GPIO_IO25__CAN2_TX 0x00= 74 0x0278 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO25__TPM4_CH3 0x00= 74 0x0278 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK 0x00= 74 0x0278 0x060C 0x05 0x01 +#define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1 0x00= 74 0x0278 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25 0x00= 74 0x0278 0x04CC 0x07 0x00 + +#define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x00= 78 0x027C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO26__USDHC3_DATA2 0x00= 78 0x027C 0x05D8 0x01 0x00 +#define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x00= 78 0x027C 0x0410 0x02 0x02 +#define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26 0x00= 78 0x027C 0x0458 0x03 0x01 +#define IMX95_PAD_GPIO_IO26__TPM5_CH3 0x00= 78 0x027C 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI 0x00= 78 0x027C 0x0610 0x05 0x01 +#define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1 0x00= 78 0x027C 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x00= 78 0x027C 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x00= 7C 0x0280 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO27__USDHC3_DATA3 0x00= 7C 0x0280 0x05DC 0x01 0x00 +#define IMX95_PAD_GPIO_IO27__CAN2_RX 0x00= 7C 0x0280 0x0444 0x02 0x02 +#define IMX95_PAD_GPIO_IO27__TPM6_CH3 0x00= 7C 0x0280 0x0000 0x04 0x00 +#define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS 0x00= 7C 0x0280 0x0614 0x05 0x01 +#define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1 0x00= 7C 0x0280 0x0000 0x06 0x00 +#define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27 0x00= 7C 0x0280 0x045C 0x07 0x01 + +#define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x00= 80 0x0284 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x00= 80 0x0284 0x0504 0x11 0x01 +#define IMX95_PAD_GPIO_IO28__CAN3_TX 0x00= 80 0x0284 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28 0x00= 80 0x0284 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x00= 84 0x0288 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x00= 84 0x0288 0x0500 0x11 0x01 +#define IMX95_PAD_GPIO_IO29__CAN3_RX 0x00= 84 0x0288 0x0448 0x02 0x01 +#define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29 0x00= 84 0x0288 0x0000 0x07 0x00 + +#define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x00= 88 0x028C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x00= 88 0x028C 0x050C 0x11 0x01 +#define IMX95_PAD_GPIO_IO30__CAN5_TX 0x00= 88 0x028C 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30 0x00= 88 0x028C 0x0460 0x07 0x01 + +#define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x00= 8C 0x0290 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x00= 8C 0x0290 0x0508 0x11 0x01 +#define IMX95_PAD_GPIO_IO31__CAN5_RX 0x00= 8C 0x0290 0x0450 0x02 0x01 +#define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31 0x00= 8C 0x0290 0x0464 0x07 0x01 + +#define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x00= 90 0x0294 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x00= 90 0x0294 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO32__LPUART6_TX 0x00= 90 0x0294 0x0580 0x02 0x00 +#define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2 0x00= 90 0x0294 0x0538 0x04 0x00 + +#define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x00= 94 0x0298 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO33__LPUART6_RX 0x00= 94 0x0298 0x057C 0x02 0x00 +#define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1 0x00= 94 0x0298 0x0534 0x04 0x00 + +#define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x00= 98 0x029C 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x00= 98 0x029C 0x0578 0x02 0x00 +#define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0 0x00= 98 0x029C 0x0530 0x04 0x00 + +#define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x00= 9C 0x02A0 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x00= 9C 0x02A0 0x0000 0x01 0x00 +#define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B 0x00= 9C 0x02A0 0x0000 0x02 0x00 +#define IMX95_PAD_GPIO_IO35__LPSPI4_SIN 0x00= 9C 0x02A0 0x0540 0x04 0x00 + +#define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x00= A0 0x02A4 0x0544 0x04 0x00 +#define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x00= A0 0x02A4 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO36__LPUART7_TX 0x00= A0 0x02A4 0x0588 0x02 0x00 + +#define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x00= A4 0x02A8 0x0000 0x00 0x00 +#define IMX95_PAD_GPIO_IO37__LPUART7_RX 0x00= A4 0x02A8 0x0584 0x02 0x00 +#define IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x00= A4 0x02A8 0x053C 0x04 0x00 + +#define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00= A8 0x02AC 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00= A8 0x02AC 0x0434 0x01 0x00 +#define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26 0x00= A8 0x02AC 0x0458 0x04 0x00 +#define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26 0x00= A8 0x02AC 0x0000 0x05 0x00 + +#define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x00= AC 0x02B0 0x0000 0x05 0x00 +#define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00= AC 0x02B0 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00= AC 0x02B0 0x0000 0x01 0x00 +#define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27 0x00= AC 0x02B0 0x045C 0x04 0x00 + +#define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00= B0 0x02B4 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00= B0 0x02B4 0x0438 0x01 0x00 +#define IMX95_PAD_CCM_CLKO3__CAN3_TX 0x00= B0 0x02B4 0x0000 0x02 0x00 +#define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28 0x00= B0 0x02B4 0x0000 0x04 0x00 +#define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x00= B0 0x02B4 0x0000 0x05 0x00 + +#define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00= B4 0x02B8 0x0000 0x00 0x00 +#define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00= B4 0x02B8 0x0000 0x01 0x00 +#define IMX95_PAD_CCM_CLKO4__CAN3_RX 0x00= B4 0x02B8 0x0448 0x02 0x00 +#define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29 0x00= B4 0x02B8 0x0000 0x04 0x00 +#define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x00= B4 0x02B8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00= B8 0x02BC 0x0424 0x00 0x00 +#define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B 0x00= B8 0x02BC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_MDC__I3C2_SCL 0x00= B8 0x02BC 0x04F8 0x02 0x00 +#define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00= B8 0x02BC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0 0x00= B8 0x02BC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x00= B8 0x02BC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00= BC 0x02C0 0x0428 0x00 0x00 +#define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B 0x00= BC 0x02C0 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x00= BC 0x02C0 0x04FC 0x02 0x00 +#define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00= BC 0x02C0 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1 0x00= BC 0x02C0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x00= BC 0x02C0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00= C0 0x02C4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD3__CAN2_TX 0x00= C0 0x02C4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00= C0 0x02C4 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2 0x00= C0 0x02C4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2 0x00= C0 0x02C4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00= C4 0x02C8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00= C4 0x02C8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TD2__CAN2_RX 0x00= C4 0x02C8 0x0444 0x02 0x01 +#define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00= C4 0x02C8 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3 0x00= C4 0x02C8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3 0x00= C4 0x02C8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00= C8 0x02CC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B 0x00= C8 0x02CC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TD1__I3C2_PUR 0x00= C8 0x02CC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00= C8 0x02CC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4 0x00= C8 0x02CC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4 0x00= C8 0x02CC 0x0000 0x05 0x00 +#define IMX95_PAD_ENET1_TD1__I3C2_PUR_B 0x00= C8 0x02CC 0x0000 0x06 0x00 +#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00= C8 0x02CC 0x0000 0x07 0x00 + +#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00= CC 0x02D0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TD0__LPUART3_TX 0x00= CC 0x02D0 0x055C 0x01 0x00 +#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00= CC 0x02D0 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5 0x00= CC 0x02D0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5 0x00= CC 0x02D0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00= D0 0x02D4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00= D0 0x02D4 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00= D0 0x02D4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6 0x00= D0 0x02D4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 0x00= D0 0x02D4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x00= D4 0x02D8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x00= D4 0x02D8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7 0x00= D4 0x02D8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7 0x00= D4 0x02D8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x00= D8 0x02DC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00= D8 0x02DC 0x0000 0x01 0x00 +#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x00= D8 0x02DC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x00= D8 0x02DC 0x0000 0x03 0x00 +#define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8 0x00= D8 0x02DC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 0x00= D8 0x02DC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x00= DC 0x02E0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00= DC 0x02E0 0x042C 0x01 0x00 +#define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9 0x00= DC 0x02E0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9 0x00= DC 0x02E0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x00= E0 0x02E4 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD0__LPUART3_RX 0x00= E0 0x02E4 0x0558 0x01 0x00 +#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x00= E0 0x02E4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10 0x00= E0 0x02E4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10 0x00= E0 0x02E4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x00= E4 0x02E8 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B 0x00= E4 0x02E8 0x0554 0x01 0x00 +#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x00= E4 0x02E8 0x0000 0x02 0x00 +#define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1 0x00= E4 0x02E8 0x0548 0x03 0x00 +#define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11 0x00= E4 0x02E8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11 0x00= E4 0x02E8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x00= E8 0x02EC 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00= E8 0x02EC 0x042C 0x02 0x01 +#define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2 0x00= E8 0x02EC 0x054C 0x03 0x00 +#define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12 0x00= E8 0x02EC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12 0x00= E8 0x02EC 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x00= EC 0x02F0 0x0000 0x00 0x00 +#define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3 0x00= EC 0x02F0 0x0550 0x03 0x00 +#define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13 0x00= EC 0x02F0 0x0000 0x04 0x00 +#define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13 0x00= EC 0x02F0 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x00= F0 0x02F4 0x0424 0x00 0x01 +#define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B 0x00= F0 0x02F4 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x00= F0 0x02F4 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14 0x00= F0 0x02F4 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x00= F0 0x02F4 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x00= F4 0x02F8 0x0428 0x00 0x01 +#define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00= F4 0x02F8 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x00= F4 0x02F8 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15 0x00= F4 0x02F8 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x00= F4 0x02F8 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x00= F8 0x02FC 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16 0x00= F8 0x02FC 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16 0x00= F8 0x02FC 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x00= F8 0x02FC 0x0000 0x00 0x00 + +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x00= FC 0x0300 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x00= FC 0x0300 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x00= FC 0x0300 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC 0x00= FC 0x0300 0x05A4 0x03 0x00 +#define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17 0x00= FC 0x0300 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x00= FC 0x0300 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x01= 00 0x0304 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B 0x01= 00 0x0304 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x01= 00 0x0304 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK 0x01= 00 0x0304 0x05A0 0x03 0x00 +#define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18 0x01= 00 0x0304 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x01= 00 0x0304 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x01= 00 0x0304 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x01= 04 0x0308 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TD0__LPUART4_TX 0x01= 04 0x0308 0x0568 0x01 0x00 +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x01= 04 0x0308 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 0x01= 04 0x0308 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19 0x01= 04 0x0308 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x01= 04 0x0308 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x01= 04 0x0308 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x01= 08 0x030C 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x01= 08 0x030C 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x01= 08 0x030C 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x01= 08 0x030C 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20 0x01= 08 0x030C 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 0x01= 08 0x030C 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x01= 0C 0x0310 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x01= 0C 0x0310 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x01= 0C 0x0310 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21 0x01= 0C 0x0310 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21 0x01= 0C 0x0310 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x01= 10 0x0314 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x01= 10 0x0314 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x01= 10 0x0314 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22 0x01= 10 0x0314 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 0x01= 10 0x0314 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x01= 10 0x0314 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x01= 14 0x0318 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x01= 14 0x0318 0x0430 0x01 0x00 +#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x01= 14 0x0318 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC 0x01= 14 0x0318 0x059C 0x03 0x00 +#define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23 0x01= 14 0x0318 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x01= 14 0x0318 0x0000 0x05 0x00 + +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x01= 18 0x031C 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD0__LPUART4_RX 0x01= 18 0x031C 0x0564 0x01 0x00 +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x01= 18 0x031C 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK 0x01= 18 0x031C 0x0594 0x03 0x00 +#define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24 0x01= 18 0x031C 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x01= 18 0x031C 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x01= 18 0x031C 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x01= 1C 0x0320 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD1__SPDIF_IN 0x01= 1C 0x0320 0x0454 0x01 0x00 +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x01= 1C 0x0320 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 0x01= 1C 0x0320 0x0598 0x03 0x00 +#define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25 0x01= 1C 0x0320 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x01= 1C 0x0320 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x01= 1C 0x0320 0x0000 0x06 0x00 + +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x01= 20 0x0324 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B 0x01= 20 0x0324 0x0560 0x01 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x01= 20 0x0324 0x0000 0x02 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x01= 20 0x0324 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26 0x01= 20 0x0324 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26 0x01= 20 0x0324 0x0000 0x05 0x00 +#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x01= 20 0x0324 0x0430 0x06 0x01 + +#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x01= 24 0x0328 0x0000 0x00 0x00 +#define IMX95_PAD_ENET2_RD3__SPDIF_OUT 0x01= 24 0x0328 0x0000 0x01 0x00 +#define IMX95_PAD_ENET2_RD3__SPDIF_IN 0x01= 24 0x0328 0x0454 0x02 0x01 +#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x01= 24 0x0328 0x0000 0x03 0x00 +#define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27 0x01= 24 0x0328 0x0000 0x04 0x00 +#define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x01= 24 0x0328 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 0x01= 28 0x032C 0x0488 0x04 0x01 +#define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8 0x01= 28 0x032C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_CLK__USDHC1_CLK 0x01= 28 0x032C 0x0000 0x00 0x00 + +#define IMX95_PAD_SD1_CMD__USDHC1_CMD 0x01= 2C 0x0330 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 0x01= 2C 0x0330 0x048C 0x04 0x01 +#define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9 0x01= 2C 0x0330 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x01= 30 0x0334 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10 0x01= 30 0x0334 0x0490 0x04 0x01 +#define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10 0x01= 30 0x0334 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x01= 34 0x0338 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11 0x01= 34 0x0338 0x0494 0x04 0x01 +#define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11 0x01= 34 0x0338 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x01= 38 0x033C 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12 0x01= 38 0x033C 0x0498 0x04 0x01 +#define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12 0x01= 38 0x033C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x01= 38 0x033C 0x0000 0x06 0x00 + +#define IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x01= 3C 0x0340 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x01= 3C 0x0340 0x0000 0x01 0x00 +#define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13 0x01= 3C 0x0340 0x049C 0x04 0x01 +#define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13 0x01= 3C 0x0340 0x0000 0x05 0x00 + +#define IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x01= 40 0x0344 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4 0x01= 40 0x0344 0x04E4 0x01 0x00 +#define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14 0x01= 40 0x0344 0x04A0 0x04 0x01 +#define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14 0x01= 40 0x0344 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4 0x01= 40 0x0344 0x05FC 0x06 0x00 + +#define IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x01= 44 0x0348 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5 0x01= 44 0x0348 0x04E8 0x01 0x00 +#define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B 0x01= 44 0x0348 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15 0x01= 44 0x0348 0x04A4 0x04 0x01 +#define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15 0x01= 44 0x0348 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5 0x01= 44 0x0348 0x0600 0x06 0x00 + +#define IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x01= 48 0x034C 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6 0x01= 48 0x034C 0x04EC 0x01 0x00 +#define IMX95_PAD_SD1_DATA6__USDHC1_CD_B 0x01= 48 0x034C 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16 0x01= 48 0x034C 0x04A8 0x04 0x01 +#define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16 0x01= 48 0x034C 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6 0x01= 48 0x034C 0x0604 0x06 0x00 + +#define IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x01= 4C 0x0350 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7 0x01= 4C 0x0350 0x04F0 0x01 0x00 +#define IMX95_PAD_SD1_DATA7__USDHC1_WP 0x01= 4C 0x0350 0x0000 0x02 0x00 +#define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17 0x01= 4C 0x0350 0x04AC 0x04 0x01 +#define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17 0x01= 4C 0x0350 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7 0x01= 4C 0x0350 0x0608 0x06 0x00 + +#define IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x01= 50 0x0354 0x0000 0x00 0x00 +#define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x01= 50 0x0354 0x04D0 0x01 0x00 +#define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18 0x01= 50 0x0354 0x04B0 0x04 0x01 +#define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18 0x01= 50 0x0354 0x0000 0x05 0x00 +#define IMX95_PAD_SD1_STROBE__XSPI_DQS 0x01= 50 0x0354 0x05E4 0x06 0x00 + +#define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x01= 54 0x0358 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_VSELECT__USDHC2_WP 0x01= 54 0x0358 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3 0x01= 54 0x0358 0x0550 0x02 0x01 +#define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19 0x01= 54 0x0358 0x04B4 0x04 0x01 +#define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x01= 54 0x0358 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x01= 54 0x0358 0x0420 0x06 0x01 + +#define IMX95_PAD_SD3_CLK__USDHC3_CLK 0x01= 58 0x035C 0x05C8 0x00 0x01 +#define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01= 58 0x035C 0x04F4 0x01 0x00 +#define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 0x01= 58 0x035C 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 0x01= 58 0x035C 0x05AC 0x03 0x00 +#define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20 0x01= 58 0x035C 0x04B8 0x04 0x01 +#define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 0x01= 58 0x035C 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_CLK__XSPI_CLK 0x01= 58 0x035C 0x05E8 0x06 0x00 + +#define IMX95_PAD_SD3_CMD__USDHC3_CMD 0x01= 5C 0x0360 0x05CC 0x00 0x01 +#define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01= 5C 0x0360 0x0000 0x01 0x00 +#define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 0x01= 5C 0x0360 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC 0x01= 5C 0x0360 0x05BC 0x03 0x00 +#define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21 0x01= 5C 0x0360 0x04BC 0x04 0x01 +#define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x01= 5C 0x0360 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_CMD__XSPI_CS 0x01= 5C 0x0360 0x05E0 0x06 0x00 + +#define IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x01= 60 0x0364 0x05D0 0x00 0x01 +#define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x01= 60 0x0364 0x04D4 0x01 0x00 +#define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 0x01= 60 0x0364 0x0000 0x02 0x00 +#define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK 0x01= 60 0x0364 0x05A8 0x03 0x00 +#define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22 0x01= 60 0x0364 0x04C0 0x04 0x01 +#define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x01= 60 0x0364 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0 0x01= 60 0x0364 0x05EC 0x06 0x00 + +#define IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x01= 64 0x0368 0x05D4 0x00 0x01 +#define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x01= 64 0x0368 0x04D8 0x01 0x00 +#define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 0x01= 64 0x0368 0x05B0 0x02 0x00 +#define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 0x01= 64 0x0368 0x0000 0x03 0x00 +#define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23 0x01= 64 0x0368 0x04C4 0x04 0x01 +#define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x01= 64 0x0368 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1 0x01= 64 0x0368 0x05F0 0x06 0x00 + +#define IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x01= 68 0x036C 0x05D8 0x00 0x01 +#define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x01= 68 0x036C 0x04DC 0x01 0x00 +#define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 0x01= 68 0x036C 0x05B4 0x02 0x00 +#define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC 0x01= 68 0x036C 0x05C4 0x03 0x00 +#define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24 0x01= 68 0x036C 0x04C8 0x04 0x01 +#define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x01= 68 0x036C 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2 0x01= 68 0x036C 0x05F4 0x06 0x00 + +#define IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x01= 6C 0x0370 0x05DC 0x00 0x01 +#define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x01= 6C 0x0370 0x04E0 0x01 0x00 +#define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 0x01= 6C 0x0370 0x05B8 0x02 0x00 +#define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK 0x01= 6C 0x0370 0x05C0 0x03 0x00 +#define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25 0x01= 6C 0x0370 0x04CC 0x04 0x01 +#define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x01= 6C 0x0370 0x0000 0x05 0x00 +#define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3 0x01= 6C 0x0370 0x05F8 0x06 0x00 + +#define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x01= 70 0x0374 0x04D4 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x01= 70 0x0374 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK 0x01= 70 0x0374 0x05A0 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1 0x01= 70 0x0374 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x01= 70 0x0374 0x05EC 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x01= 70 0x0374 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x01= 74 0x0378 0x04D8 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x01= 74 0x0378 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC 0x01= 74 0x0378 0x05A4 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1 0x01= 74 0x0378 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x01= 74 0x0378 0x05F0 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x01= 74 0x0378 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x01= 78 0x037C 0x04DC 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x01= 78 0x037C 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0 0x01= 78 0x037C 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x01= 78 0x037C 0x05F4 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x01= 78 0x037C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x01= 7C 0x0380 0x04E0 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x01= 7C 0x0380 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0 0x01= 7C 0x0380 0x0598 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x01= 7C 0x0380 0x05F8 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x01= 7C 0x0380 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x01= 80 0x0384 0x04E4 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x01= 80 0x0384 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1 0x01= 80 0x0384 0x05B0 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 0x01= 80 0x0384 0x05FC 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x01= 80 0x0384 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x01= 84 0x0388 0x04E8 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x01= 84 0x0388 0x05C4 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2 0x01= 84 0x0388 0x05B4 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x01= 84 0x0388 0x043C 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 0x01= 84 0x0388 0x0600 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x01= 84 0x0388 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x01= 88 0x038C 0x04EC 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x01= 88 0x038C 0x05C0 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3 0x01= 88 0x038C 0x05B8 0x02 0x01 +#define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x01= 88 0x038C 0x0440 0x03 0x00 +#define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 0x01= 88 0x038C 0x0604 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x01= 88 0x038C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x01= 8C 0x0390 0x04F0 0x00 0x01 +#define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x01= 8C 0x0390 0x05AC 0x01 0x01 +#define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1 0x01= 8C 0x0390 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 0x01= 8C 0x0390 0x0608 0x04 0x01 +#define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x01= 8C 0x0390 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x01= 90 0x0394 0x04D0 0x00 0x01 +#define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x01= 90 0x0394 0x05BC 0x01 0x01 +#define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 0x01= 90 0x0394 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x01= 90 0x0394 0x043C 0x03 0x01 +#define IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x01= 90 0x0394 0x05E4 0x04 0x01 +#define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x01= 90 0x0394 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x01= 94 0x0398 0x04F4 0x00 0x01 +#define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_BIT4 0x01= 94 0x0398 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC 0x01= 94 0x0398 0x059C 0x02 0x01 +#define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 0x01= 94 0x0398 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x01= 94 0x0398 0x05E8 0x04 0x01 +#define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x01= 94 0x0398 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x01= 98 0x039C 0x0000 0x00 0x00 +#define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_BIT5 0x01= 98 0x039C 0x0000 0x01 0x00 +#define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x01= 98 0x039C 0x0594 0x02 0x01 +#define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT 0x01= 98 0x039C 0x0000 0x03 0x00 +#define IMX95_PAD_XSPI1_SS0_B__XSPI_CS 0x01= 98 0x039C 0x05E0 0x04 0x01 +#define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x01= 98 0x039C 0x0000 0x05 0x00 + +#define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x01= 9C 0x03A0 0x0000 0x00 0x00 +#define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x01= 9C 0x03A0 0x05A8 0x01 0x01 +#define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3 0x01= 9C 0x03A0 0x0000 0x02 0x00 +#define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x01= 9C 0x03A0 0x0440 0x03 0x01 +#define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x01= 9C 0x03A0 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x01= A0 0x03A4 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01= A0 0x03A4 0x0434 0x01 0x01 +#define IMX95_PAD_SD2_CD_B__I3C2_SCL 0x01= A0 0x03A4 0x04F8 0x02 0x01 +#define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0 0x01= A0 0x03A4 0x0468 0x04 0x01 +#define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x01= A0 0x03A4 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_CLK__USDHC2_CLK 0x01= A4 0x03A8 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01= A4 0x03A8 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_CLK__I3C2_SDA 0x01= A4 0x03A8 0x04FC 0x02 0x01 +#define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 0x01= A4 0x03A8 0x046C 0x04 0x01 +#define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1 0x01= A4 0x03A8 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01= A4 0x03A8 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_CMD__USDHC2_CMD 0x01= A8 0x03AC 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01= A8 0x03AC 0x0438 0x01 0x01 +#define IMX95_PAD_SD2_CMD__I3C2_PUR 0x01= A8 0x03AC 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_CMD__I3C2_PUR_B 0x01= A8 0x03AC 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 0x01= A8 0x03AC 0x0470 0x04 0x01 +#define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2 0x01= A8 0x03AC 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01= A8 0x03AC 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x01= AC 0x03B0 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01= AC 0x03B0 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA0__CAN2_TX 0x01= AC 0x03B0 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3 0x01= AC 0x03B0 0x0474 0x04 0x01 +#define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3 0x01= AC 0x03B0 0x0000 0x05 0x00 +#define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01= AC 0x03B0 0x0000 0x06 0x00 + +#define IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x01= B0 0x03B4 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01= B0 0x03B4 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA1__CAN2_RX 0x01= B0 0x03B4 0x0444 0x02 0x03 +#define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4 0x01= B0 0x03B4 0x0478 0x04 0x01 +#define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4 0x01= B0 0x03B4 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x01= B4 0x03B8 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01= B4 0x03B8 0x0000 0x01 0x00 +#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01= B4 0x03B8 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5 0x01= B4 0x03B8 0x047C 0x04 0x01 +#define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5 0x01= B4 0x03B8 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x01= B8 0x03BC 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1 0x01= B8 0x03BC 0x0548 0x01 0x01 +#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01= B8 0x03BC 0x0000 0x02 0x00 +#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01= B8 0x03BC 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6 0x01= B8 0x03BC 0x0480 0x04 0x01 +#define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6 0x01= B8 0x03BC 0x0000 0x05 0x00 + +#define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B 0x01= BC 0x03C0 0x0000 0x00 0x00 +#define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2 0x01= BC 0x03C0 0x054C 0x01 0x01 +#define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01= BC 0x03C0 0x0000 0x03 0x00 +#define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7 0x01= BC 0x03C0 0x0484 0x04 0x01 +#define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x01= BC 0x03C0 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01= C0 0x03C4 0x0000 0x00 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01= C0 0x03C4 0x0000 0x01 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01= C0 0x03C4 0x0000 0x02 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01= C0 0x03C4 0x0000 0x03 0x00 +#define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01= C0 0x03C4 0x0000 0x04 0x00 +#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_BIT0 0x01= C0 0x03C4 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01= C4 0x03C8 0x0000 0x00 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01= C4 0x03C8 0x0000 0x01 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01= C4 0x03C8 0x0000 0x02 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01= C4 0x03C8 0x0000 0x03 0x00 +#define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01= C4 0x03C8 0x0000 0x04 0x00 +#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_BIT1 0x01= C4 0x03C8 0x0000 0x05 0x00 + +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01= C8 0x03CC 0x0000 0x00 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01= C8 0x03CC 0x0000 0x01 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01= C8 0x03CC 0x0000 0x02 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01= C8 0x03CC 0x0000 0x03 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01= C8 0x03CC 0x0000 0x04 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x01= C8 0x03CC 0x0000 0x05 0x00 +#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01= C8 0x03CC 0x0000 0x06 0x00 + +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01= CC 0x03D0 0x0000 0x00 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01= CC 0x03D0 0x0000 0x02 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01= CC 0x03D0 0x0000 0x03 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01= CC 0x03D0 0x0000 0x04 0x00 +#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x01= CC 0x03D0 0x0000 0x05 0x00 + +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01= D0 0x03D4 0x0000 0x00 0x00 +#define IMX95_PAD_UART1_RXD__S400_UART_RX 0x01= D0 0x03D4 0x0000 0x01 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01= D0 0x03D4 0x0000 0x02 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01= D0 0x03D4 0x0000 0x03 0x00 +#define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4 0x01= D0 0x03D4 0x0000 0x05 0x00 + +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x01= D4 0x03D8 0x0000 0x00 0x00 +#define IMX95_PAD_UART1_TXD__S400_UART_TX 0x01= D4 0x03D8 0x0000 0x01 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x01= D4 0x03D8 0x0000 0x02 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x01= D4 0x03D8 0x0000 0x03 0x00 +#define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5 0x01= D4 0x03D8 0x0000 0x05 0x00 + +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x01= D8 0x03DC 0x0000 0x00 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x01= D8 0x03DC 0x0000 0x01 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x01= D8 0x03DC 0x0000 0x02 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x01= D8 0x03DC 0x0000 0x03 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x01= D8 0x03DC 0x041C 0x04 0x00 +#define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_BIT6 0x01= D8 0x03DC 0x0000 0x05 0x00 + +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x01= DC 0x03E0 0x0000 0x00 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x01= DC 0x03E0 0x0000 0x01 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x01= DC 0x03E0 0x0000 0x02 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x01= DC 0x03E0 0x0000 0x03 0x00 +#define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x01= DC 0x03E0 0x0000 0x05 0x00 + +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x01= E0 0x03E4 0x0000 0x00 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x01= E0 0x03E4 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT1 0x01= E0 0x03E4 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x01= E0 0x03E4 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x01= E0 0x03E4 0x0000 0x06 0x00 + +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x01= E4 0x03E8 0x040C 0x00 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x01= E4 0x03E8 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x01= E4 0x03E8 0x0000 0x02 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x01= E4 0x03E8 0x0000 0x03 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT2 0x01= E4 0x03E8 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x01= E4 0x03E8 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x01= E4 0x03E8 0x0408 0x06 0x00 + +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x01= E8 0x03EC 0x0410 0x00 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x01= E8 0x03EC 0x0000 0x01 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x01= E8 0x03EC 0x0000 0x02 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x01= E8 0x03EC 0x0000 0x03 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT3 0x01= E8 0x03EC 0x0000 0x04 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x01= E8 0x03EC 0x0000 0x05 0x00 +#define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x01= E8 0x03EC 0x0420 0x06 0x00 + +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x01= EC 0x03F0 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_BIT1 0x01= EC 0x03F0 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x01= EC 0x03F0 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x01= EC 0x03F0 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x01= EC 0x03F0 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x01= EC 0x03F0 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x01= F0 0x03F4 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x01= F0 0x03F4 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x01= F0 0x03F4 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x01= F0 0x03F4 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x01= F0 0x03F4 0x0408 0x04 0x01 +#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x01= F0 0x03F4 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x01= F4 0x03F8 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x01= F4 0x03F8 0x0000 0x01 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x01= F4 0x03F8 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x01= F4 0x03F8 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x01= F4 0x03F8 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x01= F4 0x03F8 0x0000 0x05 0x00 + +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x01= F8 0x03FC 0x0000 0x00 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x01= F8 0x03FC 0x041C 0x01 0x01 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x01= F8 0x03FC 0x0000 0x02 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x01= F8 0x03FC 0x0000 0x03 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x01= F8 0x03FC 0x0000 0x04 0x00 +#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x01= F8 0x03FC 0x0000 0x05 0x00 + +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x01= FC 0x0400 0x0000 0x00 0x00 +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x01= FC 0x0400 0x0000 0x01 0x00 +#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_BIT15 0x01= FC 0x0400 0x0000 0x05 0x00 +#endif /* __DTS_IMX95_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95-power.h b/arch/arm64/boot/= dts/freescale/imx95-power.h new file mode 100644 index 000000000000..0b7f0bc30e19 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-power.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __IMX95_POWER_H__ +#define __IMX95_POWER_H__ + +#define IMX95_PD_ANA 0 +#define IMX95_PD_AON 1 +#define IMX95_PD_BBSM 2 +#define IMX95_PD_CAMERA 3 +#define IMX95_PD_CCMSRCGPC 4 +#define IMX95_PD_A55C0 5 +#define IMX95_PD_A55C1 6 +#define IMX95_PD_A55C2 7 +#define IMX95_PD_A55C3 8 +#define IMX95_PD_A55C4 9 +#define IMX95_PD_A55C5 10 +#define IMX95_PD_A55P 11 +#define IMX95_PD_DDR 12 +#define IMX95_PD_DISPLAY 13 +#define IMX95_PD_GPU 14 +#define IMX95_PD_HSIO_TOP 15 +#define IMX95_PD_HSIO_WAON 16 +#define IMX95_PD_M7 17 +#define IMX95_PD_NETC 18 +#define IMX95_PD_NOC 19 +#define IMX95_PD_NPU 20 +#define IMX95_PD_VPU 21 +#define IMX95_PD_WAKEUP 22 + +#define IMX95_PERF_ELE 0 +#define IMX95_PERF_M33 1 +#define IMX95_PERF_WAKEUP 2 +#define IMX95_PERF_M7 3 +#define IMX95_PERF_DRAM 4 +#define IMX95_PERF_HSIO 5 +#define IMX95_PERF_NPU 6 +#define IMX95_PERF_NOC 7 +#define IMX95_PERF_A55 8 +#define IMX95_PERF_GPU 9 +#define IMX95_PERF_VPU 10 +#define IMX95_PERF_CAM 11 +#define IMX95_PERF_DISP 12 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts= /freescale/imx95.dtsi new file mode 100644 index 000000000000..f98cec944eee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -0,0 +1,1042 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include + +#include "imx95-clock.h" +#include "imx95-pinfunc.h" +#include "imx95-power.h" + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + A55_0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l3>; + }; + + A55_4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l4>; + }; + + A55_5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + power-domains =3D <&scmi_devpd IMX95_PERF_A55>; + power-domain-names =3D "perf"; + enable-method =3D "psci"; + #cooling-cells =3D <2>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_cache_l5>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l4: l2-cache-l4 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l5: l2-cache-l5 { + compatible =3D "cache"; + cache-size =3D <65536>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible =3D "cache"; + cache-size =3D <524288>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&A55_0>; + }; + + core1 { + cpu =3D <&A55_1>; + }; + + core2 { + cpu =3D <&A55_2>; + }; + + core3 { + cpu =3D <&A55_3>; + }; + + core4 { + cpu =3D <&A55_4>; + }; + + core5 { + cpu =3D <&A55_5>; + }; + }; + }; + }; + + clk_ext1: clock-ext1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <133000000>; + clock-output-names =3D "clk_ext1"; + }; + + sai1_mclk: clock-sai-mclk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai1_mclk"; + }; + + sai2_mclk: clock-sai-mclk2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai2_mclk"; + }; + + sai3_mclk: clock-sai-mclk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai3_mclk"; + }; + + sai4_mclk: clock-sai-mclk4 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai4_mclk"; + }; + + sai5_mclk: clock-sai-mclk5 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency=3D <0>; + clock-output-names =3D "sai5_mclk"; + }; + + osc_24m: clock-24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc_24m"; + }; + + sram1: sram@204c0000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x204c0000 0x0 0x18000>; + ranges =3D <0x0 0x0 0x204c0000 0x18000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + firmware { + scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>; + shmem =3D <&scmi_buf0>, <&scmi_buf1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_devpd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi_perf: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + + scmi_sensor: protocol@15 { + reg =3D <0x15>; + #thermal-sensor-cells =3D <1>; + }; + + scmi_iomuxc: protocol@19 { + reg =3D <0x19>; + }; + + }; + }; + + pmu { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + thermal-zones { + a55-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&scmi_sensor 1>; + + trips { + cpu_alert0: trip0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_crit0: trip1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_alert0>; + cooling-device =3D + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <24000000>; + arm,no-tick-in-suspend; + interrupt-parent =3D <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + interrupt-parent =3D <&gic>; + dma-noncoherent; + ranges; + + its: msi-controller@48040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + dma-noncoherent; + }; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + aips2: bus@42000000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0x0 0x42000000 0x0 0x800000>; + ranges =3D <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mu7: mailbox@42430000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x42430000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + wdog3: watchdog@42490000 { + compatible =3D "fsl,imx93-wdt"; + reg =3D <0x42490000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + timeout-sec =3D <40>; + status =3D "disabled"; + }; + + tpm3: pwm@424e0000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x424e0000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x424f0000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM4>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm5: pwm@42500000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x42500000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM5>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm6: pwm@42510000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x42510000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM6>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x42530000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x42540000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42550000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI3>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42560000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI4>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpuart3: serial@42570000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42570000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART3>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart4: serial@42580000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42580000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART4>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart5: serial@42590000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42590000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART5>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x425a0000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART6>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart7: serial@42690000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x42690000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART7>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x426a0000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART8>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426b0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426c0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426d0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x426e0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x426f0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI5>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42700000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI6>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42710000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI7>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x42720000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI8>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + mu8: mailbox@42730000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x42730000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0 0x42800000 0 0x800000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x42800000 0x0 0x42800000 0x800000>; + + usdhc1: mmc@42850000 { + compatible =3D "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg =3D <0x42850000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC1>; + clock-names =3D "ipg", "ahb", "per"; + assigned-clocks =3D <&scmi_clk IMX95_CLK_USDHC1>; + assigned-clock-parents =3D <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <8>; + fsl,tuning-start-tap =3D <1>; + fsl,tuning-step=3D <2>; + status =3D "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible =3D "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg =3D <0x42860000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC2>; + clock-names =3D "ipg", "ahb", "per"; + assigned-clocks =3D <&scmi_clk IMX95_CLK_USDHC2>; + assigned-clock-parents =3D <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <4>; + fsl,tuning-start-tap =3D <1>; + fsl,tuning-step=3D <2>; + status =3D "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible =3D "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg =3D <0x428b0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_WAKEUPAXI>, + <&scmi_clk IMX95_CLK_USDHC3>; + clock-names =3D "ipg", "ahb", "per"; + assigned-clocks =3D <&scmi_clk IMX95_CLK_USDHC3>; + assigned-clock-parents =3D <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <4>; + fsl,tuning-start-tap =3D <1>; + fsl,tuning-step=3D <2>; + status =3D "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + gpio-ranges =3D <&scmi_iomuxc 0 4 32>; + }; + + gpio3: gpio@43820000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + gpio-ranges =3D <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, + <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; + }; + + gpio4: gpio@43840000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + gpio-ranges =3D <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; + }; + + gpio5: gpio@43850000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_BUSWAKEUP>; + clock-names =3D "gpio", "port"; + gpio-ranges =3D <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; + }; + + aips1: bus@44000000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0x0 0x44000000 0x0 0x800000>; + ranges =3D <0x44000000 0x0 0x44000000 0x800000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mu1: mailbox@44220000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x44220000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + tpm1: pwm@44310000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x44310000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + tpm2: pwm@44320000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x44320000 0x1000>; + clocks =3D <&scmi_clk IMX95_CLK_TPM2>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x44340000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible =3D "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x44350000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPI2C2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x44360000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI1>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg =3D <0x44370000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPSPI2>, + <&scmi_clk IMX95_CLK_BUSAON>; + clock-names =3D "per", "ipg"; + status =3D "disabled"; + }; + + lpuart1: serial@44380000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x44380000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART1>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + lpuart2: serial@44390000 { + compatible =3D "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg =3D <0x44390000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_LPUART2>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + adc1: adc@44530000 { + compatible =3D "nxp,imx93-adc"; + reg =3D <0x44530000 0x10000>; + interrupts =3D , + , + ; + clocks =3D <&scmi_clk IMX95_CLK_ADC>; + clock-names =3D "ipg"; + status =3D "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x445b0000 0x1000>; + ranges; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + #mbox-cells =3D <2>; + + sram0: sram@445b1000 { + compatible =3D "mmio-sram"; + reg =3D <0x445b1000 0x400>; + ranges =3D <0x0 0x445b1000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x445d0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x445f0000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + mu6: mailbox@44630000 { + compatible =3D "fsl,imx95-mu"; + reg =3D <0x44630000 0x10000>; + interrupts =3D ; + clocks =3D <&scmi_clk IMX95_CLK_BUSAON>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + }; + + mailbox@47320000 { + compatible =3D "fsl,imx95-mu-v2x"; + reg =3D <0x0 0x47320000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + + mailbox@47350000 { + compatible =3D "fsl,imx95-mu-v2x"; + reg =3D <0x0 0x47350000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible =3D "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg =3D <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupts =3D , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&scmi_clk IMX95_CLK_M33>, + <&scmi_clk IMX95_CLK_M33>; + clock-names =3D "gpio", "port"; + gpio-ranges =3D <&scmi_iomuxc 0 112 16>; + status =3D "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47520000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47530000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47540000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47550000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + + elemu4: mailbox@47560000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47560000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible =3D "fsl,imx95-mu-ele"; + reg =3D <0x0 0x47570000 0x0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + aips4: bus@49000000 { + compatible =3D "fsl,aips-bus", "simple-bus"; + reg =3D <0x0 0x49000000 0x0 0x800000>; + ranges =3D <0x49000000 0x0 0x49000000 0x800000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + smmu: iommu@490d0000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x490d0000 0x100000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells =3D <1>; + status =3D "disabled"; + }; + }; + }; +}; --=20 2.37.1 From nobody Fri Dec 19 16:05:44 2025 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2088.outbound.protection.outlook.com [40.107.6.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB957176ABF; Mon, 17 Jun 2024 02:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.88 ARC-Seal: i=2; a=rsa-sha256; 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arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++++++++++++++++= ++++ 2 files changed, 201 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 1b1e4db02071..c3fef4e4d8dd 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -239,6 +239,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk.dtb =20 imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64= /boot/dts/freescale/imx95-19x19-evk.dts new file mode 100644 index 000000000000..675abb70aa18 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include "imx95.dtsi" + +/ { + model =3D "NXP i.MX95 19X19 board"; + compatible =3D "fsl,imx95-19x19-evk", "fsl,imx95"; + + aliases { + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart1; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux_cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x80000000 0 0x7f000000>; + size =3D <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VDD_SD2_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us =3D <12000>; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&mu7 { + status =3D "okay"; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status =3D "okay"; +}; + +&scmi_iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins =3D < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; --=20 2.37.1