From nobody Wed Dec 17 04:08:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32C9B29428 for ; Sun, 16 Jun 2024 17:19:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558390; cv=none; b=mFJUeS+ryVxlIjsfsMXesxlPaA7n8FCQYjnVYDaRgFK8SV3AVyplarpyzPhwt4XROyBuUpP0qlcWgKXmTVyutT3m76Y0dxfeseLncI9VKfJMLaDVQ4AhHNOJrohfvI5c/T/H7Qxj/2MzwB4AcJDpEiQVt+y4S/EemkKnIXqpMJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558390; c=relaxed/simple; bh=Pd+tiD1d1gKrweB2fH2zKG5W19i1XxJlZfBI9MyqDG4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cr4MqWNS2as5UVM1x6d8n7/BVmyCqtPbvUXO4KXX257GSie/9UgLmlVURCTh6u1vV71VNP1kYUxZa2GnVkcoxdkA/eZGukSSzZSTyFE+RDcmPmnvxRgwu23GH5EaXoOVEW6Gb0zM5G4LFYfdFyR4mRJWRO9LAf8qi19JnpaDn6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fr3gZpJI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fr3gZpJI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3D620C4AF1D; Sun, 16 Jun 2024 17:19:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718558389; bh=Pd+tiD1d1gKrweB2fH2zKG5W19i1XxJlZfBI9MyqDG4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fr3gZpJIF+mNWTE/k8gjb6h8WqjKYJ5XHk32WwBuZc8BBz2lyf54J0u3VdCN3acew /hXcpsTrkkeyioYogaABM3hRLgX5jMh5nyo541LwzOl7nqgg3xPNdowHIgpz8vh0HJ YLvDhpEBndaex5SskayRd60TjumzaeTGrse3Ahb5p+qNy2ITuhWY3988dww4zuyzZk 0apSPidmNpl3UzXFVrJ6T0ByZcogNbLLpOmVo0JXxhNKvlOYtriq5F2wEgGdo/vHEf WZB0ITPpZX0Cl86QiYJt+EuWMOtmg/0mElBaj+f0gMl1wJkgDK/pbZmRWjq78KK68u X5vBu6LEFW/kw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anton Blanchard , Cyril Bur Subject: [PATCH 1/6] riscv: Improve exception and system call latency Date: Mon, 17 Jun 2024 01:05:48 +0800 Message-ID: <20240616170553.2832-2-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org> References: <20240616170553.2832-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Anton Blanchard Many CPUs implement return address branch prediction as a stack. The RISCV architecture refers to this as a return address stack (RAS). If this gets corrupted then the CPU will mispredict at least one but potentally many function returns. There are two issues with the current RISCV exception code: - We are using the alternate link stack (x5/t0) for the indirect branch which makes the hardware think this is a function return. This will corrupt the RAS. - We modify the return address of handle_exception to point to ret_from_exception. This will also corrupt the RAS. Testing the null system call latency before and after the patch: Visionfive2 (StarFive JH7110 / U74) baseline: 189.87 ns patched: 176.76 ns Lichee pi 4a (T-Head TH1520 / C910) baseline: 666.58 ns patched: 636.90 ns Just over 7% on the U74 and just over 4% on the C910. Signed-off-by: Anton Blanchard Signed-off-by: Cyril Bur Reviewed-by: Charlie Jenkins --- arch/riscv/kernel/entry.S | 17 ++++++++++------- arch/riscv/kernel/stacktrace.c | 4 ++-- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 68a24cf9481a..c933460ed3e9 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -88,7 +88,6 @@ SYM_CODE_START(handle_exception) call riscv_v_context_nesting_start #endif move a0, sp /* pt_regs */ - la ra, ret_from_exception =20 /* * MSB of cause differentiates between @@ -97,7 +96,8 @@ SYM_CODE_START(handle_exception) bge s4, zero, 1f =20 /* Handle interrupts */ - tail do_irq + call do_irq + j ret_from_exception 1: /* Handle other exceptions */ slli t0, s4, RISCV_LGPTR @@ -105,11 +105,14 @@ SYM_CODE_START(handle_exception) la t2, excp_vect_table_end add t0, t1, t0 /* Check if exception code lies within bounds */ - bgeu t0, t2, 1f - REG_L t0, 0(t0) - jr t0 -1: - tail do_trap_unknown + bgeu t0, t2, 3f + REG_L t1, 0(t0) +2: jalr t1 + j ret_from_exception +3: + + la t1, do_trap_unknown + j 2b SYM_CODE_END(handle_exception) ASM_NOKPROBE(handle_exception) =20 diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c index 528ec7cc9a62..5eb3d135b717 100644 --- a/arch/riscv/kernel/stacktrace.c +++ b/arch/riscv/kernel/stacktrace.c @@ -16,7 +16,7 @@ =20 #ifdef CONFIG_FRAME_POINTER =20 -extern asmlinkage void ret_from_exception(void); +extern asmlinkage void handle_exception(void); =20 static inline int fp_is_valid(unsigned long fp, unsigned long sp) { @@ -70,7 +70,7 @@ void notrace walk_stackframe(struct task_struct *task, st= ruct pt_regs *regs, fp =3D frame->fp; pc =3D ftrace_graph_ret_addr(current, NULL, frame->ra, &frame->ra); - if (pc =3D=3D (unsigned long)ret_from_exception) { + if (pc =3D=3D (unsigned long)handle_exception) { if (unlikely(!__kernel_text_address(pc) || !fn(arg, pc))) break; =20 --=20 2.43.0 From nobody Wed Dec 17 04:08:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3C643C463 for ; Sun, 16 Jun 2024 17:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558391; cv=none; b=ZCDvInTK6yR9JwMC2lQUP68dzMdo3Z6EixxjlRjO5Q2Zaqsth/JJ9TkT5ZyxgsqCUxYW2JE/qBYtVPAuNzUoJg/uWoXKIyyM13PTqAcuYaqV4jzIH9l9jyoIAt9aAWBH2+QvtaW5fii3G2eO36C8lhvNjpusEBGP+1jQ6J4aswQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558391; c=relaxed/simple; bh=4oPVcX+dnWixdoqxyDdXAghWvga3v3Kc2JLR+Blj82Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bCnymvElhepqA/rNXTAwJLTTLpQf3tdJNjYT7BU+lPurRnWLHmjeuLhpgzQ0aKJY8YP9Fl0h51dHQRgxPCUS3MUEIKEjgNZCDf2VyCtkcAgcIm9K8+6j/PrucxvusJjOgI3QVCWitJmtg6s7zDFajGqYv9SxS+N/0+PDt/H0LL0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CLiRO/PQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CLiRO/PQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2520EC4AF49; Sun, 16 Jun 2024 17:19:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718558391; bh=4oPVcX+dnWixdoqxyDdXAghWvga3v3Kc2JLR+Blj82Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CLiRO/PQh7a2ZWQyfdC4US0mVkLlJ6HO5eO2UarMxrnSElqTkb/0AS8JgQyaCPhsb f6Rnisd+06F259/wK4wls00MfcNsQl7NQV+Mhfnv88IgCcvrGU3EWPRqLTVQk7dVYB aSa1Ei/lYBm1EJcUUArXAUixCItAFX3YYfgToXU01t7FQ5c3d5eN5w5k0PhprfrDfz EtwdhL3f2ERamE7jYlaP9xncBE9/iJy0AMReS0P4PhkD7Tf12bJtFn1GRiJrMvsBcd 78n1RdSgzcAUv2HGdJF9Lu3B/cxSeuKOnUwNtjb8Z0Wd/djOm7Effpd6bH3OtDgeL1 peEGAE0Ub3qjQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] riscv: avoid corrupting the RAS Date: Mon, 17 Jun 2024 01:05:49 +0800 Message-ID: <20240616170553.2832-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org> References: <20240616170553.2832-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Inspired by[1], "modifying the return address of to point to ret_from_exception will corrupt the RAS", so modify the code to remove the code of modifying ra. Link: https://lore.kernel.org/linux-riscv/20240607061335.2197383-1-cyrilbur= @tenstorrent.com/ [1] Signed-off-by: Jisheng Zhang Reviewed-by: Cyril Bur --- arch/riscv/kernel/entry.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index c933460ed3e9..81dec627a8d4 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -235,8 +235,8 @@ SYM_CODE_START(ret_from_fork) jalr s0 1: move a0, sp /* pt_regs */ - la ra, ret_from_exception - tail syscall_exit_to_user_mode + call syscall_exit_to_user_mode + j ret_from_exception SYM_CODE_END(ret_from_fork) =20 #ifdef CONFIG_IRQ_STACKS --=20 2.43.0 From nobody Wed Dec 17 04:08:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 720B445C06 for ; Sun, 16 Jun 2024 17:19:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558393; cv=none; b=AleBBNmPfPkFA4/WO4z+8z9zFna37HLes29OPVRSVWCgL4TrYR3if7ijhPtT+AqbUD/xdeM9fYr2+CcKhISDMzy0j2YfCLrBb4rYy4CFudHcjDzHXE90G75jSnXcrT79d8siI7avrZTNfcA98hVQvF+FLSzGI2FK9Ue5DKSvYv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558393; c=relaxed/simple; bh=GWMgLDQITN6G/SgojfiKfA5r96nCPGSRhztDXhr7EXg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oMmsg026LF1vDWBaa+i7dnsGoKjM9iTeO55Z8L/1AmpXEGyjnIBPALtMfvmdqTZUFGeTBI+tpPW6kgWljYPuDxvQ5g9msUCjABEMpvoYIarYIE+YAR/OLD6+Pl0J6gqA05hH9zA/OVy82Y078mRyLvWTo7vZdRM2mrNdOIkHhB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pubyM0DI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pubyM0DI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6860C2BBFC; Sun, 16 Jun 2024 17:19:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718558392; bh=GWMgLDQITN6G/SgojfiKfA5r96nCPGSRhztDXhr7EXg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pubyM0DIUZ2FCQSzmiNj1L8bu3Px5o4jQOjivg6VvzHYBLOBK+GAN+Y/OxViI9qb3 eMmgyrw3DTZ+eAyvZDhDpXIt0M/y43/Vr7MmMJm3qlJuSkriq15i2r/AibavOeSCLs j1hXWIJgOU3Hn7ZY2d3Qa/vy0RZms6WZ80eVxn2JIkupnFFgWXVPPciVCLC9tJNuaF 3gse+dPBzhMruTEiABitxR+vr/P1kPbfbV/14Wg8ep+oX5HAXFZ/mF8MwO858yZ1U1 iKZhqNJXb1xuRDzL4e1EfLe2FhXv8WT4UnFqWWYTJfPxbdS/NbHniwDlIdYxvepvMd gazD/wXn3RCPg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] riscv: convert bottom half of exception handling to C Date: Mon, 17 Jun 2024 01:05:50 +0800 Message-ID: <20240616170553.2832-4-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org> References: <20240616170553.2832-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For readability, maintainability and future scalability, convert the bottom half of the exception handling to C. Mostly the assembly code is converted to C in a relatively straightforward manner. However, there are two modifications I need to mention: 1. the CSR_CAUSE reg reading and saving is moved to the C code because we need the cause to dispatch the exception handling, if we keep the cause reading and saving, we either pass it to do_traps() via. 2nd param or get it from pt_regs which an extra memory load is needed, I don't like any of the two solutions becase the exception handling sits in hot code path, every instruction matters. 2.To cope with SIFIVE_CIP_453 errata, it looks like we don't need alternative mechanism any more after the asm->c convertion. Just replace the excp_vect_table two entries. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/sifive/errata.c | 25 ++++++++--- arch/riscv/include/asm/asm-prototypes.h | 1 + arch/riscv/include/asm/errata_list.h | 5 +-- arch/riscv/kernel/entry.S | 58 +------------------------ arch/riscv/kernel/traps.c | 41 +++++++++++++++++ 5 files changed, 64 insertions(+), 66 deletions(-) diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/e= rrata.c index 716cfedad3a2..bbba99f207ca 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -10,9 +10,14 @@ #include #include #include +#include #include #include =20 +extern void (*excp_vect_table[])(struct pt_regs *regs); +extern void sifive_cip_453_insn_fault_trp(struct pt_regs *regs); +extern void sifive_cip_453_page_fault_trp(struct pt_regs *regs); + struct errata_info_t { char name[32]; bool (*check_func)(unsigned long arch_id, unsigned long impid); @@ -20,6 +25,9 @@ struct errata_info_t { =20 static bool errata_cip_453_check_func(unsigned long arch_id, unsigned lon= g impid) { + if (!IS_ENABLED(CONFIG_ERRATA_SIFIVE_CIP_453)) + return false; + /* * Affected cores: * Architecture ID: 0x8000000000000007 @@ -51,10 +59,6 @@ static bool errata_cip_1200_check_func(unsigned long ar= ch_id, unsigned long imp } =20 static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] =3D { - { - .name =3D "cip-453", - .check_func =3D errata_cip_453_check_func - }, { .name =3D "cip-1200", .check_func =3D errata_cip_1200_check_func @@ -62,11 +66,20 @@ static struct errata_info_t errata_list[ERRATA_SIFIVE_N= UMBER] =3D { }; =20 static u32 __init_or_module sifive_errata_probe(unsigned long archid, - unsigned long impid) + unsigned long impid, + unsigned int stage) { int idx; u32 cpu_req_errata =3D 0; =20 + if (stage =3D=3D RISCV_ALTERNATIVES_BOOT) { + if (IS_ENABLED(CONFIG_MMU) && + errata_cip_453_check_func(archid, impid)) { + excp_vect_table[EXC_INST_ACCESS] =3D sifive_cip_453_insn_fault_trp; + excp_vect_table[EXC_INST_PAGE_FAULT] =3D sifive_cip_453_page_fault_trp; + } + } + for (idx =3D 0; idx < ERRATA_SIFIVE_NUMBER; idx++) if (errata_list[idx].check_func(archid, impid)) cpu_req_errata |=3D (1U << idx); @@ -99,7 +112,7 @@ void sifive_errata_patch_func(struct alt_entry *begin, s= truct alt_entry *end, if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return; =20 - cpu_req_errata =3D sifive_errata_probe(archid, impid); + cpu_req_errata =3D sifive_errata_probe(archid, impid, stage); =20 for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D SIFIVE_VENDOR_ID) diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/a= sm/asm-prototypes.h index cd627ec289f1..81a1f27fa54f 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -55,5 +55,6 @@ DECLARE_DO_ERROR_INFO(do_trap_break); asmlinkage void handle_bad_stack(struct pt_regs *regs); asmlinkage void do_page_fault(struct pt_regs *regs); asmlinkage void do_irq(struct pt_regs *regs); +asmlinkage void do_traps(struct pt_regs *regs); =20 #endif /* _ASM_RISCV_PROTOTYPES_H */ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 7c8a71a526a3..95b79afc4061 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -17,9 +17,8 @@ #endif =20 #ifdef CONFIG_ERRATA_SIFIVE -#define ERRATA_SIFIVE_CIP_453 0 -#define ERRATA_SIFIVE_CIP_1200 1 -#define ERRATA_SIFIVE_NUMBER 2 +#define ERRATA_SIFIVE_CIP_1200 0 +#define ERRATA_SIFIVE_NUMBER 1 #endif =20 #ifdef CONFIG_ERRATA_THEAD diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 81dec627a8d4..401bfe85a098 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -62,13 +62,11 @@ SYM_CODE_START(handle_exception) csrrc s1, CSR_STATUS, t0 csrr s2, CSR_EPC csrr s3, CSR_TVAL - csrr s4, CSR_CAUSE csrr s5, CSR_SCRATCH REG_S s0, PT_SP(sp) REG_S s1, PT_STATUS(sp) REG_S s2, PT_EPC(sp) REG_S s3, PT_BADADDR(sp) - REG_S s4, PT_CAUSE(sp) REG_S s5, PT_TP(sp) =20 /* @@ -83,36 +81,9 @@ SYM_CODE_START(handle_exception) /* Load the kernel shadow call stack pointer if coming from userspace */ scs_load_current_if_task_changed s5 =20 -#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE - move a0, sp - call riscv_v_context_nesting_start -#endif move a0, sp /* pt_regs */ - - /* - * MSB of cause differentiates between - * interrupts and exceptions - */ - bge s4, zero, 1f - - /* Handle interrupts */ - call do_irq - j ret_from_exception -1: - /* Handle other exceptions */ - slli t0, s4, RISCV_LGPTR - la t1, excp_vect_table - la t2, excp_vect_table_end - add t0, t1, t0 - /* Check if exception code lies within bounds */ - bgeu t0, t2, 3f - REG_L t1, 0(t0) -2: jalr t1 + call do_traps j ret_from_exception -3: - - la t1, do_trap_unknown - j 2b SYM_CODE_END(handle_exception) ASM_NOKPROBE(handle_exception) =20 @@ -329,33 +300,6 @@ SYM_FUNC_START(__switch_to) ret SYM_FUNC_END(__switch_to) =20 -#ifndef CONFIG_MMU -#define do_page_fault do_trap_unknown -#endif - - .section ".rodata" - .align LGREG - /* Exception vector table */ -SYM_DATA_START_LOCAL(excp_vect_table) - RISCV_PTR do_trap_insn_misaligned - ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault) - RISCV_PTR do_trap_insn_illegal - RISCV_PTR do_trap_break - RISCV_PTR do_trap_load_misaligned - RISCV_PTR do_trap_load_fault - RISCV_PTR do_trap_store_misaligned - RISCV_PTR do_trap_store_fault - RISCV_PTR do_trap_ecall_u /* system call */ - RISCV_PTR do_trap_ecall_s - RISCV_PTR do_trap_unknown - RISCV_PTR do_trap_ecall_m - /* instruciton page fault */ - ALT_PAGE_FAULT(RISCV_PTR do_page_fault) - RISCV_PTR do_page_fault /* load page fault */ - RISCV_PTR do_trap_unknown - RISCV_PTR do_page_fault /* store page fault */ -SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) - #ifndef CONFIG_MMU SYM_DATA_START(__user_rt_sigreturn) li a7, __NR_rt_sigreturn diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 05a16b1f0aee..b44d4a8d4083 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -390,6 +390,47 @@ asmlinkage void noinstr do_irq(struct pt_regs *regs) irqentry_exit(regs, state); } =20 +void (*excp_vect_table[])(struct pt_regs *regs) __ro_after_init =3D { + do_trap_insn_misaligned, /* 0 Instruction address misaligned */ + do_trap_insn_fault, /* 1 Instruction access fault */ + do_trap_insn_illegal, /* 2 Illegal instruction */ + do_trap_break, /* 3 Breakpoint */ + do_trap_load_misaligned, /* 4 Load address misaligned */ + do_trap_load_fault, /* 5 Load access fault */ + do_trap_store_misaligned, /* 6 Store/AMO address misaligned */ + do_trap_store_fault, /* 7 Store/AMO access fault */ + do_trap_ecall_u, /* 8 Environment call from U-mode */ + do_trap_ecall_s, /* 9 Environment call from S-mode */ + do_trap_unknown, /* 10 Reserved */ + do_trap_ecall_m, /* 11 Environment call from M-mode */ +#ifdef CONFIG_MMU + do_page_fault, /* 12 Instruciton page fault */ + do_page_fault, /* 13 Load page fault */ + do_trap_unknown, /* 14 Reserved */ + do_page_fault, /* 15 Store/AMO page fault */ +#endif +}; + +asmlinkage void noinstr do_traps(struct pt_regs *regs) +{ + unsigned long cause =3D csr_read(CSR_CAUSE); + + regs->cause =3D cause; + +#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE + riscv_v_context_nesting_start(regs); +#endif + if (cause & CAUSE_IRQ_FLAG) { + do_irq(regs); + } else { + if (cause >=3D ARRAY_SIZE(excp_vect_table)) { + do_trap_unknown(regs); + return; + } + excp_vect_table[cause](regs); + } +} + #ifdef CONFIG_GENERIC_BUG int is_valid_bugaddr(unsigned long pc) { --=20 2.43.0 From nobody Wed Dec 17 04:08:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0453F49646 for ; Sun, 16 Jun 2024 17:19:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558395; cv=none; b=sYRMcKTt8msJQ/AYlj5hJaxOOmpgkq5v+5fC9IpgloxxZ6mYbsbqGR9kaecAfVGyRxTqqTcjidLC1nAeBuXKB+v+tZQPiNbyXcRRZ0fWInsv7EcoKFDPBDQLkAQqsJQxbLiifHr3CraD69fvCh+A+KjMdZZyFOpIHuqKDD/3q7Q= ARC-Message-Signature: i=1; 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b=CG3p5u4oEXwi4LuMzZozu/wQCsY1FuA8N3QqG0uHG4qD7kLca5oO47qirIA2bhT80 GyKDJmvRW2JhYloosJEDu4SVcxE96dd58uHRFDfm1Ke8IkI746Ba1HR88CCNDtCk5F yUdOaMDW2vOOGCrMI/aB4rBkLFLbCLdn+iwta83TFi39+xHcQmaP55sq4UvDR6JGsO frXhe+T2YJTUgWo+AXZYGuaZiG8yoDPc4gnLez5zqdsaRqzleAUi2HhhusDxUo/olF xcwCXw6XwkUmy7dgkKg7hiORh8qlOCojzYkBu78EIWaRQxHD6xs26+wTo7PeahMICD /lu8HwEyKiH0Q== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT Date: Mon, 17 Jun 2024 01:05:51 +0800 Message-ID: <20240616170553.2832-5-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org> References: <20240616170553.2832-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" They are used for SIFIVE_CIP_453 errata, which has been solved by replacing the excp_vect_table[] two entries in last commit. So these two macros are useless now, remove them. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/errata_list.h | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 95b79afc4061..46bf00c4a57a 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -27,21 +27,7 @@ #define ERRATA_THEAD_NUMBER 2 #endif =20 -#ifdef __ASSEMBLY__ - -#define ALT_INSN_FAULT(x) \ -ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ - __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ - SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ - CONFIG_ERRATA_SIFIVE_CIP_453) - -#define ALT_PAGE_FAULT(x) \ -ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ - __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ - SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ - CONFIG_ERRATA_SIFIVE_CIP_453) -#else /* !__ASSEMBLY__ */ - +#ifndef __ASSEMBLY__ #define ALT_SFENCE_VMA_ASID(asid) \ asm(ALTERNATIVE("sfence.vma x0, %0", "sfence.vma", SIFIVE_VENDOR_ID, \ ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ --=20 2.43.0 From nobody Wed Dec 17 04:08:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 402C84D9E9 for ; Sun, 16 Jun 2024 17:19:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558396; cv=none; b=ny8tabAvFmw3ZyL7IOqQa+M1IX7WCU3wBh8ZrOlsuoBkdr6c3wZO2X10Am/29VrCJ9fJP2rA2S0m6qjjeUiPdfVNweDI1F8F/qI7Ql7ZQVhsDqmIzt6kQ2ADsFegIr9m3TvgGWXiDHVKPsZraXyiHQe6d/eA1vJ9+u0OmnMpVY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558396; c=relaxed/simple; bh=JTbryNQs3nlw2UfEZXAy4glezWuH4wHardbP1B5eZro=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZXT1KSer2UbzXPAGLRIXyMskyEBQvdErVGYb8YxY8O9NUcSkGDOinccuC3jky2X7Dj0tFH2kiv+jcJxqmkqVSGu6I0uVTv2ga9s3CWXLD1r1rndb1ngcf+cDcgwKmnd6pWmbhRZtRkfy28YlzyA66CPGJlwv6VJTmemNglFEZSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e99AMxUM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e99AMxUM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5881C2BBFC; Sun, 16 Jun 2024 17:19:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718558396; bh=JTbryNQs3nlw2UfEZXAy4glezWuH4wHardbP1B5eZro=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e99AMxUM9kqsk1t0nkcvTWNSEsgH6QZvI3eAUpWIeocexioI8utlOu/CtuwLtruR7 tBp4cKdcU1Qg342P8QdqXloB6M9c72CcfxnTnmSs9YlpVgrAyGrDzof6koi/JShE/w qLDsLQcAiRUiALnFGnHMvbmClqfRsfFIEYWKhiKx25TtBMrUJEhnJkna7+RwS0IUKz ZgC6NMvelvB4vc0zRy5fPm1HNpjuVMRSkZea8CSrm51cyxFejc24SuBBx9fI+7XqfW PM+KdOqalP85orqXsTvsdGQXylQca65rqllQUOFAY8YPC28ucr3gLIAE1LhlAvEIsD or0dwW7jW6BFQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] riscv: errata: sifive: remove NOMMU handling Date: Mon, 17 Jun 2024 01:05:52 +0800 Message-ID: <20240616170553.2832-6-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org> References: <20240616170553.2832-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since NOMMU is now properly handling in generic do_traps() which will call do_trap_unknown() for instruciton page fault for NOMMU. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/sifive/errata_cip_453.S | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/errata/sifive/errata_cip_453.S b/arch/riscv/errata/= sifive/errata_cip_453.S index f1b9623fe1de..b8ca2ebc2652 100644 --- a/arch/riscv/errata/sifive/errata_cip_453.S +++ b/arch/riscv/errata/sifive/errata_cip_453.S @@ -23,11 +23,7 @@ =20 ENTRY(sifive_cip_453_page_fault_trp) ADD_SIGN_EXT a0, t0, t1 -#ifdef CONFIG_MMU la t0, do_page_fault -#else - la t0, do_trap_unknown -#endif jr t0 END(sifive_cip_453_page_fault_trp) =20 --=20 2.43.0 From nobody Wed Dec 17 04:08:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA8B660269 for ; Sun, 16 Jun 2024 17:19:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558397; cv=none; b=M/IOfto61JCmiuM4RpDRYpu4aLwnsj3fJeLUqhy11VAFGMkvKqd2/5wxTfE5hCFnSRhD56vPrYnx3S0IVdm8cARHfea3XhbeZpU0b9Ztrl6Q7rMOA91BoQojiNMIUZkjWQJyDa9KInjdLBf2F+yFUHVAMO+tow3l+D1ctVmAHW8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718558397; c=relaxed/simple; bh=E3GXEIZD9yn8wjrqGOzrCdvgMio8fL8UM/D6vQXKlWo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ejxeKVa8xlEt9KTy5a2sZKi13Fw5FApMfo2EyvDHJnIyQjIcoINoA9XDl8hzGMn8IJuTWtX2Jnaaj1BBw3vB56mOPN+N/E4Gi5x30VBJ+0Yjk+qqQaXhZeffwX3hLNU23ImlaUzZsWxQ8rUX921xcDC/ek3JHEgnt+u1dqPDDnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qMToKE0f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qMToKE0f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 81587C4AF4D; Sun, 16 Jun 2024 17:19:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718558397; bh=E3GXEIZD9yn8wjrqGOzrCdvgMio8fL8UM/D6vQXKlWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qMToKE0fdCNS9u9oH3qr8ZrWlxfAlYo0h0NIawg2WKdqHq7P0ptMQCHq4PMX0+qnR A6hc2daFhj2lvMPafkx6EfsLRX6X4ycBeMofZ0Xyohq4lMTJp9T8yhT6JNN9b2Crlo 0xcn7yW8+ApwXbnC42MxyfrXPbi9KZQ8e5T5sTotRSH9bnI6+8y1Sc4XsJZU9wZVed qLFJTr+mkMm9B1hYHu/eCZ5yEaS+msrYvc1XR3+TRaofVH7adIPR/+PxOIEO3xt1oL W3okdmcySYO/JjHSzgiit1EjiVBV5gyUwm711EXhnl040rKgqi26+Zzy9kf2Jf22s1 Xqo0an8m8DQHw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] riscv: remove asmlinkage from updated functions Date: Mon, 17 Jun 2024 01:05:53 +0800 Message-ID: <20240616170553.2832-7-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org> References: <20240616170553.2832-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the callers of these functions have moved into C, they no longer need the asmlinkage annotation. Remove it Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/asm-prototypes.h | 6 +++--- arch/riscv/kernel/traps.c | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/a= sm/asm-prototypes.h index 81a1f27fa54f..70b86a825922 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -37,7 +37,7 @@ asmlinkage void riscv_v_context_nesting_end(struct pt_reg= s *regs); =20 #endif /* CONFIG_RISCV_ISA_V */ =20 -#define DECLARE_DO_ERROR_INFO(name) asmlinkage void name(struct pt_regs *r= egs) +#define DECLARE_DO_ERROR_INFO(name) void name(struct pt_regs *regs) =20 DECLARE_DO_ERROR_INFO(do_trap_unknown); DECLARE_DO_ERROR_INFO(do_trap_insn_misaligned); @@ -53,8 +53,8 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_m); DECLARE_DO_ERROR_INFO(do_trap_break); =20 asmlinkage void handle_bad_stack(struct pt_regs *regs); -asmlinkage void do_page_fault(struct pt_regs *regs); -asmlinkage void do_irq(struct pt_regs *regs); +void do_page_fault(struct pt_regs *regs); +void do_irq(struct pt_regs *regs); asmlinkage void do_traps(struct pt_regs *regs); =20 #endif /* _ASM_RISCV_PROTOTYPES_H */ diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index b44d4a8d4083..ddca8e74fb72 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -147,7 +147,7 @@ static void do_trap_error(struct pt_regs *regs, int sig= no, int code, #define __trap_section noinstr #endif #define DO_ERROR_INFO(name, signo, code, str) \ -asmlinkage __visible __trap_section void name(struct pt_regs *regs) \ +__visible __trap_section void name(struct pt_regs *regs) \ { \ if (user_mode(regs)) { \ irqentry_enter_from_user_mode(regs); \ @@ -167,7 +167,7 @@ DO_ERROR_INFO(do_trap_insn_misaligned, DO_ERROR_INFO(do_trap_insn_fault, SIGSEGV, SEGV_ACCERR, "instruction access fault"); =20 -asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_re= gs *regs) +__visible __trap_section void do_trap_insn_illegal(struct pt_regs *regs) { bool handled; =20 @@ -198,7 +198,7 @@ asmlinkage __visible __trap_section void do_trap_insn_i= llegal(struct pt_regs *re DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); =20 -asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt= _regs *regs) +__visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -219,7 +219,7 @@ asmlinkage __visible __trap_section void do_trap_load_m= isaligned(struct pt_regs } } =20 -asmlinkage __visible __trap_section void do_trap_store_misaligned(struct p= t_regs *regs) +__visible __trap_section void do_trap_store_misaligned(struct pt_regs *reg= s) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -294,7 +294,7 @@ void handle_break(struct pt_regs *regs) die(regs, "Kernel BUG"); } =20 -asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *reg= s) +__visible __trap_section void do_trap_break(struct pt_regs *regs) { if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); @@ -311,7 +311,7 @@ asmlinkage __visible __trap_section void do_trap_break(= struct pt_regs *regs) } } =20 -asmlinkage __visible __trap_section __no_stack_protector +__visible __trap_section __no_stack_protector void do_trap_ecall_u(struct pt_regs *regs) { if (user_mode(regs)) { @@ -355,7 +355,7 @@ void do_trap_ecall_u(struct pt_regs *regs) } =20 #ifdef CONFIG_MMU -asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) +__visible noinstr void do_page_fault(struct pt_regs *regs) { irqentry_state_t state =3D irqentry_enter(regs); =20 @@ -378,7 +378,7 @@ static void noinstr handle_riscv_irq(struct pt_regs *re= gs) irq_exit_rcu(); } =20 -asmlinkage void noinstr do_irq(struct pt_regs *regs) +void noinstr do_irq(struct pt_regs *regs) { irqentry_state_t state =3D irqentry_enter(regs); =20 --=20 2.43.0