From nobody Fri Sep 20 01:27:39 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8876A186E36 for ; Sun, 16 Jun 2024 08:29:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718526555; cv=none; b=XGUqhJkYVeeosixxNizZk0tiPiL75kofvJS0Y2mDH2D3p9bgPxGBZeRZ7s5t6qmP9jHPeTLjuvBWK6KfNJKysi39Iu1oW/d1binfccPm3FR/w4D8uq7kozqqcgXfb8u57eznDLZLHobWHavD8UO4MThYw+PxQ4y+VFk9nCF+Gx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718526555; c=relaxed/simple; bh=u1Ec755SGAs2DOyCz8ZDHhB8uInkVMbjC8CrKq6pMlI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Yin27pbeFFLyX1DhekBtr8c+d73Ni8x1nvG8skqkFTAgfBeR7b3sV0TpQxTLqivwpaPSH8qPZRHdFin2G71l4tX/J+e5UxAoLAP5ufkHPXvOREzqYtQpwO9zo9xVt5bvwUQCqJxBQssIZsCGb/kJXH5/90e7RGTxEDWSE/jvc68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XTPSV1vh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XTPSV1vh" Received: by smtp.kernel.org (Postfix) with ESMTPS id 243E5C4AF54; Sun, 16 Jun 2024 08:29:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718526555; bh=u1Ec755SGAs2DOyCz8ZDHhB8uInkVMbjC8CrKq6pMlI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XTPSV1vhM1r24dixjMBsDQd+QjRgGkbSI22NSxdwVAoUS6dcjK01pdH17a7RT4fuk CAlFAi2fLJsrHYSeswFZzxFQaVzA296N6wqiwsZozWD9EmYCh04fmMwwp7MUr9BQ4P lFZR8lW8vICibl3caEUErusa59rCkQE/W1zEXRh/TcogplwSI0mnTDRudS6roddF2B WSDt29mizcplT+x86qaW2l9Is+v8sAhj96g7zgx4M94hTx8rSYQMHeeBnk4HomCQ3W Uo4vwSKg7IcefJ1xJIrirJOdEfTpoqumdNswleeq5FShCtFAzVe+InTm+mzwdiodzr DoLCCAAn5+HGA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A451C2BA16; Sun, 16 Jun 2024 08:29:15 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Sun, 16 Jun 2024 16:29:16 +0800 Subject: [PATCH 06/13] drm/mediatek: Turn off the layers with zero width or height Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240616-mediatek-drm-next-v1-6-7e8f9cf785d8@mediatek.com> References: <20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com> In-Reply-To: <20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718526553; l=2110; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=dqX2wm5YHxb4PcQ3tQ95rP0OPaABSh/HZP+kCxZYb/s=; b=rBv9L1sZHl5v2QITha1QsonEGs+CHt/5LjEOmGGhA4zq4fd/T5Fg2s86fr6o3Z8CqfcowF5og L1lA6ShbPNCAVdkfnsbWbj5wJKWF+2uVdMbzAyhEAeIYjg5FRruVtj7 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195") Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 02dd7dcdfedb..2b62d6475918 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index d7d16482c947..b5484a286060 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -159,7 +159,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (idx >=3D 4) return; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZ= E(idx)); return; } --=20 Git-146)