From nobody Fri Sep 20 01:38:25 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB16518628A for ; Sun, 16 Jun 2024 08:29:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718526555; cv=none; b=RkkqC7rA3tQdx8Iubz3GoV/p76El4xcwt1t51d4+FzlJNUBe9bmNmGWqFz1uqgS6/qGJf4Xc5AYuNT77gKjDiAf76c5KVUjYWdJgHbGGnIjP2hfe80oGOfY/T48qOBIldYUu0g26c7C3RmozcgkMKU7Ka3un/tFvKKWLucOCNKw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718526555; c=relaxed/simple; bh=HGD/YyvSyv29O14mwDPoDHHeYEPWb4sPouMX0i+8w4c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=akJxeHpLqWZKEmO9s69b3wWUmwNcBJRF/c6WK/1jq6achJ6usxJ0AumkQdXjZ2qqRgC2BIJcfrFuwsy9T42p7Jqd99gf3ox976BnAc5O6OmN06ZaMoe/bHgB39pBKdKuPb6drQ2Oe8v+HLgrsQZq/Z/9ZobMpRvbiLBkVtvawS0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OP3VLo3l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OP3VLo3l" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7784CC4DDE2; Sun, 16 Jun 2024 08:29:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718526555; bh=HGD/YyvSyv29O14mwDPoDHHeYEPWb4sPouMX0i+8w4c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OP3VLo3l89iU4AYRBL585fnhDMdllV8vziZ5yJEvrI4Bp/jwe+Jp05dfpdCCx7gAQ eBEdHvVcDoH3DK48OFmPGlY+2lQDcN0xsK7YXoGi2ifKiSYPxmnDK/B/qqBgdqpDx9 XYFLN0U7AIYuYL+AEZwwlr28lvskkggzDYTcMtb7iMeFnPLn9kqDjBYKUub5zNK2e+ IQUbDXJXI/0tUPTJbQK+rf033dVmIrGWjfGJECglNgcdYnyG0JHsJq529F57HZcbon cia40tNdQN5fqF6Z+k4Rm01wZQo33KBpjas3UFHvEI/Zqc1XIs7n+CMHdKNEddTLA2 vdEHFj/K3tmRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EBE9C27C77; Sun, 16 Jun 2024 08:29:15 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Sun, 16 Jun 2024 16:29:22 +0800 Subject: [PATCH 12/13] drm/mediatek: Support DRM plane alpha in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240616-mediatek-drm-next-v1-12-7e8f9cf785d8@mediatek.com> References: <20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com> In-Reply-To: <20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu , Bibby Hsieh , Daniel Kurtz , YT Shen , Mao Huang , "Nancy.Lin" Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718526553; l=991; i=shawn.sung@mediatek.com; s=20240616; h=from:subject:message-id; bh=5BJt05q2olOJLyH/qGdDD53kmjnnoM3hvSVC/ZouM1A=; b=jCZ7lXGpv+AGtyowVT4z9RF57ghEL/4IapUmjqVDC/g1vyfBCShi0WXvzHVqwsGRGhY5JtcuO otzo4pze4POBtP+gxqYbkHSwA7//1+jksNg8PKDBFkHGUP+A3bEX0p9 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=lq1w8BuWDINX+4JHjGHhhbAU5ICP+cL9VCj7wn+cEDA= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240616 with auth_id=172 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Set the plane alpha according to DRM plane property. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 33b58da15ba4..f358dbfed5e3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -450,8 +450,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, } =20 con =3D ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |=3D OVL_CON_AEN | OVL_CON_ALPHA; + if (state->base.fb) { + con |=3D OVL_CON_AEN; + con |=3D state->base.alpha & OVL_CON_ALPHA; + } =20 /* CONST_BLD must be enabled for XRGB formats although the alpha channel * can be ignored, or OVL will still read the value from memory. --=20 Git-146)