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Downing" , Arnd Bergmann , Chancel Liu , Michael Ellerman , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v3 1/4] ASoC: dt-bindings: lpc32xx: Add lpc32xx i2s DT binding Date: Fri, 14 Jun 2024 18:34:49 +0200 Message-Id: <20240614163500.386747-2-piotr.wojtaszczyk@timesys.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> References: <20240611094810.27475-1-piotr.wojtaszczyk@timesys.com> <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nxp,lpc3220-i2s DT binding documentation. Signed-off-by: Piotr Wojtaszczyk --- Changes for v3: - Added '$ref: dai-common.yaml#' and '#sound-dai-cells' - Dropped all clock-names, references - Dropped status property from the example - Added interrupts property - 'make dt_binding_check' pass Changes for v2: - Added maintainers field - Dropped clock-names - Dropped unused unneded interrupts field .../bindings/sound/nxp,lpc3220-i2s.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/nxp,lpc3220-i2s= .yaml diff --git a/Documentation/devicetree/bindings/sound/nxp,lpc3220-i2s.yaml b= /Documentation/devicetree/bindings/sound/nxp,lpc3220-i2s.yaml new file mode 100644 index 000000000000..04a1090f70cc --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nxp,lpc3220-i2s.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/nxp,lpc3220-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32XX I2S Controller + +description: + The I2S controller in LPC32XX SoCs, ASoC DAI. + +maintainers: + - J.M.B. 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Fri, 14 Jun 2024 09:35:52 -0700 (PDT) Received: from localhost.localdomain ([91.216.213.152]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cb72da156sm2462893a12.22.2024.06.14.09.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 09:35:51 -0700 (PDT) From: Piotr Wojtaszczyk To: Cc: Piotr Wojtaszczyk , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Zapolskiy , Russell King , Jaroslav Kysela , Takashi Iwai , "J.M.B. Downing" , Michael Ellerman , Chancel Liu , Arnd Bergmann , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v3 2/4] ARM: dts: lpc32xx: Add missing properties for the i2s interfaces Date: Fri, 14 Jun 2024 18:34:50 +0200 Message-Id: <20240614163500.386747-3-piotr.wojtaszczyk@timesys.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> References: <20240611094810.27475-1-piotr.wojtaszczyk@timesys.com> <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 'dma-vc-names' correspond to virtual pl08x dma channels declared in the 'phy3250.c' platform file. Signed-off-by: Piotr Wojtaszczyk --- Changes for v3: - Split previous commit for separate subsystems - Add properties to match dt binding arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp= /lpc/lpc32xx.dtsi index 974410918f35..bbd2b8b6963c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -221,6 +221,10 @@ spi2: spi@20090000 { i2s0: i2s@20094000 { compatible =3D "nxp,lpc3220-i2s"; reg =3D <0x20094000 0x1000>; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk LPC32XX_CLK_I2S0>; + dma-vc-names =3D "i2s0-tx", "i2s0-rx"; + #sound-dai-cells =3D <0>; status =3D "disabled"; }; =20 @@ -237,6 +241,10 @@ sd: sd@20098000 { i2s1: i2s@2009c000 { compatible =3D "nxp,lpc3220-i2s"; reg =3D <0x2009c000 0x1000>; + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk LPC32XX_CLK_I2S1>; + dma-vc-names =3D "i2s1-tx", "i2s1-rx"; + #sound-dai-cells =3D <0>; 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Downing" , Chancel Liu , Michael Ellerman , Arnd Bergmann , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v3 3/4] ARM: lpc32xx: Add pl08x virtual dma channels for spi and i2s Date: Fri, 14 Jun 2024 18:34:51 +0200 Message-Id: <20240614163500.386747-4-piotr.wojtaszczyk@timesys.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> References: <20240611094810.27475-1-piotr.wojtaszczyk@timesys.com> <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some of the signals are multiplexed, multiplexer configured at a signal request. Signed-off-by: Piotr Wojtaszczyk --- Changes for v3: - Split previous commit for separate subsystems - Add pl08x virtual dma channels for i2s1 - Add dma mux handling, required when requesting tx dma signal for i2s1 arch/arm/mach-lpc32xx/phy3250.c | 111 +++++++++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy325= 0.c index 5371bfaed799..2ec0411964f9 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -9,14 +9,18 @@ */ =20 #include +#include #include #include #include +#include =20 #include #include "common.h" #include "lpc32xx.h" =20 +static DEFINE_SPINLOCK(lpc32xx_pl08x_lock); + static struct pl08x_channel_data pl08x_slave_channels[] =3D { { .bus_id =3D "nand-slc", @@ -30,11 +34,97 @@ static struct pl08x_channel_data pl08x_slave_channels[]= =3D { .max_signal =3D 12, .periph_buses =3D PL08X_AHB1, }, + { + .bus_id =3D "i2s0-tx", + .min_signal =3D 13, + .max_signal =3D 13, + .periph_buses =3D PL08X_AHB1, + }, + { + .bus_id =3D "i2s0-rx", + .min_signal =3D 0, + .max_signal =3D 0, + .periph_buses =3D PL08X_AHB1, + }, + { + .bus_id =3D "i2s1-tx", + .min_signal =3D 10, + .max_signal =3D 10, + .muxval =3D 1, + .periph_buses =3D PL08X_AHB1, + }, + { + .bus_id =3D "i2s1-rx", + .min_signal =3D 2, + .max_signal =3D 2, + .periph_buses =3D PL08X_AHB1, + }, + { + .bus_id =3D "ssp0-tx", + .min_signal =3D 15, + .max_signal =3D 15, + .muxval =3D 1, + .periph_buses =3D PL08X_AHB1, + }, + { + .bus_id =3D "ssp0-rx", + .min_signal =3D 14, + .max_signal =3D 14, + .muxval =3D 1, + .periph_buses =3D PL08X_AHB1, + }, + { + .bus_id =3D "ssp1-tx", + .min_signal =3D 11, + .max_signal =3D 11, + .muxval =3D 1, + .periph_buses =3D PL08X_AHB1, + }, + { + .bus_id =3D "ssp1-rx", + .min_signal =3D 3, + .max_signal =3D 3, + .muxval =3D 1, + .periph_buses =3D PL08X_AHB1, + }, +}; + +struct lpc32xx_pl08x_mux { + int signal; + void __iomem *addr; + int bit; +}; + +/* From LPC32x0 User manual "3.2.1 DMA request signals" */ +static const struct lpc32xx_pl08x_mux dma_mux[] =3D { + {3, LPC32XX_CLKPWR_SSP_CLK_CTRL, 5}, + {10, LPC32XX_CLKPWR_I2S_CLK_CTRL, 4}, + {11, LPC32XX_CLKPWR_SSP_CLK_CTRL, 4}, + {14, LPC32XX_CLKPWR_SSP_CLK_CTRL, 3}, + {15, LPC32XX_CLKPWR_SSP_CLK_CTRL, 2}, }; =20 static int pl08x_get_signal(const struct pl08x_channel_data *cd) { - return cd->min_signal; + const int signal =3D cd->min_signal; + unsigned long flags; + int i, tmp; + + /* Set corresponding dma mux bit if muxed */ + for (i =3D 0; i < ARRAY_SIZE(dma_mux); i++) { + if (dma_mux[i].signal =3D=3D signal) { + spin_lock_irqsave(&lpc32xx_pl08x_lock, flags); + tmp =3D __raw_readl(dma_mux[i].addr); + if (cd->muxval) + tmp |=3D BIT(dma_mux[i].bit); + else + tmp &=3D ~BIT(dma_mux[i].bit); + __raw_writel(tmp, dma_mux[i].addr); + spin_unlock_irqrestore(&lpc32xx_pl08x_lock, flags); + break; + } + } + return signal; } =20 static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) @@ -61,12 +151,31 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_da= ta =3D { .dma_filter =3D pl08x_filter_id, }; =20 +static struct pl022_ssp_controller lpc32xx_ssp_data[] =3D { + { + .bus_id =3D 0, + .enable_dma =3D 0, + .dma_filter =3D pl08x_filter_id, + .dma_tx_param =3D "ssp0-tx", + .dma_rx_param =3D "ssp0-rx", + }, + { + .bus_id =3D 1, + .enable_dma =3D 0, + .dma_filter =3D pl08x_filter_id, + .dma_tx_param =3D "ssp1-tx", + .dma_rx_param =3D "ssp1-rx", + } +}; + static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = =3D { OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash", &lpc32xx_slc_data), OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash", &lpc32xx_mlc_data), + OF_DEV_AUXDATA("arm,pl022", 0x20084000, NULL, &lpc32xx_ssp_data[0]), + OF_DEV_AUXDATA("arm,pl022", 0x2008c000, NULL, &lpc32xx_ssp_data[1]), { } }; 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Downing" , Chancel Liu , Michael Ellerman , Arnd Bergmann , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v3 4/4] ASoC: fsl: Add i2s and pcm drivers for LPC32xx CPUs Date: Fri, 14 Jun 2024 18:34:52 +0200 Message-Id: <20240614163500.386747-5-piotr.wojtaszczyk@timesys.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> References: <20240611094810.27475-1-piotr.wojtaszczyk@timesys.com> <20240614163500.386747-1-piotr.wojtaszczyk@timesys.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This driver was ported from an old version in linux 2.6.27 and adjusted for the new ASoC framework and DMA API. Signed-off-by: Piotr Wojtaszczyk --- Changes for v3: - Split previous commit for separate subsystems - Add support and as a maintainer for the dri= ver - Replaced `SND_SOC` config dependency with COMPILE_TEST - Moved `snd-soc-fsl-lpc3xxx-y` in Makefile up in the list to maintain alfa= bedical order - Changed comment to c++ format - replaced custom absd32() with standard abs() function - Added clock provider check in lpc3xxx_i2s_set_dai_fmt() - Removed empty lpc32xx_i2s_remove() function - Reworked i2s regs definitions to include LPC3XXX prefix - Replaced custom _BIT, _SBD with standard BIT and FIELD_PREP macros Changes for v2: - Coding Style cleanup - Use dev_err_probe() for error handling in probe function - Removed unneded err_clk_disable label - Removed empty function - Droped of_match_ptr in lpc32xx_i2s_match DT match table - ASoC struct adjustmes for the latest 6.10-rc3 kernel MAINTAINERS | 8 + sound/soc/fsl/Kconfig | 7 + sound/soc/fsl/Makefile | 2 + sound/soc/fsl/lpc3xxx-i2s.c | 393 ++++++++++++++++++++++++++++++++++++ sound/soc/fsl/lpc3xxx-i2s.h | 79 ++++++++ sound/soc/fsl/lpc3xxx-pcm.c | 74 +++++++ 6 files changed, 563 insertions(+) create mode 100644 sound/soc/fsl/lpc3xxx-i2s.c create mode 100644 sound/soc/fsl/lpc3xxx-i2s.h create mode 100644 sound/soc/fsl/lpc3xxx-pcm.c diff --git a/MAINTAINERS b/MAINTAINERS index aacccb376c28..9789c1e4e291 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8909,6 +8909,14 @@ S: Maintained F: sound/soc/fsl/fsl* F: sound/soc/fsl/imx* =20 +FREESCALE SOC LPC32XX SOUND DRIVERS +M: J.M.B. Downing +M: Piotr Wojtaszczyk +L: alsa-devel@alsa-project.org (moderated for non-subscribers) +L: linuxppc-dev@lists.ozlabs.org +S: Maintained +F: sound/soc/fsl/lpc3xxx-* + FREESCALE SOC SOUND QMC DRIVER M: Herve Codina L: alsa-devel@alsa-project.org (moderated for non-subscribers) diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index acadec3e8947..839a35214acb 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -136,6 +136,13 @@ config SND_SOC_FSL_RPMSG This option is only useful for out-of-tree drivers since in-tree drivers select it automatically. =20 +config SND_SOC_FSL_LPC3XXX + tristate "SoC Audio for NXP LPC32XX CPUs" + depends on ARCH_LPC32XX || COMPILE_TEST + select SND_SOC_GENERIC_DMAENGINE_PCM + help + Say Y or M if you want to add support for the LPC3XXX I2S interface. + config SND_SOC_IMX_PCM_DMA tristate select SND_SOC_GENERIC_DMAENGINE_PCM diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile index 550d1e3aced1..7b1ca557e953 100644 --- a/sound/soc/fsl/Makefile +++ b/sound/soc/fsl/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) +=3D snd-soc-p1022-rdk.o snd-soc-fsl-audmix-y :=3D fsl_audmix.o snd-soc-fsl-asoc-card-y :=3D fsl-asoc-card.o snd-soc-fsl-asrc-y :=3D fsl_asrc.o fsl_asrc_dma.o +snd-soc-fsl-lpc3xxx-y :=3D lpc3xxx-pcm.o lpc3xxx-i2s.o snd-soc-fsl-sai-y :=3D fsl_sai.o snd-soc-fsl-ssi-y :=3D fsl_ssi.o snd-soc-fsl-ssi-$(CONFIG_DEBUG_FS) +=3D fsl_ssi_dbg.o @@ -30,6 +31,7 @@ snd-soc-fsl-qmc-audio-y :=3D fsl_qmc_audio.o obj-$(CONFIG_SND_SOC_FSL_AUDMIX) +=3D snd-soc-fsl-audmix.o obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) +=3D snd-soc-fsl-asoc-card.o obj-$(CONFIG_SND_SOC_FSL_ASRC) +=3D snd-soc-fsl-asrc.o +obj-$(CONFIG_SND_SOC_FSL_LPC3XXX) +=3D snd-soc-fsl-lpc3xxx.o obj-$(CONFIG_SND_SOC_FSL_SAI) +=3D snd-soc-fsl-sai.o obj-$(CONFIG_SND_SOC_FSL_SSI) +=3D snd-soc-fsl-ssi.o obj-$(CONFIG_SND_SOC_FSL_SPDIF) +=3D snd-soc-fsl-spdif.o diff --git a/sound/soc/fsl/lpc3xxx-i2s.c b/sound/soc/fsl/lpc3xxx-i2s.c new file mode 100644 index 000000000000..480e1e8deded --- /dev/null +++ b/sound/soc/fsl/lpc3xxx-i2s.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// +// Author: Kevin Wells +// +// Copyright (C) 2008 NXP Semiconductors +// Copyright 2023 Timesys Corporation + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "lpc3xxx-i2s.h" + +#define I2S_PLAYBACK_FLAG 0x1 +#define I2S_CAPTURE_FLAG 0x2 + +#define LPC3XXX_I2S_RATES ( \ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000) + +#define LPC3XXX_I2S_FORMATS ( \ + SNDRV_PCM_FMTBIT_S8 | \ + SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static void __lpc3xxx_find_clkdiv(u32 *clkx, u32 *clky, int freq, int xbyt= es, u32 clkrate) +{ + u32 i2srate; + u32 idxx, idyy; + u32 savedbitclkrate, diff, trate, baseclk; + + /* Adjust rate for sample size (bits) and 2 channels and offset for + * divider in clock output + */ + i2srate =3D (freq / 100) * 2 * (8 * xbytes); + i2srate =3D i2srate << 1; + clkrate =3D clkrate / 100; + baseclk =3D clkrate; + *clkx =3D 1; + *clky =3D 1; + + /* Find the best divider */ + *clkx =3D *clky =3D 0; + savedbitclkrate =3D 0; + diff =3D ~0; + for (idxx =3D 1; idxx < 0xFF; idxx++) { + for (idyy =3D 1; idyy < 0xFF; idyy++) { + trate =3D (baseclk * idxx) / idyy; + if (abs(trate - i2srate) < diff) { + diff =3D abs(trate - i2srate); + savedbitclkrate =3D trate; + *clkx =3D idxx; + *clky =3D idyy; + } + } + } +} + +static int lpc3xxx_i2s_startup(struct snd_pcm_substream *substream, struct= snd_soc_dai *cpu_dai) +{ + struct lpc3xxx_i2s_info *i2s_info_p =3D snd_soc_dai_get_drvdata(cpu_dai); + struct device *dev =3D i2s_info_p->dev; + u32 flag; + int ret =3D 0; + + mutex_lock(&i2s_info_p->lock); + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) + flag =3D I2S_PLAYBACK_FLAG; + else + flag =3D I2S_CAPTURE_FLAG; + + if (flag & i2s_info_p->streams_in_use) { + dev_warn(dev, "I2S channel is busy\n"); + ret =3D -EBUSY; + goto lpc32xx_unlock; + } + + if (i2s_info_p->streams_in_use =3D=3D 0) { + ret =3D clk_prepare_enable(i2s_info_p->clk); + if (ret) { + dev_err(dev, "Can't enable clock, err=3D%d\n", ret); + goto lpc32xx_unlock; + } + } + + i2s_info_p->streams_in_use |=3D flag; + +lpc32xx_unlock: + mutex_unlock(&i2s_info_p->lock); + return ret; +} + +static void lpc3xxx_i2s_shutdown(struct snd_pcm_substream *substream, stru= ct snd_soc_dai *cpu_dai) +{ + struct lpc3xxx_i2s_info *i2s_info_p =3D snd_soc_dai_get_drvdata(cpu_dai); + struct regmap *regs =3D i2s_info_p->regs; + const u32 stop_bits =3D (LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP); + u32 flag; + + mutex_lock(&i2s_info_p->lock); + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + flag =3D I2S_PLAYBACK_FLAG; + regmap_write(regs, LPC3XXX_REG_I2S_TX_RATE, 0); + regmap_update_bits(regs, LPC3XXX_REG_I2S_DAO, stop_bits, stop_bits); + } else { + flag =3D I2S_CAPTURE_FLAG; + regmap_write(regs, LPC3XXX_REG_I2S_RX_RATE, 0); + regmap_update_bits(regs, LPC3XXX_REG_I2S_DAI, stop_bits, stop_bits); + } + i2s_info_p->streams_in_use &=3D ~flag; + + if (i2s_info_p->streams_in_use =3D=3D 0) + clk_disable_unprepare(i2s_info_p->clk); + + mutex_unlock(&i2s_info_p->lock); +} + +static int lpc3xxx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai, + int clk_id, unsigned int freq, int dir) +{ + struct lpc3xxx_i2s_info *i2s_info_p =3D snd_soc_dai_get_drvdata(cpu_dai); + + /* Will use in HW params later */ + i2s_info_p->freq =3D freq; + + return 0; +} + +static int lpc3xxx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned i= nt fmt) +{ + struct lpc3xxx_i2s_info *i2s_info_p =3D snd_soc_dai_get_drvdata(cpu_dai); + struct device *dev =3D i2s_info_p->dev; + + if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) !=3D SND_SOC_DAIFMT_I2S) { + dev_warn(dev, "unsupported bus format %d\n", fmt); + return -EINVAL; + } + + if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) !=3D SND_SOC_DAIFMT_BP_FP)= { + dev_warn(dev, "unsupported clock provider %d\n", fmt); + return -EINVAL; + } + + return 0; +} + +static int lpc3xxx_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + struct lpc3xxx_i2s_info *i2s_info_p =3D snd_soc_dai_get_drvdata(cpu_dai); + struct device *dev =3D i2s_info_p->dev; + struct regmap *regs =3D i2s_info_p->regs; + int xfersize; + u32 tmp, clkx, clky; + + tmp =3D LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S8: + tmp |=3D LPC3XXX_I2S_WW8 | LPC3XXX_I2S_WS_HP(LPC3XXX_I2S_WW8_HP); + xfersize =3D 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + tmp |=3D LPC3XXX_I2S_WW16 | LPC3XXX_I2S_WS_HP(LPC3XXX_I2S_WW16_HP); + xfersize =3D 2; + break; + + case SNDRV_PCM_FORMAT_S32_LE: + tmp |=3D LPC3XXX_I2S_WW32 | LPC3XXX_I2S_WS_HP(LPC3XXX_I2S_WW32_HP); + xfersize =3D 4; + break; + + default: + dev_warn(dev, "Unsupported audio data format %d\n", params_format(params= )); + return -EINVAL; + } + + if (params_channels(params) =3D=3D 1) + tmp |=3D LPC3XXX_I2S_MONO; + + __lpc3xxx_find_clkdiv(&clkx, &clky, i2s_info_p->freq, xfersize, i2s_info_= p->clkrate); + + dev_dbg(dev, "Stream : %s\n", + substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK ? "playback" : "captu= re"); + dev_dbg(dev, "Desired clock rate : %d\n", i2s_info_p->freq); + dev_dbg(dev, "Base clock rate : %d\n", i2s_info_p->clkrate); + dev_dbg(dev, "Transfer size (bytes) : %d\n", xfersize); + dev_dbg(dev, "Clock divider (x) : %d\n", clkx); + dev_dbg(dev, "Clock divider (y) : %d\n", clky); + dev_dbg(dev, "Channels : %d\n", params_channels(params)); + dev_dbg(dev, "Data format : %s\n", "I2S"); + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + regmap_write(regs, LPC3XXX_REG_I2S_DMA1, + LPC3XXX_I2S_DMA1_TX_EN | LPC3XXX_I2S_DMA0_TX_DEPTH(4)); + regmap_write(regs, LPC3XXX_REG_I2S_TX_RATE, (clkx << 8) | clky); + regmap_write(regs, LPC3XXX_REG_I2S_DAO, tmp); + } else { + regmap_write(regs, LPC3XXX_REG_I2S_DMA0, + LPC3XXX_I2S_DMA0_RX_EN | LPC3XXX_I2S_DMA1_RX_DEPTH(4)); + regmap_write(regs, LPC3XXX_REG_I2S_RX_RATE, (clkx << 8) | clky); + regmap_write(regs, LPC3XXX_REG_I2S_DAI, tmp); + } + + return 0; +} + +static int lpc3xxx_i2s_trigger(struct snd_pcm_substream *substream, int cm= d, + struct snd_soc_dai *cpu_dai) +{ + struct lpc3xxx_i2s_info *i2s_info_p =3D snd_soc_dai_get_drvdata(cpu_dai); + struct regmap *regs =3D i2s_info_p->regs; + int ret =3D 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + case SNDRV_PCM_TRIGGER_SUSPEND: + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) + regmap_update_bits(regs, LPC3XXX_REG_I2S_DAO, + LPC3XXX_I2S_STOP, LPC3XXX_I2S_STOP); + else + regmap_update_bits(regs, LPC3XXX_REG_I2S_DAI, + LPC3XXX_I2S_STOP, LPC3XXX_I2S_STOP); + break; + + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_RESUME: + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) + regmap_update_bits(regs, LPC3XXX_REG_I2S_DAO, + (LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP), 0); + else + regmap_update_bits(regs, LPC3XXX_REG_I2S_DAI, + (LPC3XXX_I2S_RESET | LPC3XXX_I2S_STOP), 0); + break; + default: + ret =3D -EINVAL; + } + + return ret; +} + +static int lpc3xxx_i2s_dai_probe(struct snd_soc_dai *dai) +{ + struct lpc3xxx_i2s_info *i2s_info_p =3D snd_soc_dai_get_drvdata(dai); + + snd_soc_dai_init_dma_data(dai, &i2s_info_p->playback_dma_config, + &i2s_info_p->capture_dma_config); + return 0; +} + +const struct snd_soc_dai_ops lpc3xxx_i2s_dai_ops =3D { + .probe =3D lpc3xxx_i2s_dai_probe, + .startup =3D lpc3xxx_i2s_startup, + .shutdown =3D lpc3xxx_i2s_shutdown, + .trigger =3D lpc3xxx_i2s_trigger, + .hw_params =3D lpc3xxx_i2s_hw_params, + .set_sysclk =3D lpc3xxx_i2s_set_dai_sysclk, + .set_fmt =3D lpc3xxx_i2s_set_dai_fmt, +}; + +struct snd_soc_dai_driver lpc3xxx_i2s_dai_driver =3D { + .playback =3D { + .channels_min =3D 1, + .channels_max =3D 2, + .rates =3D LPC3XXX_I2S_RATES, + .formats =3D LPC3XXX_I2S_FORMATS, + }, + .capture =3D { + .channels_min =3D 1, + .channels_max =3D 2, + .rates =3D LPC3XXX_I2S_RATES, + .formats =3D LPC3XXX_I2S_FORMATS, + }, + .ops =3D &lpc3xxx_i2s_dai_ops, + .symmetric_rate =3D 1, + .symmetric_channels =3D 1, + .symmetric_sample_bits =3D 1, +}; + +static const struct snd_soc_component_driver lpc32xx_i2s_component =3D { + .name =3D "lpc32xx-i2s", + .legacy_dai_naming =3D 1, +}; + +static const struct regmap_config lpc32xx_i2s_regconfig =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D LPC3XXX_REG_I2S_RX_RATE, +}; + +static int lpc32xx_i2s_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct lpc3xxx_i2s_info *i2s_info_p; + struct resource *res; + void __iomem *iomem; + const char *filter_data; + int ret; + + i2s_info_p =3D devm_kzalloc(dev, sizeof(*i2s_info_p), GFP_KERNEL); + if (!i2s_info_p) + return -ENOMEM; + + platform_set_drvdata(pdev, i2s_info_p); + i2s_info_p->dev =3D dev; + + iomem =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(iomem)) + return dev_err_probe(dev, PTR_ERR(iomem), "Can't map registers\n"); + + i2s_info_p->regs =3D devm_regmap_init_mmio(dev, iomem, &lpc32xx_i2s_regco= nfig); + if (IS_ERR(i2s_info_p->regs)) + return dev_err_probe(dev, PTR_ERR(i2s_info_p->regs), + "failed to init register map: %d\n", ret); + + i2s_info_p->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(i2s_info_p->clk)) + return dev_err_probe(dev, PTR_ERR(i2s_info_p->clk), "Can't get clock\n"); + + i2s_info_p->clkrate =3D clk_get_rate(i2s_info_p->clk); + if (i2s_info_p->clkrate =3D=3D 0) + return dev_err_probe(dev, -EINVAL, "Invalid returned clock rate\n"); + + ret =3D of_property_count_strings(dev->of_node, "dma-vc-names"); + if (ret !=3D 2) + return dev_err_probe(dev, -EINVAL, "Requires two 'dma-vc-names' entries\= n"); + + mutex_init(&i2s_info_p->lock); + + ret =3D devm_snd_soc_register_component(dev, &lpc32xx_i2s_component, + &lpc3xxx_i2s_dai_driver, 1); + if (ret) + return dev_err_probe(dev, ret, "Can't register cpu_dai component\n"); + + i2s_info_p->playback_dma_config.addr =3D (dma_addr_t)(res->start + LPC3XX= X_REG_I2S_TX_FIFO); + i2s_info_p->playback_dma_config.maxburst =3D 4; + ret =3D of_property_read_string_index(dev->of_node, "dma-vc-names", 0, &f= ilter_data); + if (ret) + return dev_err_probe(dev, ret, "Can't get tx virtual dma channel\n"); + i2s_info_p->playback_dma_config.filter_data =3D (void *)filter_data; + + i2s_info_p->capture_dma_config.addr =3D (dma_addr_t)(res->start + LPC3XXX= _REG_I2S_RX_FIFO); + i2s_info_p->capture_dma_config.maxburst =3D 4; + ret =3D of_property_read_string_index(dev->of_node, "dma-vc-names", 1, &f= ilter_data); + if (ret) + return dev_err_probe(dev, ret, "Can't get rx virtual dma channel\n"); + i2s_info_p->capture_dma_config.filter_data =3D (void *)filter_data; + + ret =3D lpc3xxx_pcm_register(pdev); + if (ret) + return dev_err_probe(dev, ret, "Can't register pcm component\n"); + + return 0; +} + +static const struct of_device_id lpc32xx_i2s_match[] =3D { + { .compatible =3D "nxp,lpc3220-i2s" }, + {}, +}; +MODULE_DEVICE_TABLE(of, lpc32xx_i2s_match); + +static struct platform_driver lpc32xx_i2s_driver =3D { + .probe =3D lpc32xx_i2s_probe, + .driver =3D { + .name =3D "lpc3xxx-i2s", + .of_match_table =3D lpc32xx_i2s_match, + }, +}; + +module_platform_driver(lpc32xx_i2s_driver); + +MODULE_AUTHOR("Kevin Wells "); +MODULE_AUTHOR("Piotr Wojtaszczyk "); +MODULE_DESCRIPTION("ASoC LPC3XXX I2S interface"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/fsl/lpc3xxx-i2s.h b/sound/soc/fsl/lpc3xxx-i2s.h new file mode 100644 index 000000000000..eec755448478 --- /dev/null +++ b/sound/soc/fsl/lpc3xxx-i2s.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Author: Kevin Wells + * + * Copyright (C) 2008 NXP Semiconductors + * Copyright 2023 Timesys Corporation + */ + +#ifndef __SOUND_SOC_LPC3XXX_I2S_H +#define __SOUND_SOC_LPC3XXX_I2S_H + +#include +#include + +struct lpc3xxx_i2s_info { + struct device *dev; + struct clk *clk; + struct mutex lock; /* To serialize user-space access */ + struct regmap *regs; + u32 streams_in_use; + u32 clkrate; + int freq; + struct snd_dmaengine_dai_dma_data playback_dma_config; + struct snd_dmaengine_dai_dma_data capture_dma_config; +}; + +int lpc3xxx_pcm_register(struct platform_device *pdev); + +/* I2S controller register offsets */ +#define LPC3XXX_REG_I2S_DAO 0x00 +#define LPC3XXX_REG_I2S_DAI 0x04 +#define LPC3XXX_REG_I2S_TX_FIFO 0x08 +#define LPC3XXX_REG_I2S_RX_FIFO 0x0C +#define LPC3XXX_REG_I2S_STAT 0x10 +#define LPC3XXX_REG_I2S_DMA0 0x14 +#define LPC3XXX_REG_I2S_DMA1 0x18 +#define LPC3XXX_REG_I2S_IRQ 0x1C +#define LPC3XXX_REG_I2S_TX_RATE 0x20 +#define LPC3XXX_REG_I2S_RX_RATE 0x24 + +/* i2s_daO i2s_dai register definitions */ +#define LPC3XXX_I2S_WW8 FIELD_PREP(0x3, 0) /* Word width is 8bit */ +#define LPC3XXX_I2S_WW16 FIELD_PREP(0x3, 1) /* Word width is 16bit */ +#define LPC3XXX_I2S_WW32 FIELD_PREP(0x3, 3) /* Word width is 32bit */ +#define LPC3XXX_I2S_MONO BIT(2) /* Mono */ +#define LPC3XXX_I2S_STOP BIT(3) /* Stop, diables the access to FIFO,= mutes the channel */ +#define LPC3XXX_I2S_RESET BIT(4) /* Reset the channel */ +#define LPC3XXX_I2S_WS_SEL BIT(5) /* Channel Master(0) or slave(1) mod= e select */ +#define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half per= iod - 1 */ +#define LPC3XXX_I2S_MUTE BIT(15) /* Mute the channel, Transmit channe= l only */ + +#define LPC3XXX_I2S_WW32_HP 0x1f /* Word select half period for 32bit wor= d width */ +#define LPC3XXX_I2S_WW16_HP 0x0f /* Word select half period for 16bit wor= d width */ +#define LPC3XXX_I2S_WW8_HP 0x7 /* Word select half period for 8bit word= width */ + +/* i2s_stat register definitions */ +#define LPC3XXX_I2S_IRQ_STAT BIT(0) +#define LPC3XXX_I2S_DMA0_REQ BIT(1) +#define LPC3XXX_I2S_DMA1_REQ BIT(2) + +/* i2s_dma0 Configuration register definitions */ +#define LPC3XXX_I2S_DMA0_RX_EN BIT(0) /* Enable RX DMA1 */ +#define LPC3XXX_I2S_DMA0_TX_EN BIT(1) /* Enable TX DMA1 */ +#define LPC3XXX_I2S_DMA0_RX_DEPTH(s) FIELD_PREP(0xF00, s) /* Set the DMA1= RX Request level */ +#define LPC3XXX_I2S_DMA0_TX_DEPTH(s) FIELD_PREP(0xF0000, s) /* Set the DMA= 1 TX Request level */ + +/* i2s_dma1 Configuration register definitions */ +#define LPC3XXX_I2S_DMA1_RX_EN BIT(0) /* Enable RX DMA1 */ +#define LPC3XXX_I2S_DMA1_TX_EN BIT(1) /* Enable TX DMA1 */ +#define LPC3XXX_I2S_DMA1_RX_DEPTH(s) FIELD_PREP(0x700, s) /* Set the DMA1 = RX Request level */ +#define LPC3XXX_I2S_DMA1_TX_DEPTH(s) FIELD_PREP(0x70000, s) /* Set the DMA= 1 TX Request level */ + +/* i2s_irq register definitions */ +#define LPC3XXX_I2S_RX_IRQ_EN BIT(0) /* Enable RX IRQ */ +#define LPC3XXX_I2S_TX_IRQ_EN BIT(1) /* Enable TX IRQ */ +#define LPC3XXX_I2S_IRQ_RX_DEPTH(s) FIELD_PREP(0xFF00, s) /* valid value= s ar 0 to 7 */ +#define LPC3XXX_I2S_IRQ_TX_DEPTH(s) FIELD_PREP(0xFF0000, s) /* valid valu= es ar 0 to 7 */ + +#endif diff --git a/sound/soc/fsl/lpc3xxx-pcm.c b/sound/soc/fsl/lpc3xxx-pcm.c new file mode 100644 index 000000000000..59d64cae4e05 --- /dev/null +++ b/sound/soc/fsl/lpc3xxx-pcm.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// +// Author: Kevin Wells +// +// Copyright (C) 2008 NXP Semiconductors +// Copyright 2023 Timesys Corporation + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "lpc3xxx-i2s.h" + +#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ + SNDRV_PCM_FMTBIT_U8 | \ + SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_U16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_U24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE | \ + SNDRV_PCM_FMTBIT_U32_LE | \ + SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE) + +static const struct snd_pcm_hardware lpc3xxx_pcm_hardware =3D { + .info =3D (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME), + .formats =3D STUB_FORMATS, + .period_bytes_min =3D 128, + .period_bytes_max =3D 2048, + .periods_min =3D 2, + .periods_max =3D 1024, + .buffer_bytes_max =3D 128 * 1024 +}; + +static const struct snd_dmaengine_pcm_config lpc3xxx_dmaengine_pcm_config = =3D { + .pcm_hardware =3D &lpc3xxx_pcm_hardware, + .prepare_slave_config =3D snd_dmaengine_pcm_prepare_slave_config, + .compat_filter_fn =3D pl08x_filter_id, + .prealloc_buffer_size =3D 128 * 1024, +}; + +const struct snd_soc_component_driver lpc3xxx_soc_platform_driver =3D { + .name =3D "lpc32xx-pcm", +}; + +int lpc3xxx_pcm_register(struct platform_device *pdev) +{ + int ret; + int flags; + + flags =3D SND_DMAENGINE_PCM_FLAG_NO_DT | SND_DMAENGINE_PCM_FLAG_COMPAT; + ret =3D devm_snd_dmaengine_pcm_register(&pdev->dev, &lpc3xxx_dmaengine_pc= m_config, flags); + if (ret) { + dev_err(&pdev->dev, "failed to register dmaengine: %d\n", ret); + return ret; + } + + return devm_snd_soc_register_component(&pdev->dev, &lpc3xxx_soc_platform_= driver, + NULL, 0); +} +EXPORT_SYMBOL(lpc3xxx_pcm_register); --=20 2.25.1