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charset="utf-8" Content-Transfer-Encoding: quoted-printable Currently, the init_code of the jd9365da driver is placed in the enable() function and sent, but this seems to take a long time. It takes 17ms to send each instruction (an init code consists of about 200 instructions), so it takes about 3.5s to send the init_code. So we moved the sending of the inti_code to the prepare() function, and each instruction seemed to take only 25=CE=BCs. Signed-off-by: Zhaoxiong Lv --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 781 +++++++++--------- 1 file changed, 393 insertions(+), 388 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu= /drm/panel/panel-jadard-jd9365da-h3.c index 4879835fe101..b39f01d7002e 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -19,17 +19,13 @@ #include #include =20 -#define JD9365DA_INIT_CMD_LEN 2 - -struct jadard_init_cmd { - u8 data[JD9365DA_INIT_CMD_LEN]; -}; +struct jadard; =20 struct jadard_panel_desc { const struct drm_display_mode mode; unsigned int lanes; enum mipi_dsi_pixel_format format; - const struct jadard_init_cmd *init_cmds; + int (*init)(struct jadard *jadard); u32 num_init_cmds; }; =20 @@ -52,21 +48,9 @@ static int jadard_enable(struct drm_panel *panel) { struct device *dev =3D panel->dev; struct jadard *jadard =3D panel_to_jadard(panel); - const struct jadard_panel_desc *desc =3D jadard->desc; struct mipi_dsi_device *dsi =3D jadard->dsi; - unsigned int i; int err; =20 - msleep(10); - - for (i =3D 0; i < desc->num_init_cmds; i++) { - const struct jadard_init_cmd *cmd =3D &desc->init_cmds[i]; - - err =3D mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); - if (err < 0) - return err; - } - msleep(120); =20 err =3D mipi_dsi_dcs_exit_sleep_mode(dsi); @@ -117,9 +101,21 @@ static int jadard_prepare(struct drm_panel *panel) msleep(10); =20 gpiod_set_value(jadard->reset, 1); - msleep(120); + msleep(130); + + ret =3D jadard->desc->init(jadard); + if (ret < 0) + goto poweroff; =20 return 0; + +poweroff: + gpiod_set_value(jadard->reset, 0); + /* T6: 2ms */ + usleep_range(1000, 2000); + regulator_disable(jadard->vccio); + + return ret; } =20 static int jadard_unprepare(struct drm_panel *panel) @@ -167,176 +163,181 @@ static const struct drm_panel_funcs jadard_funcs = =3D { .get_modes =3D jadard_get_modes, }; =20 -static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = =3D { - { .data =3D { 0xE0, 0x00 } }, - { .data =3D { 0xE1, 0x93 } }, - { .data =3D { 0xE2, 0x65 } }, - { .data =3D { 0xE3, 0xF8 } }, - { .data =3D { 0x80, 0x03 } }, - { .data =3D { 0xE0, 0x01 } }, - { .data =3D { 0x00, 0x00 } }, - { .data =3D { 0x01, 0x7E } }, - { .data =3D { 0x03, 0x00 } }, - { .data =3D { 0x04, 0x65 } }, - { .data =3D { 0x0C, 0x74 } }, - { .data =3D { 0x17, 0x00 } }, - { .data =3D { 0x18, 0xB7 } }, - { .data =3D { 0x19, 0x00 } }, - { .data =3D { 0x1A, 0x00 } }, - { .data =3D { 0x1B, 0xB7 } }, - { .data =3D { 0x1C, 0x00 } }, - { .data =3D { 0x24, 0xFE } }, - { .data =3D { 0x37, 0x19 } }, - { .data =3D { 0x38, 0x05 } }, - { .data =3D { 0x39, 0x00 } }, - { .data =3D { 0x3A, 0x01 } }, - { .data =3D { 0x3B, 0x01 } }, - { .data =3D { 0x3C, 0x70 } }, - { .data =3D { 0x3D, 0xFF } }, - { .data =3D { 0x3E, 0xFF } }, - { .data =3D { 0x3F, 0xFF } }, - { .data =3D { 0x40, 0x06 } }, - { .data =3D { 0x41, 0xA0 } }, - { .data =3D { 0x43, 0x1E } }, - { .data =3D { 0x44, 0x0F } }, - { .data =3D { 0x45, 0x28 } }, - { .data =3D { 0x4B, 0x04 } }, - { .data =3D { 0x55, 0x02 } }, - { .data =3D { 0x56, 0x01 } }, - { .data =3D { 0x57, 0xA9 } }, - { .data =3D { 0x58, 0x0A } }, - { .data =3D { 0x59, 0x0A } }, - { .data =3D { 0x5A, 0x37 } }, - { .data =3D { 0x5B, 0x19 } }, - { .data =3D { 0x5D, 0x78 } }, - { .data =3D { 0x5E, 0x63 } }, - { .data =3D { 0x5F, 0x54 } }, - { .data =3D { 0x60, 0x49 } }, - { .data =3D { 0x61, 0x45 } }, - { .data =3D { 0x62, 0x38 } }, - { .data =3D { 0x63, 0x3D } }, - { .data =3D { 0x64, 0x28 } }, - { .data =3D { 0x65, 0x43 } }, - { .data =3D { 0x66, 0x41 } }, - { .data =3D { 0x67, 0x43 } }, - { .data =3D { 0x68, 0x62 } }, - { .data =3D { 0x69, 0x50 } }, - { .data =3D { 0x6A, 0x57 } }, - { .data =3D { 0x6B, 0x49 } }, - { .data =3D { 0x6C, 0x44 } }, - { .data =3D { 0x6D, 0x37 } }, - { .data =3D { 0x6E, 0x23 } }, - { .data =3D { 0x6F, 0x10 } }, - { .data =3D { 0x70, 0x78 } }, - { .data =3D { 0x71, 0x63 } }, - { .data =3D { 0x72, 0x54 } }, - { .data =3D { 0x73, 0x49 } }, - { .data =3D { 0x74, 0x45 } }, - { .data =3D { 0x75, 0x38 } }, - { .data =3D { 0x76, 0x3D } }, - { .data =3D { 0x77, 0x28 } }, - { .data =3D { 0x78, 0x43 } }, - { .data =3D { 0x79, 0x41 } }, - { .data =3D { 0x7A, 0x43 } }, - { .data =3D { 0x7B, 0x62 } }, - { .data =3D { 0x7C, 0x50 } }, - { .data =3D { 0x7D, 0x57 } }, - { .data =3D { 0x7E, 0x49 } }, - { .data =3D { 0x7F, 0x44 } }, - { .data =3D { 0x80, 0x37 } }, - { .data =3D { 0x81, 0x23 } }, - { .data =3D { 0x82, 0x10 } }, - { .data =3D { 0xE0, 0x02 } }, - { .data =3D { 0x00, 0x47 } }, - { .data =3D { 0x01, 0x47 } }, - { .data =3D { 0x02, 0x45 } }, - { .data =3D { 0x03, 0x45 } }, - { .data =3D { 0x04, 0x4B } }, - { .data =3D { 0x05, 0x4B } }, - { .data =3D { 0x06, 0x49 } }, - { .data =3D { 0x07, 0x49 } }, - { .data =3D { 0x08, 0x41 } }, - { .data =3D { 0x09, 0x1F } }, - { .data =3D { 0x0A, 0x1F } }, - { .data =3D { 0x0B, 0x1F } }, - { .data =3D { 0x0C, 0x1F } }, - { .data =3D { 0x0D, 0x1F } }, - { .data =3D { 0x0E, 0x1F } }, - { .data =3D { 0x0F, 0x5F } }, - { .data =3D { 0x10, 0x5F } }, - { .data =3D { 0x11, 0x57 } }, - { .data =3D { 0x12, 0x77 } }, - { .data =3D { 0x13, 0x35 } }, - { .data =3D { 0x14, 0x1F } }, - { .data =3D { 0x15, 0x1F } }, - { .data =3D { 0x16, 0x46 } }, - { .data =3D { 0x17, 0x46 } }, - { .data =3D { 0x18, 0x44 } }, - { .data =3D { 0x19, 0x44 } }, - { .data =3D { 0x1A, 0x4A } }, - { .data =3D { 0x1B, 0x4A } }, - { .data =3D { 0x1C, 0x48 } }, - { .data =3D { 0x1D, 0x48 } }, - { .data =3D { 0x1E, 0x40 } }, - { .data =3D { 0x1F, 0x1F } }, - { .data =3D { 0x20, 0x1F } }, - { .data =3D { 0x21, 0x1F } }, - { .data =3D { 0x22, 0x1F } }, - { .data =3D { 0x23, 0x1F } }, - { .data =3D { 0x24, 0x1F } }, - { .data =3D { 0x25, 0x5F } }, - { .data =3D { 0x26, 0x5F } }, - { .data =3D { 0x27, 0x57 } }, - { .data =3D { 0x28, 0x77 } }, - { .data =3D { 0x29, 0x35 } }, - { .data =3D { 0x2A, 0x1F } }, - { .data =3D { 0x2B, 0x1F } }, - { .data =3D { 0x58, 0x40 } }, - { .data =3D { 0x59, 0x00 } }, - { .data =3D { 0x5A, 0x00 } }, - { .data =3D { 0x5B, 0x10 } }, - { .data =3D { 0x5C, 0x06 } }, - { .data =3D { 0x5D, 0x40 } }, - { .data =3D { 0x5E, 0x01 } }, - { .data =3D { 0x5F, 0x02 } }, - { .data =3D { 0x60, 0x30 } }, - { .data =3D { 0x61, 0x01 } }, - { .data =3D { 0x62, 0x02 } }, - { .data =3D { 0x63, 0x03 } }, - { .data =3D { 0x64, 0x6B } }, - { .data =3D { 0x65, 0x05 } }, - { .data =3D { 0x66, 0x0C } }, - { .data =3D { 0x67, 0x73 } }, - { .data =3D { 0x68, 0x09 } }, - { .data =3D { 0x69, 0x03 } }, - { .data =3D { 0x6A, 0x56 } }, - { .data =3D { 0x6B, 0x08 } }, - { .data =3D { 0x6C, 0x00 } }, - { .data =3D { 0x6D, 0x04 } }, - { .data =3D { 0x6E, 0x04 } }, - { .data =3D { 0x6F, 0x88 } }, - { .data =3D { 0x70, 0x00 } }, - { .data =3D { 0x71, 0x00 } }, - { .data =3D { 0x72, 0x06 } }, - { .data =3D { 0x73, 0x7B } }, - { .data =3D { 0x74, 0x00 } }, - { .data =3D { 0x75, 0xF8 } }, - { .data =3D { 0x76, 0x00 } }, - { .data =3D { 0x77, 0xD5 } }, - { .data =3D { 0x78, 0x2E } }, - { .data =3D { 0x79, 0x12 } }, - { .data =3D { 0x7A, 0x03 } }, - { .data =3D { 0x7B, 0x00 } }, - { .data =3D { 0x7C, 0x00 } }, - { .data =3D { 0x7D, 0x03 } }, - { .data =3D { 0x7E, 0x7B } }, - { .data =3D { 0xE0, 0x04 } }, - { .data =3D { 0x00, 0x0E } }, - { .data =3D { 0x02, 0xB3 } }, - { .data =3D { 0x09, 0x60 } }, - { .data =3D { 0x0E, 0x2A } }, - { .data =3D { 0x36, 0x59 } }, - { .data =3D { 0xE0, 0x00 } }, +static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + + return 0; }; =20 static const struct jadard_panel_desc radxa_display_8hd_ad002_desc =3D { @@ -359,205 +360,209 @@ static const struct jadard_panel_desc radxa_display= _8hd_ad002_desc =3D { }, .lanes =3D 4, .format =3D MIPI_DSI_FMT_RGB888, - .init_cmds =3D radxa_display_8hd_ad002_init_cmds, - .num_init_cmds =3D ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds), + .init =3D radxa_display_8hd_ad002_init_cmds, }; =20 -static const struct jadard_init_cmd cz101b4001_init_cmds[] =3D { - { .data =3D { 0xE0, 0x00 } }, - { .data =3D { 0xE1, 0x93 } }, - { .data =3D { 0xE2, 0x65 } }, - { .data =3D { 0xE3, 0xF8 } }, - { .data =3D { 0x80, 0x03 } }, - { .data =3D { 0xE0, 0x01 } }, - { .data =3D { 0x00, 0x00 } }, - { .data =3D { 0x01, 0x3B } }, - { .data =3D { 0x0C, 0x74 } }, - { .data =3D { 0x17, 0x00 } }, - { .data =3D { 0x18, 0xAF } }, - { .data =3D { 0x19, 0x00 } }, - { .data =3D { 0x1A, 0x00 } }, - { .data =3D { 0x1B, 0xAF } }, - { .data =3D { 0x1C, 0x00 } }, - { .data =3D { 0x35, 0x26 } }, - { .data =3D { 0x37, 0x09 } }, - { .data =3D { 0x38, 0x04 } }, - { .data =3D { 0x39, 0x00 } }, - { .data =3D { 0x3A, 0x01 } }, - { .data =3D { 0x3C, 0x78 } }, - { .data =3D { 0x3D, 0xFF } }, - { .data =3D { 0x3E, 0xFF } }, - { .data =3D { 0x3F, 0x7F } }, - { .data =3D { 0x40, 0x06 } }, - { .data =3D { 0x41, 0xA0 } }, - { .data =3D { 0x42, 0x81 } }, - { .data =3D { 0x43, 0x14 } }, - { .data =3D { 0x44, 0x23 } }, - { .data =3D { 0x45, 0x28 } }, - { .data =3D { 0x55, 0x02 } }, - { .data =3D { 0x57, 0x69 } }, - { .data =3D { 0x59, 0x0A } }, - { .data =3D { 0x5A, 0x2A } }, - { .data =3D { 0x5B, 0x17 } }, - { .data =3D { 0x5D, 0x7F } }, - { .data =3D { 0x5E, 0x6B } }, - { .data =3D { 0x5F, 0x5C } }, - { .data =3D { 0x60, 0x4F } }, - { .data =3D { 0x61, 0x4D } }, - { .data =3D { 0x62, 0x3F } }, - { .data =3D { 0x63, 0x42 } }, - { .data =3D { 0x64, 0x2B } }, - { .data =3D { 0x65, 0x44 } }, - { .data =3D { 0x66, 0x43 } }, - { .data =3D { 0x67, 0x43 } }, - { .data =3D { 0x68, 0x63 } }, - { .data =3D { 0x69, 0x52 } }, - { .data =3D { 0x6A, 0x5A } }, - { .data =3D { 0x6B, 0x4F } }, - { .data =3D { 0x6C, 0x4E } }, - { .data =3D { 0x6D, 0x20 } }, - { .data =3D { 0x6E, 0x0F } }, - { .data =3D { 0x6F, 0x00 } }, - { .data =3D { 0x70, 0x7F } }, - { .data =3D { 0x71, 0x6B } }, - { .data =3D { 0x72, 0x5C } }, - { .data =3D { 0x73, 0x4F } }, - { .data =3D { 0x74, 0x4D } }, - { .data =3D { 0x75, 0x3F } }, - { .data =3D { 0x76, 0x42 } }, - { .data =3D { 0x77, 0x2B } }, - { .data =3D { 0x78, 0x44 } }, - { .data =3D { 0x79, 0x43 } }, - { .data =3D { 0x7A, 0x43 } }, - { .data =3D { 0x7B, 0x63 } }, - { .data =3D { 0x7C, 0x52 } }, - { .data =3D { 0x7D, 0x5A } }, - { .data =3D { 0x7E, 0x4F } }, - { .data =3D { 0x7F, 0x4E } }, - { .data =3D { 0x80, 0x20 } }, - { .data =3D { 0x81, 0x0F } }, - { .data =3D { 0x82, 0x00 } }, - { .data =3D { 0xE0, 0x02 } }, - { .data =3D { 0x00, 0x02 } }, - { .data =3D { 0x01, 0x02 } }, - { .data =3D { 0x02, 0x00 } }, - { .data =3D { 0x03, 0x00 } }, - { .data =3D { 0x04, 0x1E } }, - { .data =3D { 0x05, 0x1E } }, - { .data =3D { 0x06, 0x1F } }, - { .data =3D { 0x07, 0x1F } }, - { .data =3D { 0x08, 0x1F } }, - { .data =3D { 0x09, 0x17 } }, - { .data =3D { 0x0A, 0x17 } }, - { .data =3D { 0x0B, 0x37 } }, - { .data =3D { 0x0C, 0x37 } }, - { .data =3D { 0x0D, 0x47 } }, - { .data =3D { 0x0E, 0x47 } }, - { .data =3D { 0x0F, 0x45 } }, - { .data =3D { 0x10, 0x45 } }, - { .data =3D { 0x11, 0x4B } }, - { .data =3D { 0x12, 0x4B } }, - { .data =3D { 0x13, 0x49 } }, - { .data =3D { 0x14, 0x49 } }, - { .data =3D { 0x15, 0x1F } }, - { .data =3D { 0x16, 0x01 } }, - { .data =3D { 0x17, 0x01 } }, - { .data =3D { 0x18, 0x00 } }, - { .data =3D { 0x19, 0x00 } }, - { .data =3D { 0x1A, 0x1E } }, - { .data =3D { 0x1B, 0x1E } }, - { .data =3D { 0x1C, 0x1F } }, - { .data =3D { 0x1D, 0x1F } }, - { .data =3D { 0x1E, 0x1F } }, - { .data =3D { 0x1F, 0x17 } }, - { .data =3D { 0x20, 0x17 } }, - { .data =3D { 0x21, 0x37 } }, - { .data =3D { 0x22, 0x37 } }, - { .data =3D { 0x23, 0x46 } }, - { .data =3D { 0x24, 0x46 } }, - { .data =3D { 0x25, 0x44 } }, - { .data =3D { 0x26, 0x44 } }, - { .data =3D { 0x27, 0x4A } }, - { .data =3D { 0x28, 0x4A } }, - { .data =3D { 0x29, 0x48 } }, - { .data =3D { 0x2A, 0x48 } }, - { .data =3D { 0x2B, 0x1F } }, - { .data =3D { 0x2C, 0x01 } }, - { .data =3D { 0x2D, 0x01 } }, - { .data =3D { 0x2E, 0x00 } }, - { .data =3D { 0x2F, 0x00 } }, - { .data =3D { 0x30, 0x1F } }, - { .data =3D { 0x31, 0x1F } }, - { .data =3D { 0x32, 0x1E } }, - { .data =3D { 0x33, 0x1E } }, - { .data =3D { 0x34, 0x1F } }, - { .data =3D { 0x35, 0x17 } }, - { .data =3D { 0x36, 0x17 } }, - { .data =3D { 0x37, 0x37 } }, - { .data =3D { 0x38, 0x37 } }, - { .data =3D { 0x39, 0x08 } }, - { .data =3D { 0x3A, 0x08 } }, - { .data =3D { 0x3B, 0x0A } }, - { .data =3D { 0x3C, 0x0A } }, - { .data =3D { 0x3D, 0x04 } }, - { .data =3D { 0x3E, 0x04 } }, - { .data =3D { 0x3F, 0x06 } }, - { .data =3D { 0x40, 0x06 } }, - { .data =3D { 0x41, 0x1F } }, - { .data =3D { 0x42, 0x02 } }, - { .data =3D { 0x43, 0x02 } }, - { .data =3D { 0x44, 0x00 } }, - { .data =3D { 0x45, 0x00 } }, - { .data =3D { 0x46, 0x1F } }, - { .data =3D { 0x47, 0x1F } }, - { .data =3D { 0x48, 0x1E } }, - { .data =3D { 0x49, 0x1E } }, - { .data =3D { 0x4A, 0x1F } }, - { .data =3D { 0x4B, 0x17 } }, - { .data =3D { 0x4C, 0x17 } }, - { .data =3D { 0x4D, 0x37 } }, - { .data =3D { 0x4E, 0x37 } }, - { .data =3D { 0x4F, 0x09 } }, - { .data =3D { 0x50, 0x09 } }, - { .data =3D { 0x51, 0x0B } }, - { .data =3D { 0x52, 0x0B } }, - { .data =3D { 0x53, 0x05 } }, - { .data =3D { 0x54, 0x05 } }, - { .data =3D { 0x55, 0x07 } }, - { .data =3D { 0x56, 0x07 } }, - { .data =3D { 0x57, 0x1F } }, - { .data =3D { 0x58, 0x40 } }, - { .data =3D { 0x5B, 0x30 } }, - { .data =3D { 0x5C, 0x16 } }, - { .data =3D { 0x5D, 0x34 } }, - { .data =3D { 0x5E, 0x05 } }, - { .data =3D { 0x5F, 0x02 } }, - { .data =3D { 0x63, 0x00 } }, - { .data =3D { 0x64, 0x6A } }, - { .data =3D { 0x67, 0x73 } }, - { .data =3D { 0x68, 0x1D } }, - { .data =3D { 0x69, 0x08 } }, - { .data =3D { 0x6A, 0x6A } }, - { .data =3D { 0x6B, 0x08 } }, - { .data =3D { 0x6C, 0x00 } }, - { .data =3D { 0x6D, 0x00 } }, - { .data =3D { 0x6E, 0x00 } }, - { .data =3D { 0x6F, 0x88 } }, - { .data =3D { 0x75, 0xFF } }, - { .data =3D { 0x77, 0xDD } }, - { .data =3D { 0x78, 0x3F } }, - { .data =3D { 0x79, 0x15 } }, - { .data =3D { 0x7A, 0x17 } }, - { .data =3D { 0x7D, 0x14 } }, - { .data =3D { 0x7E, 0x82 } }, - { .data =3D { 0xE0, 0x04 } }, - { .data =3D { 0x00, 0x0E } }, - { .data =3D { 0x02, 0xB3 } }, - { .data =3D { 0x09, 0x61 } }, - { .data =3D { 0x0E, 0x48 } }, - { .data =3D { 0xE0, 0x00 } }, - { .data =3D { 0xE6, 0x02 } }, - { .data =3D { 0xE7, 0x0C } }, +static int cz101b4001_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xAF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xAF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x5C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x5A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x4E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x5A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x4E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x6A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xDD); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C); + + return 0; }; =20 static const struct jadard_panel_desc cz101b4001_desc =3D { @@ -580,8 +585,8 @@ static const struct jadard_panel_desc cz101b4001_desc = =3D { }, .lanes =3D 4, .format =3D MIPI_DSI_FMT_RGB888, - .init_cmds =3D cz101b4001_init_cmds, - .num_init_cmds =3D ARRAY_SIZE(cz101b4001_init_cmds), + .init =3D cz101b4001_init_cmds, + }; =20 static int jadard_dsi_probe(struct mipi_dsi_device *dsi) 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d9443c01a7336-1f869edd7c5mr19731945ad.53.1718376931373; Fri, 14 Jun 2024 07:55:31 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e739b7sm32914495ad.93.2024.06.14.07.55.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 07:55:30 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Date: Fri, 14 Jun 2024 22:55:08 +0800 Message-Id: <20240614145510.22965-3-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240614145510.22965-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240614145510.22965-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The kingdisplay-kd101ne3 is a 10.1" WXGA TFT-LCD panel with jadard-jd9365da controller. Hence, we add a new compatible with panel specific config. Signed-off-by: Zhaoxiong Lv --- Chage since V3: - 1. Abandon the V2 patch and add kingdisplay kd101ne3-40ti binding to=20 - jadard,jd9365da-h3.yaml again. V2:https://lore.kernel.org/all/20240601084528.22502-2-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Chage since V2: - Drop some properties that have already been defined in panel-common. - The header file 'dt-bindings/gpio/gpio.h' is not used, delete it V1: https://lore.kernel.org/all/20240418081548.12160-2-lvzhaoxiong@huaqin.c= orp-partner.google.com/ --- .../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365d= a-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da= -h3.yaml index 41eb7fbf7715..6138d853a15b 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.ya= ml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.ya= ml @@ -19,6 +19,7 @@ properties: - chongzhou,cz101b4001 - radxa,display-10hd-ad001 - radxa,display-8hd-ad002 + - kingdisplay,kd101ne3-40ti - const: jadard,jd9365da-h3 =20 reg: true --=20 2.17.1 From nobody Thu Dec 18 11:29:50 2025 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11ACC3C482 for ; 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Fri, 14 Jun 2024 07:55:36 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e739b7sm32914495ad.93.2024.06.14.07.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 07:55:35 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v3 3/4] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel. Date: Fri, 14 Jun 2024 22:55:09 +0800 Message-Id: <20240614145510.22965-4-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240614145510.22965-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240614145510.22965-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The K&d kd101ne3-40ti is a 10.1" WXGA TFT-LCD panel, use jd9365da controller,which fits in nicely with the existing panel-jadard-jd9365da-h3 driver.Hence,we add a new compatible with panel specific config. Although they have the same control IC, the two panels are different, and the timing will be slightly different, so we added some variables in struct jadard_panel_desc to control the timing Signed-off-by: Zhaoxiong Lv --- Chage since V3: - 1. Give up creating a new driver and re-add K&d kd101ne3-40ti=20 - configuration to the panel-jadard-jd9365da-h3.c driver. V2:https://lore.kernel.org/all/20240601084528.22502-3-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Chage since V2: - 1. Use the new mipi_dsi_dcs_write_seq_multi() function. - 2. Modify Move mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sle= ep_mode() to disable(), - and drop kingdisplay_panel_enter_sleep_mode(). - 3. If prepare fails, disable GPIO before regulators. - 4. This function drm_connector_set_panel_orientation() is no longer used= . Delete it. - 5. Drop ".shutdown =3D kingdisplay_panel_shutdown". --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 284 ++++++++++++++++++ 1 file changed, 284 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu= /drm/panel/panel-jadard-jd9365da-h3.c index b39f01d7002e..f6e130567707 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -27,6 +27,15 @@ struct jadard_panel_desc { enum mipi_dsi_pixel_format format; int (*init)(struct jadard *jadard); u32 num_init_cmds; + bool lp11_before_reset; + bool power_off_vcioo_before_reset; + unsigned int vcioo_to_lp11_delay; + unsigned int lp11_to_reset_delay; + unsigned int exit_sleep_to_display_on_delay; + unsigned int display_on_delay; + unsigned int backlight_off_to_display_off_delay; + unsigned int display_off_to_enter_sleep_delay; + unsigned int enter_sleep_to_reset_down_delay; }; =20 struct jadard { @@ -57,10 +66,18 @@ static int jadard_enable(struct drm_panel *panel) if (err < 0) DRM_DEV_ERROR(dev, "failed to exit sleep mode ret =3D %d\n", err); =20 + /* tSLPOUT >=3D 120ms */ + if (jadard->desc->exit_sleep_to_display_on_delay) + msleep(jadard->desc->exit_sleep_to_display_on_delay); + err =3D mipi_dsi_dcs_set_display_on(dsi); if (err < 0) DRM_DEV_ERROR(dev, "failed to set display on ret =3D %d\n", err); =20 + /* tDISON >=3D 20ms */ + if (jadard->desc->display_on_delay) + msleep(jadard->desc->display_on_delay); + return 0; } =20 @@ -70,14 +87,26 @@ static int jadard_disable(struct drm_panel *panel) struct jadard *jadard =3D panel_to_jadard(panel); int ret; =20 + /* tBLOFF:Backlight_to_0x28h >=3D 100ms */ + if (jadard->desc->backlight_off_to_display_off_delay) + msleep(jadard->desc->backlight_off_to_display_off_delay); + ret =3D mipi_dsi_dcs_set_display_off(jadard->dsi); if (ret < 0) DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); =20 + /* tDISOFF >=3D 50ms */ + if (jadard->desc->display_off_to_enter_sleep_delay) + msleep(jadard->desc->display_off_to_enter_sleep_delay); + ret =3D mipi_dsi_dcs_enter_sleep_mode(jadard->dsi); if (ret < 0) DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); =20 + /* tSLPIN >=3D 100ms */ + if (jadard->desc->enter_sleep_to_reset_down_delay) + msleep(jadard->desc->enter_sleep_to_reset_down_delay); + return 0; } =20 @@ -94,6 +123,21 @@ static int jadard_prepare(struct drm_panel *panel) if (ret) return ret; =20 + /* tMIPI_ON >=3D 0ms */ + if (jadard->desc->vcioo_to_lp11_delay) + msleep(jadard->desc->vcioo_to_lp11_delay); + + if (jadard->desc->lp11_before_reset) { + ret =3D mipi_dsi_dcs_nop(jadard->dsi); + if (ret < 0) + goto poweroff; + + usleep_range(1000, 2000); + } + /* tRPWIRES >=3D 5ms */ + if (jadard->desc->lp11_to_reset_delay) + msleep(jadard->desc->lp11_to_reset_delay); + gpiod_set_value(jadard->reset, 1); msleep(5); =20 @@ -125,6 +169,12 @@ static int jadard_unprepare(struct drm_panel *panel) gpiod_set_value(jadard->reset, 1); msleep(120); =20 + if (jadard->desc->power_off_vcioo_before_reset) { + gpiod_set_value(jadard->reset, 0); + + usleep_range(1000, 2000); + } + regulator_disable(jadard->vdd); regulator_disable(jadard->vccio); =20 @@ -586,7 +636,237 @@ static const struct jadard_panel_desc cz101b4001_desc= =3D { .lanes =3D 4, .format =3D MIPI_DSI_FMT_RGB888, .init =3D cz101b4001_init_cmds, +}; + +static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; =20 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + + return 0; +}; + +static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc =3D { + .mode =3D { + .clock =3D 70595, + + .hdisplay =3D 800, + .hsync_start =3D 800 + 30, + .hsync_end =3D 800 + 30 + 30, + .htotal =3D 800 + 30 + 30 + 30, + + .vdisplay =3D 1280, + .vsync_start =3D 1280 + 30, + .vsync_end =3D 1280 + 30 + 4, + .vtotal =3D 1280 + 30 + 4 + 8, + + .width_mm =3D 135, + .height_mm =3D 216, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes =3D 4, + .format =3D MIPI_DSI_FMT_RGB888, + .init =3D kingdisplay_kd101ne3_init_cmds, + .lp11_before_reset =3D true, + .power_off_vcioo_before_reset =3D true, + .vcioo_to_lp11_delay =3D 5, + .lp11_to_reset_delay =3D 10, + .exit_sleep_to_display_on_delay =3D 120, + .display_on_delay =3D 20, + .backlight_off_to_display_off_delay =3D 100, + .display_off_to_enter_sleep_delay =3D 50, + .enter_sleep_to_reset_down_delay =3D 100, }; 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Fri, 14 Jun 2024 07:55:40 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e739b7sm32914495ad.93.2024.06.14.07.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 07:55:40 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v3 4/4] drm/panel: jd9365da: Add the function of adjusting orientation Date: Fri, 14 Jun 2024 22:55:10 +0800 Message-Id: <20240614145510.22965-5-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240614145510.22965-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240614145510.22965-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This driver does not have the function to adjust the orientation, so this function is added. Signed-off-by: Zhaoxiong Lv --- drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu= /drm/panel/panel-jadard-jd9365da-h3.c index f6e130567707..7f86bb7f2299 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -42,7 +42,7 @@ struct jadard { struct drm_panel panel; struct mipi_dsi_device *dsi; const struct jadard_panel_desc *desc; - + enum drm_panel_orientation orientation; struct regulator *vdd; struct regulator *vccio; struct gpio_desc *reset; @@ -205,12 +205,20 @@ static int jadard_get_modes(struct drm_panel *panel, return 1; } =20 +static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_= panel *panel) +{ + struct jadard *jadard =3D panel_to_jadard(panel); + + return jadard->orientation; +} + static const struct drm_panel_funcs jadard_funcs =3D { .disable =3D jadard_disable, .unprepare =3D jadard_unprepare, .prepare =3D jadard_prepare, .enable =3D jadard_enable, .get_modes =3D jadard_get_modes, + .get_orientation =3D jadard_panel_get_orientation, }; =20 static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) @@ -907,6 +915,12 @@ static int jadard_dsi_probe(struct mipi_dsi_device *ds= i) drm_panel_init(&jadard->panel, dev, &jadard_funcs, DRM_MODE_CONNECTOR_DSI); =20 + ret =3D of_drm_get_panel_orientation(dev->of_node, &jadard->orientation); + if (ret < 0) { + dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret); + return ret; + } + ret =3D drm_panel_of_backlight(&jadard->panel); if (ret) return ret; --=20 2.17.1