From nobody Thu Dec 18 23:39:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C16919D896 for ; Fri, 14 Jun 2024 13:47:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718372873; cv=none; b=ngom3A1O90Eb5NoTCgQr8OVl9vvyRluyPbUQOYnxiTTBZuItJs2uogLZELwSzFlEUfXtM7mQgJdLv0VP4Fb9VtqvbY51GjqG2RMBLr4xsW1THd2aKSBbX8saa9eRRnGHA1aD4vTrnNhPeEtg2siuqm7Sa5Vv5xpK43MDQdq0Bo4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718372873; c=relaxed/simple; bh=dSRu79zPsFMjSz7soAdAwuKfJ58eR3YhLRJFc8yq9m4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fkZ7UsdHICVXKDJ9Me5D4m9VwjXWHKLcg+95z0a8m/oyPRrg6zCapLrY4dcPvJ/bYZuCPtAVuIvsy4UMqRoksyKjFi1/ipoJvJUCmZKqSIdW929xHMv3XWWheysH5UWWWkan1QiUG8ZVbEZpToHFVZJybHdzzfJIua0KYVb2XxQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Vp8oSRDD; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Vp8oSRDD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718372872; x=1749908872; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dSRu79zPsFMjSz7soAdAwuKfJ58eR3YhLRJFc8yq9m4=; b=Vp8oSRDDjHaUNrUUuMJkj7Ng/5hP+pq0kgxNjpcxRajrLk9EExizmSyD 0eSfv+qAyR7oh35sqNENm9oQlTZ8oxqYsTWQ0ba28SwA2O/pnHZl042Fo OmZENZWjKPCXkbIz9IO5ofbIEECYHbuVbnF0ic4Z2h7gsqkOk6YTnhopI gyALBTVTj0cZJtUAMTecilCA50BnY6q/vp2k5mTzDuHO3z/NgEEN1+NHt nyurxttyelgzzJfTgUEHOI20inKIliXplitySqV6oxiRSWWFA5y7N21zg W1t8BuAqIsUhopcNWiUmjTxWO6QmpX24BRiXDI3SMmCVwr01gY46hpsDk A==; X-CSE-ConnectionGUID: ltnUYSnZR1W6iqGD/7LBng== X-CSE-MsgGUID: bcxGcsGUSg+hEUgfgAvGjw== X-IronPort-AV: E=McAfee;i="6700,10204,11103"; a="19079147" X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="19079147" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 06:47:51 -0700 X-CSE-ConnectionGUID: bwb/n8h4Svy/LrE+iGQ9cQ== X-CSE-MsgGUID: Xi9mFQNDToeOD2LNcGvQTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="40386664" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa006.fm.intel.com with ESMTP; 14 Jun 2024 06:47:50 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, tim.c.chen@linux.intel.com, Kan Liang Subject: [PATCH V2 1/8] perf/x86/uncore: Save the unit control address of all units Date: Fri, 14 Jun 2024 06:46:24 -0700 Message-Id: <20240614134631.1092359-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240614134631.1092359-1-kan.liang@linux.intel.com> References: <20240614134631.1092359-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The unit control address of some CXL units may be wrongly calculated under some configuration on a EMR machine. The current implementation only saves the unit control address of the units from the first die, and the first unit of the rest of dies. Perf assumed that the units from the other dies have the same offset as the first die. So the unit control address of the rest of the units can be calculated. However, the assumption is wrong, especially for the CXL units. Introduce an RB tree for each uncore type to save the unit control address and three kinds of ID information (unit ID, PMU ID, and die ID) for all units. The unit ID is a physical ID of a unit. The PMU ID is a logical ID assigned to a unit. The logical IDs start from 0 and must be contiguous. The physical ID and the logical ID are 1:1 mapping. The units with the same physical ID in different dies share the same PMU. The die ID indicates which die a unit belongs to. The RB tree can be searched by two different keys (unit ID or PMU ID + die ID). During the RB tree setup, the unit ID is used as a key to look up the RB tree. The perf can create/assign a proper PMU ID to the unit. Later, after the RB tree is setup, PMU ID + die ID is used as a key to look up the RB tree to fill the cpumask of a PMU. It's used more frequently, so PMU ID + die ID is compared in the unit_less(). The uncore_find_unit() has to be O(N). But the RB tree setup only occurs once during the driver load time. It should be acceptable. Compared with the current implementation, more space is required to save the information of all units. The extra size should be acceptable. For example, on EMR, there are 221 units at most. For a 2-socket machine, the extra space is ~6KB at most. Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_discovery.c | 79 +++++++++++++++++++++++- arch/x86/events/intel/uncore_discovery.h | 10 +++ 2 files changed, 87 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 9a698a92962a..ce520e69a3c1 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -93,6 +93,8 @@ add_uncore_discovery_type(struct uncore_unit_discovery *u= nit) if (!type->box_ctrl_die) goto free_type; =20 + type->units =3D RB_ROOT; + type->access_type =3D unit->access_type; num_discovered_types[type->access_type]++; type->type =3D unit->box_type; @@ -120,10 +122,59 @@ get_uncore_discovery_type(struct uncore_unit_discover= y *unit) return add_uncore_discovery_type(unit); } =20 +static inline bool unit_less(struct rb_node *a, const struct rb_node *b) +{ + struct intel_uncore_discovery_unit *a_node, *b_node; + + a_node =3D rb_entry(a, struct intel_uncore_discovery_unit, node); + b_node =3D rb_entry(b, struct intel_uncore_discovery_unit, node); + + if (a_node->pmu_idx < b_node->pmu_idx) + return true; + if (a_node->pmu_idx > b_node->pmu_idx) + return false; + + if (a_node->die < b_node->die) + return true; + if (a_node->die > b_node->die) + return false; + + return 0; +} + +static inline struct intel_uncore_discovery_unit * +uncore_find_unit(struct rb_root *root, unsigned int id) +{ + struct intel_uncore_discovery_unit *unit; + struct rb_node *node; + + for (node =3D rb_first(root); node; node =3D rb_next(node)) { + unit =3D rb_entry(node, struct intel_uncore_discovery_unit, node); + if (unit->id =3D=3D id) + return unit; + } + + return NULL; +} + +static void uncore_find_add_unit(struct intel_uncore_discovery_unit *node, + struct rb_root *root, u16 *num_units) +{ + struct intel_uncore_discovery_unit *unit =3D uncore_find_unit(root, node-= >id); + + if (unit) + node->pmu_idx =3D unit->pmu_idx; + else if (num_units) + node->pmu_idx =3D (*num_units)++; + + rb_add(&node->node, root, unit_less); +} + static void uncore_insert_box_info(struct uncore_unit_discovery *unit, int die, bool parsed) { + struct intel_uncore_discovery_unit *node; struct intel_uncore_discovery_type *type; unsigned int *ids; u64 *box_offset; @@ -136,14 +187,26 @@ uncore_insert_box_info(struct uncore_unit_discovery *= unit, return; } =20 + node =3D kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + return; + + node->die =3D die; + node->id =3D unit->box_id; + node->addr =3D unit->ctl; + if (parsed) { type =3D search_uncore_discovery_type(unit->box_type); if (!type) { pr_info("A spurious uncore type %d is detected, " "Disable the uncore type.\n", unit->box_type); + kfree(node); return; } + + uncore_find_add_unit(node, &type->units, &type->num_units); + /* Store the first box of each die */ if (!type->box_ctrl_die[die]) type->box_ctrl_die[die] =3D unit->ctl; @@ -152,16 +215,18 @@ uncore_insert_box_info(struct uncore_unit_discovery *= unit, =20 type =3D get_uncore_discovery_type(unit); if (!type) - return; + goto free_node; =20 box_offset =3D kcalloc(type->num_boxes + 1, sizeof(u64), GFP_KERNEL); if (!box_offset) - return; + goto free_node; =20 ids =3D kcalloc(type->num_boxes + 1, sizeof(unsigned int), GFP_KERNEL); if (!ids) goto free_box_offset; =20 + uncore_find_add_unit(node, &type->units, &type->num_units); + /* Store generic information for the first box */ if (!type->num_boxes) { type->box_ctrl =3D unit->ctl; @@ -201,6 +266,8 @@ uncore_insert_box_info(struct uncore_unit_discovery *un= it, free_box_offset: kfree(box_offset); =20 +free_node: + kfree(node); } =20 static bool @@ -339,8 +406,16 @@ bool intel_uncore_has_discovery_tables(int *ignore) void intel_uncore_clear_discovery_tables(void) { struct intel_uncore_discovery_type *type, *next; + struct intel_uncore_discovery_unit *pos; + struct rb_node *node; =20 rbtree_postorder_for_each_entry_safe(type, next, &discovery_tables, node)= { + while (!RB_EMPTY_ROOT(&type->units)) { + node =3D rb_first(&type->units); + pos =3D rb_entry(node, struct intel_uncore_discovery_unit, node); + rb_erase(node, &type->units); + kfree(pos); + } kfree(type->box_ctrl_die); kfree(type); } diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 22e769a81103..5190017aba51 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -113,17 +113,27 @@ struct uncore_unit_discovery { }; }; =20 +struct intel_uncore_discovery_unit { + struct rb_node node; + unsigned int pmu_idx; /* The idx of the corresponding PMU */ + unsigned int id; /* Unit ID */ + unsigned int die; /* Die ID */ + u64 addr; /* Unit Control Address */ +}; + struct intel_uncore_discovery_type { struct rb_node node; enum uncore_access_type access_type; u64 box_ctrl; /* Unit ctrl addr of the first box */ u64 *box_ctrl_die; /* Unit ctrl addr of the first box of each die */ + struct rb_root units; /* Unit ctrl addr for all units */ u16 type; /* Type ID of the uncore block */ u8 num_counters; u8 counter_width; u8 ctl_offset; /* Counter Control 0 offset */ u8 ctr_offset; /* Counter 0 offset */ u16 num_boxes; /* number of boxes for the uncore block */ + u16 num_units; /* number of units */ unsigned int *ids; /* Box IDs */ u64 *box_offset; /* Box offset */ }; --=20 2.35.1 From nobody Thu Dec 18 23:39:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6ED5523D for ; Fri, 14 Jun 2024 13:47:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718372874; cv=none; b=fzqQVq7LJBQkxVbeFm5kqd1ENzopkKnX+rwn980ar+0ttZ+HWN4hbTQSBQXcV555Gp5UNA86kFcTX2wIDkHzEaKHsRTH63834r+tA+8g5IzL5517qvTQU/hfmrr/e/8jKYCfjzfARCuxdVZ04XQaOhthso+/JigWXyDGAOtFAcg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718372874; c=relaxed/simple; bh=VTtdyC2NsuHT44Nr0ys9g8RojgFenib/2fJcDi831bA=; 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14 Jun 2024 06:47:50 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, tim.c.chen@linux.intel.com, Kan Liang Subject: [PATCH V2 2/8] perf/x86/uncore: Support per PMU cpumask Date: Fri, 14 Jun 2024 06:46:25 -0700 Message-Id: <20240614134631.1092359-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240614134631.1092359-1-kan.liang@linux.intel.com> References: <20240614134631.1092359-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The cpumask of some uncore units, e.g., CXL uncore units, may be wrong under some configurations. Perf may access an uncore counter of a non-existent uncore unit. The uncore driver assumes that all uncore units are symmetric among dies. A global cpumask is shared among all uncore PMUs. However, some CXL uncore units may only be available on some dies. A per PMU cpumask is introduced to track the CPU mask of this PMU. The driver searches the unit control RB tree to check whether the PMU is available on a given die, and updates the per PMU cpumask accordingly. Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 31 +++++++++++-- arch/x86/events/intel/uncore.h | 2 + arch/x86/events/intel/uncore_discovery.c | 58 ++++++++++++++++++++++++ arch/x86/events/intel/uncore_discovery.h | 3 ++ 4 files changed, 89 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 258e2cdf28fa..c2d877d20e31 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -843,7 +843,9 @@ static void uncore_pmu_disable(struct pmu *pmu) static ssize_t uncore_get_attr_cpumask(struct device *dev, struct device_attribute *attr, char *buf) { - return cpumap_print_to_pagebuf(true, buf, &uncore_cpu_mask); + struct intel_uncore_pmu *pmu =3D container_of(dev_get_drvdata(dev), struc= t intel_uncore_pmu, pmu); + + return cpumap_print_to_pagebuf(true, buf, &pmu->cpu_mask); } =20 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL); @@ -1453,6 +1455,18 @@ static void uncore_pci_exit(void) } } =20 +static bool uncore_die_has_box(struct intel_uncore_type *type, + int die, unsigned int pmu_idx) +{ + if (!type->boxes) + return true; + + if (intel_uncore_find_discovery_unit_id(type->boxes, die, pmu_idx) < 0) + return false; + + return true; +} + static void uncore_change_type_ctx(struct intel_uncore_type *type, int old= _cpu, int new_cpu) { @@ -1468,18 +1482,25 @@ static void uncore_change_type_ctx(struct intel_unc= ore_type *type, int old_cpu, =20 if (old_cpu < 0) { WARN_ON_ONCE(box->cpu !=3D -1); - box->cpu =3D new_cpu; + if (uncore_die_has_box(type, die, pmu->pmu_idx)) { + box->cpu =3D new_cpu; + cpumask_set_cpu(new_cpu, &pmu->cpu_mask); + } continue; } =20 - WARN_ON_ONCE(box->cpu !=3D old_cpu); + WARN_ON_ONCE(box->cpu !=3D -1 && box->cpu !=3D old_cpu); box->cpu =3D -1; + cpumask_clear_cpu(old_cpu, &pmu->cpu_mask); if (new_cpu < 0) continue; =20 + if (!uncore_die_has_box(type, die, pmu->pmu_idx)) + continue; uncore_pmu_cancel_hrtimer(box); perf_pmu_migrate_context(&pmu->pmu, old_cpu, new_cpu); box->cpu =3D new_cpu; + cpumask_set_cpu(new_cpu, &pmu->cpu_mask); } } =20 @@ -1502,7 +1523,7 @@ static void uncore_box_unref(struct intel_uncore_type= **types, int id) pmu =3D type->pmus; for (i =3D 0; i < type->num_boxes; i++, pmu++) { box =3D pmu->boxes[id]; - if (box && atomic_dec_return(&box->refcnt) =3D=3D 0) + if (box && box->cpu >=3D 0 && atomic_dec_return(&box->refcnt) =3D=3D 0) uncore_box_exit(box); } } @@ -1592,7 +1613,7 @@ static int uncore_box_ref(struct intel_uncore_type **= types, pmu =3D type->pmus; for (i =3D 0; i < type->num_boxes; i++, pmu++) { box =3D pmu->boxes[id]; - if (box && atomic_inc_return(&box->refcnt) =3D=3D 1) + if (box && box->cpu >=3D 0 && atomic_inc_return(&box->refcnt) =3D=3D 1) uncore_box_init(box); } } diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 4838502d89ae..0a49e304fe40 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -86,6 +86,7 @@ struct intel_uncore_type { const struct attribute_group *attr_groups[4]; const struct attribute_group **attr_update; struct pmu *pmu; /* for custom pmu ops */ + struct rb_root *boxes; /* * Uncore PMU would store relevant platform topology configuration here * to identify which platform component each PMON block of that type is @@ -125,6 +126,7 @@ struct intel_uncore_pmu { int func_id; bool registered; atomic_t activeboxes; + cpumask_t cpu_mask; struct intel_uncore_type *type; struct intel_uncore_box **boxes; }; diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index ce520e69a3c1..e61e460520a8 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -122,6 +122,64 @@ get_uncore_discovery_type(struct uncore_unit_discovery= *unit) return add_uncore_discovery_type(unit); } =20 +static inline int pmu_idx_cmp(const void *key, const struct rb_node *b) +{ + struct intel_uncore_discovery_unit *unit; + const unsigned int *id =3D key; + + unit =3D rb_entry(b, struct intel_uncore_discovery_unit, node); + + if (unit->pmu_idx > *id) + return -1; + else if (unit->pmu_idx < *id) + return 1; + + return 0; +} + +static struct intel_uncore_discovery_unit * +intel_uncore_find_discovery_unit(struct rb_root *units, int die, + unsigned int pmu_idx) +{ + struct intel_uncore_discovery_unit *unit; + struct rb_node *pos; + + if (!units) + return NULL; + + pos =3D rb_find_first(&pmu_idx, units, pmu_idx_cmp); + if (!pos) + return NULL; + unit =3D rb_entry(pos, struct intel_uncore_discovery_unit, node); + + if (die < 0) + return unit; + + for (; pos; pos =3D rb_next(pos)) { + unit =3D rb_entry(pos, struct intel_uncore_discovery_unit, node); + + if (unit->pmu_idx !=3D pmu_idx) + break; + + if (unit->die =3D=3D die) + return unit; + } + + return NULL; +} + +int intel_uncore_find_discovery_unit_id(struct rb_root *units, int die, + unsigned int pmu_idx) +{ + struct intel_uncore_discovery_unit *unit; + + unit =3D intel_uncore_find_discovery_unit(units, die, pmu_idx); + if (unit) + return unit->id; + + return -1; +} + static inline bool unit_less(struct rb_node *a, const struct rb_node *b) { struct intel_uncore_discovery_unit *a_node, *b_node; diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 5190017aba51..96265cf1fc86 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -166,3 +166,6 @@ u64 intel_generic_uncore_pci_read_counter(struct intel_= uncore_box *box, =20 struct intel_uncore_type ** intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num= _extra); 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14 Jun 2024 06:47:51 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, tim.c.chen@linux.intel.com, Kan Liang Subject: [PATCH V2 3/8] perf/x86/uncore: Retrieve the unit ID from the unit control RB tree Date: Fri, 14 Jun 2024 06:46:26 -0700 Message-Id: <20240614134631.1092359-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240614134631.1092359-1-kan.liang@linux.intel.com> References: <20240614134631.1092359-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The box_ids only save the unit ID for the first die. If a unit, e.g., a CXL unit, doesn't exist in the first die. The unit ID cannot be retrieved. The unit control RB tree also stores the unit ID information. Retrieve the unit ID from the unit control RB tree Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index c2d877d20e31..3ad23527833a 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -862,6 +862,9 @@ static const struct attribute_group uncore_pmu_attr_gro= up =3D { static inline int uncore_get_box_id(struct intel_uncore_type *type, struct intel_uncore_pmu *pmu) { + if (type->boxes) + return intel_uncore_find_discovery_unit_id(type->boxes, -1, pmu->pmu_idx= ); + return type->box_ids ? type->box_ids[pmu->pmu_idx] : pmu->pmu_idx; } =20 --=20 2.35.1 From nobody Thu Dec 18 23:39:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF18D8BFC for ; Fri, 14 Jun 2024 13:47:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718372875; cv=none; b=gP2hijv4cgkgY0Nc++HQo0Ubp5uZY8tX0CZCM3tOwSYpJiDknYyUy7yb81JhR2wpOp9u3esmtxJ4d++ViFKjb+WOgvCvS5QfwiklaBLQdyFI4aktkgLKObd/YQfGic4GsSjBh+wCcJum7t38zfjbD0ZI2vBmCq7s9mtlR78/s0U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718372875; c=relaxed/simple; bh=BIopyuEiippERL55Q+YUB/F51kO/pgwegBOMEDJyk+c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I4sXIp50RiIiBrIhTZYm6jrQMzFqyPpThJcI94Uz3YjaZNL4XgioPQNjEhOMNwS7hjVMCAx4iKDAh0TLJLWRZVAG0OEFK7Isy1K8SecMaeBCd7a88ZW4evX3QT7VOMUl2bYS8KmU+C1rjThwk6cH5Nl+aLmLEX8grwOVa9Htn0c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IYvNKa24; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IYvNKa24" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718372874; x=1749908874; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BIopyuEiippERL55Q+YUB/F51kO/pgwegBOMEDJyk+c=; b=IYvNKa24ih2XYg/NvWL3vRHHEYE67VMhKkUdQQQgUa+XGFaPz3juMXsX hGHlB4aYvToN3I/es1crS1v4KePB+1D3B50IR7FvHBb8fNy7Hx0rgm12T 5TVGvuyx5Ts7WytqDLZLFt6on/nu5e6jCtogmptdfVQB31KdlEoSvNBzp d79RnFbI0yuoPi/iHUk6nT2DheRC7Gk0n6uKrZ/veNJ8pjhFK5bo/jxyi LmPsNIHKh2xL3PlTbCDesii9kU+JZFp9SlTldaGoyEknpzQv7XMzl5/hi ddPIDKDajd+q+NUB1yIzzzmMBdyufBbD40CKDXoAmfrDzlxcIydbNtuwo w==; X-CSE-ConnectionGUID: 23kuTPzTQnm4l3XBnXnJqw== X-CSE-MsgGUID: nfQ1/hZERGemJowzV9aNBA== X-IronPort-AV: E=McAfee;i="6700,10204,11103"; a="19079159" X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="19079159" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 06:47:52 -0700 X-CSE-ConnectionGUID: XFRdpkM5T7GaMvL8/YssQw== X-CSE-MsgGUID: iqvbjXGqR/+0gaqbkB8YfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="40386674" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa006.fm.intel.com with ESMTP; 14 Jun 2024 06:47:51 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, tim.c.chen@linux.intel.com, Kan Liang Subject: [PATCH V2 4/8] perf/x86/uncore: Apply the unit control RB tree to MMIO uncore units Date: Fri, 14 Jun 2024 06:46:27 -0700 Message-Id: <20240614134631.1092359-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240614134631.1092359-1-kan.liang@linux.intel.com> References: <20240614134631.1092359-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The unit control RB tree has the unit control and unit ID information for all the units. Use it to replace the box_ctls/mmio_offsets to get an accurate unit control address for MMIO uncore units. Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_discovery.c | 30 +++++++++++------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index e61e460520a8..ece761c9f17a 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -606,34 +606,30 @@ static struct intel_uncore_ops generic_uncore_pci_ops= =3D { =20 #define UNCORE_GENERIC_MMIO_SIZE 0x4000 =20 -static u64 generic_uncore_mmio_box_ctl(struct intel_uncore_box *box) -{ - struct intel_uncore_type *type =3D box->pmu->type; - - if (!type->box_ctls || !type->box_ctls[box->dieid] || !type->mmio_offsets) - return 0; - - return type->box_ctls[box->dieid] + type->mmio_offsets[box->pmu->pmu_idx]; -} - void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box) { - u64 box_ctl =3D generic_uncore_mmio_box_ctl(box); + static struct intel_uncore_discovery_unit *unit; struct intel_uncore_type *type =3D box->pmu->type; resource_size_t addr; =20 - if (!box_ctl) { + unit =3D intel_uncore_find_discovery_unit(type->boxes, box->dieid, box->p= mu->pmu_idx); + if (!unit) { + pr_warn("Uncore type %d id %d: Cannot find box control address.\n", + type->type_id, box->pmu->pmu_idx); + return; + } + + if (!unit->addr) { pr_warn("Uncore type %d box %d: Invalid box control address.\n", - type->type_id, type->box_ids[box->pmu->pmu_idx]); + type->type_id, unit->id); return; } =20 - addr =3D box_ctl; + addr =3D unit->addr; box->io_addr =3D ioremap(addr, UNCORE_GENERIC_MMIO_SIZE); if (!box->io_addr) { pr_warn("Uncore type %d box %d: ioremap error for 0x%llx.\n", - type->type_id, type->box_ids[box->pmu->pmu_idx], - (unsigned long long)addr); + type->type_id, unit->id, (unsigned long long)addr); return; } =20 @@ -722,6 +718,8 @@ static bool uncore_update_uncore_type(enum uncore_acces= s_type type_id, uncore->box_ctls =3D type->box_ctrl_die; uncore->mmio_offsets =3D type->box_offset; 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14 Jun 2024 06:47:51 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, tim.c.chen@linux.intel.com, Kan Liang Subject: [PATCH V2 5/8] perf/x86/uncore: Apply the unit control RB tree to MSR uncore units Date: Fri, 14 Jun 2024 06:46:28 -0700 Message-Id: <20240614134631.1092359-6-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240614134631.1092359-1-kan.liang@linux.intel.com> References: <20240614134631.1092359-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The unit control RB tree has the unit control and unit ID information for all the MSR units. Use them to replace the box_ctl and uncore_msr_box_ctl() to get an accurate unit control address for MSR uncore units. Add intel_generic_uncore_assign_hw_event(), which utilizes the accurate unit control address from the unit control RB tree to calculate the config_base and event_base. The unit id related information should be retrieved from the unit control RB tree as well. Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 3 ++ arch/x86/events/intel/uncore_discovery.c | 49 +++++++++++++++++++++--- arch/x86/events/intel/uncore_discovery.h | 2 + arch/x86/events/intel/uncore_snbep.c | 16 +++++--- 4 files changed, 59 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 3ad23527833a..f48c7049d2ed 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -263,6 +263,9 @@ static void uncore_assign_hw_event(struct intel_uncore_= box *box, return; } =20 + if (intel_generic_uncore_assign_hw_event(event, box)) + return; + hwc->config_base =3D uncore_event_ctl(box, hwc->idx); hwc->event_base =3D uncore_perf_ctr(box, hwc->idx); } diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index ece761c9f17a..076ec1efe9cc 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -499,19 +499,31 @@ static const struct attribute_group generic_uncore_fo= rmat_group =3D { .attrs =3D generic_uncore_formats_attr, }; =20 +static u64 intel_generic_uncore_box_ctl(struct intel_uncore_box *box) +{ + struct intel_uncore_discovery_unit *unit; + + unit =3D intel_uncore_find_discovery_unit(box->pmu->type->boxes, + -1, box->pmu->pmu_idx); + if (WARN_ON_ONCE(!unit)) + return 0; + + return unit->addr; +} + void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) { - wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); + wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); } =20 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) { - wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); + wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); } =20 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box) { - wrmsrl(uncore_msr_box_ctl(box), 0); + wrmsrl(intel_generic_uncore_box_ctl(box), 0); } =20 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box = *box, @@ -539,6 +551,31 @@ static struct intel_uncore_ops generic_uncore_msr_ops = =3D { .read_counter =3D uncore_msr_read_counter, }; =20 +bool intel_generic_uncore_assign_hw_event(struct perf_event *event, + struct intel_uncore_box *box) +{ + struct hw_perf_event *hwc =3D &event->hw; + u64 box_ctl; + + if (!box->pmu->type->boxes) + return false; + + if (box->pci_dev || box->io_addr) { + hwc->config_base =3D uncore_pci_event_ctl(box, hwc->idx); + hwc->event_base =3D uncore_pci_perf_ctr(box, hwc->idx); + return true; + } + + box_ctl =3D intel_generic_uncore_box_ctl(box); + if (!box_ctl) + return false; + + hwc->config_base =3D box_ctl + box->pmu->type->event_ctl + hwc->idx; + hwc->event_base =3D box_ctl + box->pmu->type->perf_ctr + hwc->idx; + + return true; +} + void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; @@ -697,10 +734,12 @@ static bool uncore_update_uncore_type(enum uncore_acc= ess_type type_id, switch (type_id) { case UNCORE_ACCESS_MSR: uncore->ops =3D &generic_uncore_msr_ops; - uncore->perf_ctr =3D (unsigned int)type->box_ctrl + type->ctr_offset; - uncore->event_ctl =3D (unsigned int)type->box_ctrl + type->ctl_offset; + uncore->perf_ctr =3D (unsigned int)type->ctr_offset; + uncore->event_ctl =3D (unsigned int)type->ctl_offset; uncore->box_ctl =3D (unsigned int)type->box_ctrl; uncore->msr_offsets =3D type->box_offset; + uncore->boxes =3D &type->units; + uncore->num_boxes =3D type->num_units; break; case UNCORE_ACCESS_PCI: uncore->ops =3D &generic_uncore_pci_ops; diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 96265cf1fc86..4a7a7c819d6f 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -169,3 +169,5 @@ intel_uncore_generic_init_uncores(enum uncore_access_ty= pe type_id, int num_extra =20 int intel_uncore_find_discovery_unit_id(struct rb_root *units, int die, unsigned int pmu_idx); +bool intel_generic_uncore_assign_hw_event(struct perf_event *event, + struct intel_uncore_box *box); diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 2eaf0f339849..c42b170886d2 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5932,10 +5932,11 @@ static int spr_cha_hw_config(struct intel_uncore_bo= x *box, struct perf_event *ev struct hw_perf_event_extra *reg1 =3D &event->hw.extra_reg; bool tie_en =3D !!(event->hw.config & SPR_CHA_PMON_CTL_TID_EN); struct intel_uncore_type *type =3D box->pmu->type; + int id =3D intel_uncore_find_discovery_unit_id(type->boxes, -1, box->pmu-= >pmu_idx); =20 if (tie_en) { reg1->reg =3D SPR_C0_MSR_PMON_BOX_FILTER0 + - HSWEP_CBO_MSR_OFFSET * type->box_ids[box->pmu->pmu_idx]; + HSWEP_CBO_MSR_OFFSET * id; reg1->config =3D event->attr.config1 & SPR_CHA_PMON_BOX_FILTER_TID; reg1->idx =3D 0; } @@ -6459,18 +6460,21 @@ uncore_find_type_by_id(struct intel_uncore_type **t= ypes, int type_id) static int uncore_type_max_boxes(struct intel_uncore_type **types, int type_id) { + struct intel_uncore_discovery_unit *unit; struct intel_uncore_type *type; - int i, max =3D 0; + struct rb_node *node; + int max =3D 0; =20 type =3D uncore_find_type_by_id(types, type_id); if (!type) return 0; =20 - for (i =3D 0; i < type->num_boxes; i++) { - if (type->box_ids[i] > max) - max =3D type->box_ids[i]; - } + for (node =3D rb_first(type->boxes); node; node =3D rb_next(node)) { + unit =3D rb_entry(node, struct intel_uncore_discovery_unit, node); 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charset="utf-8" From: Kan Liang The unit control RB tree has the unit control and unit ID information for all the PCI units. Use them to replace the box_ctls/pci_offsets to get an accurate unit control address for PCI uncore units. The UPI/M3UPI units in the discovery table are ignored. Please see the commit 65248a9a9ee1 ("perf/x86/uncore: Add a quirk for UPI on SPR"). Manually allocate a unit control RB tree for UPI/M3UPI. Add cleanup_extra_boxes to release such manual allocation. Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 53 +++++++++++----------- arch/x86/events/intel/uncore.h | 4 ++ arch/x86/events/intel/uncore_discovery.c | 26 ++++++++--- arch/x86/events/intel/uncore_discovery.h | 2 + arch/x86/events/intel/uncore_snbep.c | 57 ++++++++++++++++++------ 5 files changed, 94 insertions(+), 48 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index f48c7049d2ed..79449c5b9256 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -969,6 +969,9 @@ static void uncore_type_exit(struct intel_uncore_type *= type) if (type->cleanup_mapping) type->cleanup_mapping(type); =20 + if (type->cleanup_extra_boxes) + type->cleanup_extra_boxes(type); + if (pmu) { for (i =3D 0; i < type->num_boxes; i++, pmu++) { uncore_pmu_unregister(pmu); @@ -1084,22 +1087,19 @@ static struct intel_uncore_pmu * uncore_pci_find_dev_pmu_from_types(struct pci_dev *pdev) { struct intel_uncore_type **types =3D uncore_pci_uncores; + struct intel_uncore_discovery_unit *unit; struct intel_uncore_type *type; - u64 box_ctl; - int i, die; + struct rb_node *node; =20 for (; *types; types++) { type =3D *types; - for (die =3D 0; die < __uncore_max_dies; die++) { - for (i =3D 0; i < type->num_boxes; i++) { - if (!type->box_ctls[die]) - continue; - box_ctl =3D type->box_ctls[die] + type->pci_offsets[i]; - if (pdev->devfn =3D=3D UNCORE_DISCOVERY_PCI_DEVFN(box_ctl) && - pdev->bus->number =3D=3D UNCORE_DISCOVERY_PCI_BUS(box_ctl) && - pci_domain_nr(pdev->bus) =3D=3D UNCORE_DISCOVERY_PCI_DOMAIN(box_ct= l)) - return &type->pmus[i]; - } + + for (node =3D rb_first(type->boxes); node; node =3D rb_next(node)) { + unit =3D rb_entry(node, struct intel_uncore_discovery_unit, node); + if (pdev->devfn =3D=3D UNCORE_DISCOVERY_PCI_DEVFN(unit->addr) && + pdev->bus->number =3D=3D UNCORE_DISCOVERY_PCI_BUS(unit->addr) && + pci_domain_nr(pdev->bus) =3D=3D UNCORE_DISCOVERY_PCI_DOMAIN(unit->a= ddr)) + return &type->pmus[unit->pmu_idx]; } } =20 @@ -1375,28 +1375,25 @@ static struct notifier_block uncore_pci_notifier = =3D { static void uncore_pci_pmus_register(void) { struct intel_uncore_type **types =3D uncore_pci_uncores; + struct intel_uncore_discovery_unit *unit; struct intel_uncore_type *type; struct intel_uncore_pmu *pmu; + struct rb_node *node; struct pci_dev *pdev; - u64 box_ctl; - int i, die; =20 for (; *types; types++) { type =3D *types; - for (die =3D 0; die < __uncore_max_dies; die++) { - for (i =3D 0; i < type->num_boxes; i++) { - if (!type->box_ctls[die]) - continue; - box_ctl =3D type->box_ctls[die] + type->pci_offsets[i]; - pdev =3D pci_get_domain_bus_and_slot(UNCORE_DISCOVERY_PCI_DOMAIN(box_c= tl), - UNCORE_DISCOVERY_PCI_BUS(box_ctl), - UNCORE_DISCOVERY_PCI_DEVFN(box_ctl)); - if (!pdev) - continue; - pmu =3D &type->pmus[i]; - - uncore_pci_pmu_register(pdev, type, pmu, die); - } + + for (node =3D rb_first(type->boxes); node; node =3D rb_next(node)) { + unit =3D rb_entry(node, struct intel_uncore_discovery_unit, node); + pdev =3D pci_get_domain_bus_and_slot(UNCORE_DISCOVERY_PCI_DOMAIN(unit->= addr), + UNCORE_DISCOVERY_PCI_BUS(unit->addr), + UNCORE_DISCOVERY_PCI_DEVFN(unit->addr)); + + if (!pdev) + continue; + pmu =3D &type->pmus[unit->pmu_idx]; + uncore_pci_pmu_register(pdev, type, pmu, unit->die); } } =20 diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 0a49e304fe40..05c429c8cb93 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -99,6 +99,10 @@ struct intel_uncore_type { int (*get_topology)(struct intel_uncore_type *type); void (*set_mapping)(struct intel_uncore_type *type); void (*cleanup_mapping)(struct intel_uncore_type *type); + /* + * Optional callbacks for extra uncore units cleanup + */ + void (*cleanup_extra_boxes)(struct intel_uncore_type *type); }; =20 #define pmu_group attr_groups[0] diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 076ec1efe9cc..866493fda47c 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -215,8 +215,8 @@ uncore_find_unit(struct rb_root *root, unsigned int id) return NULL; } =20 -static void uncore_find_add_unit(struct intel_uncore_discovery_unit *node, - struct rb_root *root, u16 *num_units) +void uncore_find_add_unit(struct intel_uncore_discovery_unit *node, + struct rb_root *root, u16 *num_units) { struct intel_uncore_discovery_unit *unit =3D uncore_find_unit(root, node-= >id); =20 @@ -560,7 +560,7 @@ bool intel_generic_uncore_assign_hw_event(struct perf_e= vent *event, if (!box->pmu->type->boxes) return false; =20 - if (box->pci_dev || box->io_addr) { + if (box->io_addr) { hwc->config_base =3D uncore_pci_event_ctl(box, hwc->idx); hwc->event_base =3D uncore_pci_perf_ctr(box, hwc->idx); return true; @@ -570,16 +570,28 @@ bool intel_generic_uncore_assign_hw_event(struct perf= _event *event, if (!box_ctl) return false; =20 + if (box->pci_dev) { + box_ctl =3D UNCORE_DISCOVERY_PCI_BOX_CTRL(box_ctl); + hwc->config_base =3D box_ctl + uncore_pci_event_ctl(box, hwc->idx); + hwc->event_base =3D box_ctl + uncore_pci_perf_ctr(box, hwc->idx); + return true; + } + hwc->config_base =3D box_ctl + box->pmu->type->event_ctl + hwc->idx; hwc->event_base =3D box_ctl + box->pmu->type->perf_ctr + hwc->idx; =20 return true; } =20 +static inline int intel_pci_uncore_box_ctl(struct intel_uncore_box *box) +{ + return UNCORE_DISCOVERY_PCI_BOX_CTRL(intel_generic_uncore_box_ctl(box)); +} + void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; - int box_ctl =3D uncore_pci_box_ctl(box); + int box_ctl =3D intel_pci_uncore_box_ctl(box); =20 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT); @@ -588,7 +600,7 @@ void intel_generic_uncore_pci_init_box(struct intel_unc= ore_box *box) void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; - int box_ctl =3D uncore_pci_box_ctl(box); + int box_ctl =3D intel_pci_uncore_box_ctl(box); =20 pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ); } @@ -596,7 +608,7 @@ void intel_generic_uncore_pci_disable_box(struct intel_= uncore_box *box) void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; - int box_ctl =3D uncore_pci_box_ctl(box); + int box_ctl =3D intel_pci_uncore_box_ctl(box); =20 pci_write_config_dword(pdev, box_ctl, 0); } @@ -748,6 +760,8 @@ static bool uncore_update_uncore_type(enum uncore_acces= s_type type_id, uncore->box_ctl =3D (unsigned int)UNCORE_DISCOVERY_PCI_BOX_CTRL(type->bo= x_ctrl); uncore->box_ctls =3D type->box_ctrl_die; uncore->pci_offsets =3D type->box_offset; + uncore->boxes =3D &type->units; + uncore->num_boxes =3D type->num_units; break; case UNCORE_ACCESS_MMIO: uncore->ops =3D &generic_uncore_mmio_ops; diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 4a7a7c819d6f..0acf9b681f3b 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -171,3 +171,5 @@ int intel_uncore_find_discovery_unit_id(struct rb_root = *units, int die, unsigned int pmu_idx); bool intel_generic_uncore_assign_hw_event(struct perf_event *event, struct intel_uncore_box *box); +void uncore_find_add_unit(struct intel_uncore_discovery_unit *node, + struct rb_root *root, u16 *num_units); diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index c42b170886d2..fbafc6ea198f 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6198,6 +6198,24 @@ static u64 spr_upi_pci_offsets[SPR_UNCORE_UPI_NUM_BO= XES] =3D { 0, 0x8000, 0x10000, 0x18000 }; =20 +static void spr_extra_boxes_cleanup(struct intel_uncore_type *type) +{ + struct intel_uncore_discovery_unit *pos; + struct rb_node *node; + + if (!type->boxes) + return; + + while (!RB_EMPTY_ROOT(type->boxes)) { + node =3D rb_first(type->boxes); + pos =3D rb_entry(node, struct intel_uncore_discovery_unit, node); + rb_erase(node, type->boxes); + kfree(pos); + } + kfree(type->boxes); + type->boxes =3D NULL; +} + static struct intel_uncore_type spr_uncore_upi =3D { .event_mask =3D SNBEP_PMON_RAW_EVENT_MASK, .event_mask_ext =3D SPR_RAW_EVENT_MASK_EXT, @@ -6212,10 +6230,11 @@ static struct intel_uncore_type spr_uncore_upi =3D { .num_counters =3D 4, .num_boxes =3D SPR_UNCORE_UPI_NUM_BOXES, .perf_ctr_bits =3D 48, - .perf_ctr =3D ICX_UPI_PCI_PMON_CTR0, - .event_ctl =3D ICX_UPI_PCI_PMON_CTL0, + .perf_ctr =3D ICX_UPI_PCI_PMON_CTR0 - ICX_UPI_PCI_PMON_BOX_CTL, + .event_ctl =3D ICX_UPI_PCI_PMON_CTL0 - ICX_UPI_PCI_PMON_BOX_CTL, .box_ctl =3D ICX_UPI_PCI_PMON_BOX_CTL, .pci_offsets =3D spr_upi_pci_offsets, + .cleanup_extra_boxes =3D spr_extra_boxes_cleanup, }; =20 static struct intel_uncore_type spr_uncore_m3upi =3D { @@ -6225,11 +6244,12 @@ static struct intel_uncore_type spr_uncore_m3upi = =3D { .num_counters =3D 4, .num_boxes =3D SPR_UNCORE_UPI_NUM_BOXES, .perf_ctr_bits =3D 48, - .perf_ctr =3D ICX_M3UPI_PCI_PMON_CTR0, - .event_ctl =3D ICX_M3UPI_PCI_PMON_CTL0, + .perf_ctr =3D ICX_M3UPI_PCI_PMON_CTR0 - ICX_M3UPI_PCI_PMON_BOX_CTL, + .event_ctl =3D ICX_M3UPI_PCI_PMON_CTL0 - ICX_M3UPI_PCI_PMON_BOX_CTL, .box_ctl =3D ICX_M3UPI_PCI_PMON_BOX_CTL, .pci_offsets =3D spr_upi_pci_offsets, .constraints =3D icx_uncore_m3upi_constraints, + .cleanup_extra_boxes =3D spr_extra_boxes_cleanup, }; =20 enum perf_uncore_spr_iio_freerunning_type_id { @@ -6516,10 +6536,11 @@ void spr_uncore_cpu_init(void) =20 static void spr_update_device_location(int type_id) { + struct intel_uncore_discovery_unit *unit; struct intel_uncore_type *type; struct pci_dev *dev =3D NULL; + struct rb_root *root; u32 device, devfn; - u64 *ctls; int die; =20 if (type_id =3D=3D UNCORE_SPR_UPI) { @@ -6533,27 +6554,35 @@ static void spr_update_device_location(int type_id) } else return; =20 - ctls =3D kcalloc(__uncore_max_dies, sizeof(u64), GFP_KERNEL); - if (!ctls) { + root =3D kzalloc(sizeof(struct rb_root), GFP_KERNEL); + if (!root) { type->num_boxes =3D 0; return; } + *root =3D RB_ROOT; =20 while ((dev =3D pci_get_device(PCI_VENDOR_ID_INTEL, device, dev)) !=3D NU= LL) { - if (devfn !=3D dev->devfn) - continue; =20 die =3D uncore_device_to_die(dev); if (die < 0) continue; =20 - ctls[die] =3D pci_domain_nr(dev->bus) << UNCORE_DISCOVERY_PCI_DOMAIN_OFF= SET | - dev->bus->number << UNCORE_DISCOVERY_PCI_BUS_OFFSET | - devfn << UNCORE_DISCOVERY_PCI_DEVFN_OFFSET | - type->box_ctl; + unit =3D kzalloc(sizeof(*unit), GFP_KERNEL); + if (!unit) + continue; + unit->die =3D die; + unit->id =3D PCI_SLOT(dev->devfn) - PCI_SLOT(devfn); + unit->addr =3D pci_domain_nr(dev->bus) << UNCORE_DISCOVERY_PCI_DOMAIN_OF= FSET | + dev->bus->number << UNCORE_DISCOVERY_PCI_BUS_OFFSET | + devfn << UNCORE_DISCOVERY_PCI_DEVFN_OFFSET | + type->box_ctl; + + unit->pmu_idx =3D unit->id; + + uncore_find_add_unit(unit, root, NULL); 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14 Jun 2024 06:47:52 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, tim.c.chen@linux.intel.com, Kan Liang Subject: [PATCH V2 7/8] perf/x86/uncore: Cleanup unused unit structure Date: Fri, 14 Jun 2024 06:46:30 -0700 Message-Id: <20240614134631.1092359-8-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240614134631.1092359-1-kan.liang@linux.intel.com> References: <20240614134631.1092359-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The unit control and ID information are retrieved from the unit control RB tree. No one uses the old structure anymore. Remove them. Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 7 +- arch/x86/events/intel/uncore.h | 2 - arch/x86/events/intel/uncore_discovery.c | 110 +++-------------------- arch/x86/events/intel/uncore_discovery.h | 5 -- 4 files changed, 12 insertions(+), 112 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 79449c5b9256..0c724b804e7b 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -868,7 +868,7 @@ static inline int uncore_get_box_id(struct intel_uncore= _type *type, if (type->boxes) return intel_uncore_find_discovery_unit_id(type->boxes, -1, pmu->pmu_idx= ); =20 - return type->box_ids ? type->box_ids[pmu->pmu_idx] : pmu->pmu_idx; + return pmu->pmu_idx; } =20 void uncore_get_alias_name(char *pmu_name, struct intel_uncore_pmu *pmu) @@ -980,10 +980,7 @@ static void uncore_type_exit(struct intel_uncore_type = *type) kfree(type->pmus); type->pmus =3D NULL; } - if (type->box_ids) { - kfree(type->box_ids); - type->box_ids =3D NULL; - } + kfree(type->events_group); type->events_group =3D NULL; } diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 05c429c8cb93..027ef292c602 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -62,7 +62,6 @@ struct intel_uncore_type { unsigned fixed_ctr; unsigned fixed_ctl; unsigned box_ctl; - u64 *box_ctls; /* Unit ctrl addr of the first box of each die */ union { unsigned msr_offset; unsigned mmio_offset; @@ -76,7 +75,6 @@ struct intel_uncore_type { u64 *pci_offsets; u64 *mmio_offsets; }; - unsigned *box_ids; struct event_constraint unconstrainted; struct event_constraint *constraints; struct intel_uncore_pmu *pmus; diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 866493fda47c..571e44b49691 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -89,10 +89,6 @@ add_uncore_discovery_type(struct uncore_unit_discovery *= unit) if (!type) return NULL; =20 - type->box_ctrl_die =3D kcalloc(__uncore_max_dies, sizeof(u64), GFP_KERNEL= ); - if (!type->box_ctrl_die) - goto free_type; - type->units =3D RB_ROOT; =20 type->access_type =3D unit->access_type; @@ -102,12 +98,6 @@ add_uncore_discovery_type(struct uncore_unit_discovery = *unit) rb_add(&type->node, &discovery_tables, __type_less); =20 return type; - -free_type: - kfree(type); - - return NULL; - } =20 static struct intel_uncore_discovery_type * @@ -230,13 +220,10 @@ void uncore_find_add_unit(struct intel_uncore_discove= ry_unit *node, =20 static void uncore_insert_box_info(struct uncore_unit_discovery *unit, - int die, bool parsed) + int die) { struct intel_uncore_discovery_unit *node; struct intel_uncore_discovery_type *type; - unsigned int *ids; - u64 *box_offset; - int i; =20 if (!unit->ctl || !unit->ctl_offset || !unit->ctr_offset) { pr_info("Invalid address is detected for uncore type %d box %d, " @@ -253,79 +240,21 @@ uncore_insert_box_info(struct uncore_unit_discovery *= unit, node->id =3D unit->box_id; node->addr =3D unit->ctl; =20 - if (parsed) { - type =3D search_uncore_discovery_type(unit->box_type); - if (!type) { - pr_info("A spurious uncore type %d is detected, " - "Disable the uncore type.\n", - unit->box_type); - kfree(node); - return; - } - - uncore_find_add_unit(node, &type->units, &type->num_units); - - /* Store the first box of each die */ - if (!type->box_ctrl_die[die]) - type->box_ctrl_die[die] =3D unit->ctl; + type =3D get_uncore_discovery_type(unit); + if (!type) { + kfree(node); return; } =20 - type =3D get_uncore_discovery_type(unit); - if (!type) - goto free_node; - - box_offset =3D kcalloc(type->num_boxes + 1, sizeof(u64), GFP_KERNEL); - if (!box_offset) - goto free_node; - - ids =3D kcalloc(type->num_boxes + 1, sizeof(unsigned int), GFP_KERNEL); - if (!ids) - goto free_box_offset; - uncore_find_add_unit(node, &type->units, &type->num_units); =20 /* Store generic information for the first box */ - if (!type->num_boxes) { - type->box_ctrl =3D unit->ctl; - type->box_ctrl_die[die] =3D unit->ctl; + if (type->num_units =3D=3D 1) { type->num_counters =3D unit->num_regs; type->counter_width =3D unit->bit_width; type->ctl_offset =3D unit->ctl_offset; type->ctr_offset =3D unit->ctr_offset; - *ids =3D unit->box_id; - goto end; } - - for (i =3D 0; i < type->num_boxes; i++) { - ids[i] =3D type->ids[i]; - box_offset[i] =3D type->box_offset[i]; - - if (unit->box_id =3D=3D ids[i]) { - pr_info("Duplicate uncore type %d box ID %d is detected, " - "Drop the duplicate uncore unit.\n", - unit->box_type, unit->box_id); - goto free_ids; - } - } - ids[i] =3D unit->box_id; - box_offset[i] =3D unit->ctl - type->box_ctrl; - kfree(type->ids); - kfree(type->box_offset); -end: - type->ids =3D ids; - type->box_offset =3D box_offset; - type->num_boxes++; - return; - -free_ids: - kfree(ids); - -free_box_offset: - kfree(box_offset); - -free_node: - kfree(node); } =20 static bool @@ -404,7 +333,7 @@ static int parse_discovery_table(struct pci_dev *dev, i= nt die, if (uncore_ignore_unit(&unit, ignore)) continue; =20 - uncore_insert_box_info(&unit, die, *parsed); + uncore_insert_box_info(&unit, die); } =20 *parsed =3D true; @@ -474,7 +403,6 @@ void intel_uncore_clear_discovery_tables(void) rb_erase(node, &type->units); kfree(pos); } - kfree(type->box_ctrl_die); kfree(type); } } @@ -738,41 +666,23 @@ static bool uncore_update_uncore_type(enum uncore_acc= ess_type type_id, struct intel_uncore_discovery_type *type) { uncore->type_id =3D type->type; - uncore->num_boxes =3D type->num_boxes; uncore->num_counters =3D type->num_counters; uncore->perf_ctr_bits =3D type->counter_width; - uncore->box_ids =3D type->ids; + uncore->perf_ctr =3D (unsigned int)type->ctr_offset; + uncore->event_ctl =3D (unsigned int)type->ctl_offset; + uncore->boxes =3D &type->units; + uncore->num_boxes =3D type->num_units; =20 switch (type_id) { case UNCORE_ACCESS_MSR: uncore->ops =3D &generic_uncore_msr_ops; - uncore->perf_ctr =3D (unsigned int)type->ctr_offset; - uncore->event_ctl =3D (unsigned int)type->ctl_offset; - uncore->box_ctl =3D (unsigned int)type->box_ctrl; - uncore->msr_offsets =3D type->box_offset; - uncore->boxes =3D &type->units; - uncore->num_boxes =3D type->num_units; break; case UNCORE_ACCESS_PCI: uncore->ops =3D &generic_uncore_pci_ops; - uncore->perf_ctr =3D (unsigned int)UNCORE_DISCOVERY_PCI_BOX_CTRL(type->b= ox_ctrl) + type->ctr_offset; - uncore->event_ctl =3D (unsigned int)UNCORE_DISCOVERY_PCI_BOX_CTRL(type->= box_ctrl) + type->ctl_offset; - uncore->box_ctl =3D (unsigned int)UNCORE_DISCOVERY_PCI_BOX_CTRL(type->bo= x_ctrl); - uncore->box_ctls =3D type->box_ctrl_die; - uncore->pci_offsets =3D type->box_offset; - uncore->boxes =3D &type->units; - uncore->num_boxes =3D type->num_units; break; case UNCORE_ACCESS_MMIO: uncore->ops =3D &generic_uncore_mmio_ops; - uncore->perf_ctr =3D (unsigned int)type->ctr_offset; - uncore->event_ctl =3D (unsigned int)type->ctl_offset; - uncore->box_ctl =3D (unsigned int)type->box_ctrl; - uncore->box_ctls =3D type->box_ctrl_die; - uncore->mmio_offsets =3D type->box_offset; uncore->mmio_map_size =3D UNCORE_GENERIC_MMIO_SIZE; - uncore->boxes =3D &type->units; - uncore->num_boxes =3D type->num_units; break; default: return false; diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 0acf9b681f3b..0e94aa7db8e7 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -124,18 +124,13 @@ struct intel_uncore_discovery_unit { struct intel_uncore_discovery_type { struct rb_node node; enum uncore_access_type access_type; - u64 box_ctrl; /* Unit ctrl addr of the first box */ - u64 *box_ctrl_die; /* Unit ctrl addr of the first box of each die */ struct rb_root units; /* Unit ctrl addr for all units */ u16 type; /* Type ID of the uncore block */ u8 num_counters; u8 counter_width; u8 ctl_offset; /* Counter Control 0 offset */ u8 ctr_offset; /* Counter 0 offset */ - u16 num_boxes; /* number of boxes for the uncore block */ u16 num_units; /* number of units */ - unsigned int *ids; /* Box IDs */ - u64 *box_offset; /* Box offset */ }; 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X-CSE-ConnectionGUID: vWDflc15Qg6N+11CyQhdsA== X-CSE-MsgGUID: vqu0/whrQ/Wg4cAGNnBEiQ== X-IronPort-AV: E=McAfee;i="6700,10204,11103"; a="19079175" X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="19079175" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 06:47:53 -0700 X-CSE-ConnectionGUID: oZ/SNXioSFWQnJeFwVAFHA== X-CSE-MsgGUID: xifLnIQaQ/WeX0ldZChrFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="40386690" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa006.fm.intel.com with ESMTP; 14 Jun 2024 06:47:52 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, tim.c.chen@linux.intel.com, Kan Liang Subject: [PATCH V2 8/8] perf/x86/intel/uncore: Support HBM and CXL PMON counters Date: Fri, 14 Jun 2024 06:46:31 -0700 Message-Id: <20240614134631.1092359-9-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240614134631.1092359-1-kan.liang@linux.intel.com> References: <20240614134631.1092359-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang Unknown uncore PMON types can be found in both SPR and EMR with HBM or CXL. $ls /sys/devices/ | grep type uncore_type_12_16 uncore_type_12_18 uncore_type_12_2 uncore_type_12_4 uncore_type_12_6 uncore_type_12_8 uncore_type_13_17 uncore_type_13_19 uncore_type_13_3 uncore_type_13_5 uncore_type_13_7 uncore_type_13_9 The unknown PMON types are HBM and CXL PMON. Except for the name, the other information regarding the HBM and CXL PMON counters can be retrieved via the discovery table. Add them into the uncores tables for SPR and EMR. The event config registers for all CXL related units are 8-byte apart. Add SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT to specially handle it. Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_snbep.c | 55 +++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index fbafc6ea198f..4d5933851895 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6162,7 +6162,55 @@ static struct intel_uncore_type spr_uncore_mdf =3D { .name =3D "mdf", }; =20 -#define UNCORE_SPR_NUM_UNCORE_TYPES 12 +static void spr_uncore_mmio_offs8_init_box(struct intel_uncore_box *box) +{ + __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); + intel_generic_uncore_mmio_init_box(box); +} + +static struct intel_uncore_ops spr_uncore_mmio_offs8_ops =3D { + .init_box =3D spr_uncore_mmio_offs8_init_box, + .exit_box =3D uncore_mmio_exit_box, + .disable_box =3D intel_generic_uncore_mmio_disable_box, + .enable_box =3D intel_generic_uncore_mmio_enable_box, + .disable_event =3D intel_generic_uncore_mmio_disable_event, + .enable_event =3D spr_uncore_mmio_enable_event, + .read_counter =3D uncore_mmio_read_counter, +}; + +#define SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT() \ + SPR_UNCORE_COMMON_FORMAT(), \ + .ops =3D &spr_uncore_mmio_offs8_ops + +static struct event_constraint spr_uncore_cxlcm_constraints[] =3D { + UNCORE_EVENT_CONSTRAINT(0x02, 0x0f), + UNCORE_EVENT_CONSTRAINT(0x05, 0x0f), + UNCORE_EVENT_CONSTRAINT(0x40, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x41, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x42, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x43, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0), + UNCORE_EVENT_CONSTRAINT(0x52, 0xf0), + EVENT_CONSTRAINT_END +}; + +static struct intel_uncore_type spr_uncore_cxlcm =3D { + SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), + .name =3D "cxlcm", + .constraints =3D spr_uncore_cxlcm_constraints, +}; + +static struct intel_uncore_type spr_uncore_cxldp =3D { + SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), + .name =3D "cxldp", +}; + +static struct intel_uncore_type spr_uncore_hbm =3D { + SPR_UNCORE_COMMON_FORMAT(), + .name =3D "hbm", +}; + +#define UNCORE_SPR_NUM_UNCORE_TYPES 15 #define UNCORE_SPR_CHA 0 #define UNCORE_SPR_IIO 1 #define UNCORE_SPR_IMC 6 @@ -6186,6 +6234,9 @@ static struct intel_uncore_type *spr_uncores[UNCORE_S= PR_NUM_UNCORE_TYPES] =3D { NULL, NULL, &spr_uncore_mdf, + &spr_uncore_cxlcm, + &spr_uncore_cxldp, + &spr_uncore_hbm, }; =20 /* @@ -6655,7 +6706,7 @@ static struct intel_uncore_type gnr_uncore_b2cmi =3D { }; =20 static struct intel_uncore_type gnr_uncore_b2cxl =3D { - SPR_UNCORE_MMIO_COMMON_FORMAT(), + SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), .name =3D "b2cxl", }; =20 --=20 2.35.1