From nobody Thu Dec 18 21:49:50 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D4C71946CC; Fri, 14 Jun 2024 10:25:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718360748; cv=none; b=ilJb7oY9WVnS19k1ElkTdzVnkAJrQv5JTHcYD1qJ3PJ4hSjOmQ9croaruV7LBW3qjEHudhkIGi8FKVZLHXY0F84ttxd3QDZpk6bNW3otivF4I+cL/hmfGqrBVX75QDuVt5hLLkb33auQFu0yDeQXvuDMRym59KvVz9dDvy2i5dQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718360748; c=relaxed/simple; bh=1cTfACq0ElpLGuB54rvU1+TM97B4xQ9mq7NqWyYTbTY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RAVvN19kZ94SVb4t2BJSK3uUuNsJHfmEJhdh02G2aDp+dCSkCWRc6NuBIgqz8wfLOsh9hdGly9aYY6fntAmjloJGxf3YahLm4wuUTh0woPp03p2FV9v8gx3F6cxXxMuQK5++HKhTD6UflF7KKwPhuqRFUjhrexejY+goGpnQzF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LMHK+efT; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iti74EDo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LMHK+efT"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iti74EDo" From: Shivamurthy Shastri DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1718360745; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9ruApRDwyE/XyhuHw4ObCqk6nkpUiEnJy2HPfoSkyyE=; b=LMHK+efTBHcUjK792bQcYg4ppjUYxz6dXXLKKgMwPa5/cdjD8nuLdLhZV0JXy3N1uUQ5B8 UUtZE0IgA55tSI7+kmqmjyHuyxRX5Vs+Hr0sDrbWvW2DRAI1Kqt97PkKEJuniuDspjUTHi KeHCe0mItqp8+UeYwLTX+4XnckNcavZ3gulEv+0eXOT05ZScsttxySI+eXnY0MeH3Lggqc ySaEIOOcglwb94K4FEpsgy6BYx5CbdCRq+BEAojPCYyhdifAIdGDRYcgHC/5ZJE0c+2Aza SomPnOzxhILmnOYecNG2FVlpMMVWEMlu/4VGBx0q0x0ZHljH88pocyHm7RTLYQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1718360745; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9ruApRDwyE/XyhuHw4ObCqk6nkpUiEnJy2HPfoSkyyE=; b=iti74EDoqRLhWOMUcrG4JG503EYXtLXBqeeLJByqikzEJvE1oQEXaQUgQK8Sa5NQ9w9GQq S/lX9gLbNgYEerCQ== To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, maz@kernel.org, tglx@linutronix.de, anna-maria@linutronix.de, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, bhelgaas@google.com, rdunlap@infradead.org, vidyas@nvidia.com, ilpo.jarvinen@linux.intel.com, apatel@ventanamicro.com, kevin.tian@intel.com, nipun.gupta@amd.com, den@valinux.co.jp, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, gregkh@linuxfoundation.org, rafael@kernel.org, alex.williamson@redhat.com, will@kernel.org, lorenzo.pieralisi@arm.com, jgg@mellanox.com, ammarfaizi2@gnuweeb.org, robin.murphy@arm.com, lpieralisi@kernel.org, nm@ti.com, kristo@kernel.org, vkoul@kernel.org, okaya@kernel.org, agross@kernel.org, andersson@kernel.org, mark.rutland@arm.com, shameerali.kolothum.thodi@huawei.com, yuzenghui@huawei.com, shivamurthy.shastri@linutronix.de Subject: [PATCH v3 15/24] genirq/gic-v3-mbi: Switch to MSI parent Date: Fri, 14 Jun 2024 12:23:54 +0200 Message-Id: <20240614102403.13610-16-shivamurthy.shastri@linutronix.de> In-Reply-To: <20240614102403.13610-1-shivamurthy.shastri@linutronix.de> References: <20240614102403.13610-1-shivamurthy.shastri@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner All platform MSI users and the PCI/MSI code handle per device MSI domains when the irqdomain associated to the device provides MSI parent functionality. Remove the "global" PCI/MSI and platform domain related code and provide the MSI parent functionality by filling in msi_parent_ops. Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Cc: Thomas Gleixner Cc: Marc Zyngier --- v3: enabled MSI_FLAG_PCI_MSI_MASK_PARENT in msi_parent_ops::supported_flags=20 --- drivers/irqchip/irq-gic-v3-mbi.c | 127 +++++++++---------------------- 1 file changed, 35 insertions(+), 92 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-= mbi.c index 19298cc6c2ee..26b95027934e 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -18,6 +18,8 @@ =20 #include =20 +#include "irq-msi-lib.h" + struct mbi_range { u32 spi_start; u32 nr_spis; @@ -29,6 +31,15 @@ static phys_addr_t mbi_phys_base; static struct mbi_range *mbi_ranges; static unsigned int mbi_range_nr; =20 +static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + msg[0].address_hi =3D upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR); + msg[0].address_lo =3D lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); + msg[0].data =3D data->hwirq; + + iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); +} + static struct irq_chip mbi_irq_chip =3D { .name =3D "MBI", .irq_mask =3D irq_chip_mask_parent, @@ -36,11 +47,11 @@ static struct irq_chip mbi_irq_chip =3D { .irq_eoi =3D irq_chip_eoi_parent, .irq_set_type =3D irq_chip_set_type_parent, .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_compose_msi_msg =3D mbi_compose_msi_msg, }; =20 -static int mbi_irq_gic_domain_alloc(struct irq_domain *domain, - unsigned int virq, - irq_hw_number_t hwirq) +static int mbi_irq_gic_domain_alloc(struct irq_domain *domain, unsigned in= t virq, + irq_hw_number_t hwirq) { struct irq_fwspec fwspec; struct irq_data *d; @@ -138,85 +149,31 @@ static void mbi_irq_domain_free(struct irq_domain *do= main, } =20 static const struct irq_domain_ops mbi_domain_ops =3D { + .select =3D msi_lib_irq_domain_select, .alloc =3D mbi_irq_domain_alloc, .free =3D mbi_irq_domain_free, }; =20 -static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) -{ - msg[0].address_hi =3D upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR); - msg[0].address_lo =3D lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); - msg[0].data =3D data->parent_data->hwirq; - - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); -} - -#ifdef CONFIG_PCI_MSI -/* PCI-specific irqchip */ -static void mbi_mask_msi_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void mbi_unmask_msi_irq(struct irq_data *d) -{ - pci_msi_unmask_irq(d); - irq_chip_unmask_parent(d); -} - -static struct irq_chip mbi_msi_irq_chip =3D { - .name =3D "MSI", - .irq_mask =3D mbi_mask_msi_irq, - .irq_unmask =3D mbi_unmask_msi_irq, - .irq_eoi =3D irq_chip_eoi_parent, - .irq_compose_msi_msg =3D mbi_compose_msi_msg, -}; - -static struct msi_domain_info mbi_msi_domain_info =3D { - .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), - .chip =3D &mbi_msi_irq_chip, +#define MBI_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define MBI_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_PCI_MSIX | \ + MSI_FLAG_MULTI_PCI_MSI | \ + MSI_FLAG_PCI_MSI_MASK_PARENT) + +static const struct msi_parent_ops gic_v3_mbi_msi_parent_ops =3D { + .supported_flags =3D MBI_MSI_FLAGS_SUPPORTED, + .required_flags =3D MBI_MSI_FLAGS_REQUIRED, + .bus_select_token =3D DOMAIN_BUS_NEXUS, + .bus_select_mask =3D MATCH_PCI_MSI | MATCH_PLATFORM_MSI, + .prefix =3D "MBI-", + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 -static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain, - struct irq_domain **pci_domain) +static int mbi_allocate_domain(struct irq_domain *parent) { - *pci_domain =3D pci_msi_create_irq_domain(nexus_domain->parent->fwnode, - &mbi_msi_domain_info, - nexus_domain); - if (!*pci_domain) - return -ENOMEM; - - return 0; -} -#else -static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain, - struct irq_domain **pci_domain) -{ - *pci_domain =3D NULL; - return 0; -} -#endif - -/* Platform-MSI specific irqchip */ -static struct irq_chip mbi_pmsi_irq_chip =3D { - .name =3D "pMSI", -}; - -static struct msi_domain_ops mbi_pmsi_ops =3D { -}; - -static struct msi_domain_info mbi_pmsi_domain_info =3D { - .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), - .ops =3D &mbi_pmsi_ops, - .chip =3D &mbi_pmsi_irq_chip, -}; - -static int mbi_allocate_domains(struct irq_domain *parent) -{ - struct irq_domain *nexus_domain, *pci_domain, *plat_domain; - int err; + struct irq_domain *nexus_domain; =20 nexus_domain =3D irq_domain_create_hierarchy(parent, 0, 0, parent->fwnode, &mbi_domain_ops, NULL); @@ -224,22 +181,8 @@ static int mbi_allocate_domains(struct irq_domain *par= ent) return -ENOMEM; =20 irq_domain_update_bus_token(nexus_domain, DOMAIN_BUS_NEXUS); - - err =3D mbi_allocate_pci_domain(nexus_domain, &pci_domain); - - plat_domain =3D platform_msi_create_irq_domain(parent->fwnode, - &mbi_pmsi_domain_info, - nexus_domain); - - if (err || !plat_domain) { - if (plat_domain) - irq_domain_remove(plat_domain); - if (pci_domain) - irq_domain_remove(pci_domain); - irq_domain_remove(nexus_domain); - return -ENOMEM; - } - + nexus_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; + nexus_domain->msi_parent_ops =3D &gic_v3_mbi_msi_parent_ops; return 0; } =20 @@ -302,7 +245,7 @@ int __init mbi_init(struct fwnode_handle *fwnode, struc= t irq_domain *parent) =20 pr_info("Using MBI frame %pa\n", &mbi_phys_base); =20 - ret =3D mbi_allocate_domains(parent); + ret =3D mbi_allocate_domain(parent); if (ret) goto err_free_mbi; =20 --=20 2.34.1