From nobody Mon Feb 9 03:33:09 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E716C19306F; Fri, 14 Jun 2024 10:06:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718359603; cv=none; b=MC4Ws62zsSWWBUlcRyC4E73BOu1sQSaiatE+z6XeQWdAOdil4PkV1eZvvH4aVaK9Fah72KwaOHv2XnCeKcVafpbhFxOmu8aimbMiUdAadEOu5sCCSP6wnWD0R7d8LhlCtug8uU2M9nbYUzYjN3V+MI4GOZ/7TGTrcSyMBtstYFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718359603; c=relaxed/simple; bh=mckqtCbMg/PN3ZmJo/7O6ED7mq8IgQLK63SxG6r+URE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=BIXwKxeoB1AmaxfpyhLKS60FH1Euv3dcrsYDfH0OfCcRfDqW9laj9is19X0wgAUlUBFSBMc5JXUSiPNQPU8bgrpyOGHAE44JPcun3+QNW5k9pQY8ZfiBEqyD3UdRxoTvZZBsEsHfeoxYFO6KbBahCMkZRb6nEmCdnG39hDAt/mE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fj4caFxw; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fj4caFxw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718359602; x=1749895602; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mckqtCbMg/PN3ZmJo/7O6ED7mq8IgQLK63SxG6r+URE=; b=fj4caFxwxNPyQrAh04wK3uPbWszzi9yofttm34TonvfzvNCH4vTxPD0I gtq61Oo14KmHr1GQ0X1CFMk4VQIhj3Ae348C9BIkfE/b3IEtmERxWCR0V hQbgW/W1QdrygzmaUbf0krbS1vI9RBpyb6AHYKscOtU1yHYMWTKHyFEMa 4xpLCwm0RqFI87ljPoZzkshFNHwgv9jozPtT98cXpd2qqBStJ7+3DUHOk YTwjT5eOxu2RrX5F7w0cTdyvcxAvZloGQrltXos6co+lL4JgBIzddqiP5 WYFOUOILyH6VLi6h0CVEhjgPadjcvX9Sn1bfR6Jery/8erYEfdnwrvz48 g==; X-CSE-ConnectionGUID: d/9XMBRXSWG+BQV43q1yOQ== X-CSE-MsgGUID: MxC1DaFMTl+w4OQXgOOc9A== X-IronPort-AV: E=McAfee;i="6700,10204,11102"; a="32715875" X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="32715875" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 03:06:41 -0700 X-CSE-ConnectionGUID: TImz3kKASDuUg/v8cb5+9Q== X-CSE-MsgGUID: E10NB3A5Qn2/WXk2vOYyVg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,237,1712646000"; d="scan'208";a="45575943" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.222]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2024 03:06:36 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Jonathan Cameron , Philipp Stanner , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Thierry Reding , Jonathan Hunter , Robert Richter , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 2/4] PCI: Use resource_set_{range,size}() helpers Date: Fri, 14 Jun 2024 13:06:04 +0300 Message-Id: <20240614100606.15830-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614100606.15830-1-ilpo.jarvinen@linux.intel.com> References: <20240614100606.15830-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert open-coded resource size calculations to use resource_set_{range,size}() helpers. While at it, use SZ_* for size parameter where appropriate which makes the intent of code more obvious. Also, cast sizes to resource_size_t, not u64. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Jonathan Cameron --- drivers/pci/controller/pci-tegra.c | 2 +- drivers/pci/controller/pci-thunder-pem.c | 4 +-- drivers/pci/ecam.c | 2 +- drivers/pci/iov.c | 6 ++-- drivers/pci/pci.c | 3 +- drivers/pci/quirks.c | 20 ++++++-------- drivers/pci/setup-bus.c | 35 ++++++++++-------------- drivers/pci/setup-res.c | 7 ++--- 8 files changed, 34 insertions(+), 45 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pc= i-tegra.c index 038d974a318e..2ce55ed1cd8b 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -1460,7 +1460,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie= *pcie) pcie->cs =3D *res; =20 /* constrain configuration space to 4 KiB */ - pcie->cs.end =3D pcie->cs.start + SZ_4K - 1; + resource_set_size(&pcie->cs, SZ_4K); =20 pcie->cfg =3D devm_ioremap_resource(dev, &pcie->cs); if (IS_ERR(pcie->cfg)) { diff --git a/drivers/pci/controller/pci-thunder-pem.c b/drivers/pci/control= ler/pci-thunder-pem.c index 06a9855cb431..f1bd5de67997 100644 --- a/drivers/pci/controller/pci-thunder-pem.c +++ b/drivers/pci/controller/pci-thunder-pem.c @@ -400,9 +400,9 @@ static int thunder_pem_acpi_init(struct pci_config_wind= ow *cfg) * Reserve 64K size PEM specific resources. The full 16M range * size is required for thunder_pem_init() call. */ - res_pem->end =3D res_pem->start + SZ_64K - 1; + resource_set_size(res_pem, SZ_64K); thunder_pem_reserve_range(dev, root->segment, res_pem); - res_pem->end =3D res_pem->start + SZ_16M - 1; + resource_set_size(res_pem, SZ_16M); =20 /* Reserve PCI configuration space as well. */ thunder_pem_reserve_range(dev, root->segment, &cfg->res); diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c index 1c40d2506aef..260b7de2dbd5 100644 --- a/drivers/pci/ecam.c +++ b/drivers/pci/ecam.c @@ -55,7 +55,7 @@ struct pci_config_window *pci_ecam_create(struct device *= dev, bus_range_max =3D resource_size(cfgres) >> bus_shift; if (bus_range > bus_range_max) { bus_range =3D bus_range_max; - cfg->busr.end =3D busr->start + bus_range - 1; + resource_set_size(&cfg->busr, bus_range); dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR = desired)\n", cfgres, &cfg->busr, busr); } diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index aaa33e8dc4c9..4be402fe9ab9 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -327,8 +327,8 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id) virtfn->resource[i].name =3D pci_name(virtfn); virtfn->resource[i].flags =3D res->flags; size =3D pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); - virtfn->resource[i].start =3D res->start + size * id; - virtfn->resource[i].end =3D virtfn->resource[i].start + size - 1; + resource_set_range(&virtfn->resource[i], + res->start + size * id, size); rc =3D request_resource(res, &virtfn->resource[i]); BUG_ON(rc); } @@ -804,7 +804,7 @@ static int sriov_init(struct pci_dev *dev, int pos) goto failed; } iov->barsz[i] =3D resource_size(res); - res->end =3D res->start + resource_size(res) * total - 1; + resource_set_size(res, resource_size(res) * total); pci_info(dev, "%s %pR: contains BAR %d for %d VFs\n", res_name, res, i, total); i +=3D bar64; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 59e0949fb079..afcd8e49e82c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6559,8 +6559,7 @@ static void pci_request_resource_alignment(struct pci= _dev *dev, int bar, } else { r->flags &=3D ~IORESOURCE_SIZEALIGN; r->flags |=3D IORESOURCE_STARTALIGN; - r->start =3D align; - r->end =3D r->start + size - 1; + resource_set_range(r, align, size); } r->flags |=3D IORESOURCE_UNSET; } diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 568410e64ce6..bde0f5388d06 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include "pci.h" @@ -573,8 +574,7 @@ static void quirk_extend_bar_to_page(struct pci_dev *de= v) const char *r_name =3D pci_resource_name(dev, i); =20 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { - r->end =3D PAGE_SIZE - 1; - r->start =3D 0; + resource_set_range(r, 0, PAGE_SIZE); r->flags |=3D IORESOURCE_UNSET; pci_info(dev, "%s %pR: expanded to page size\n", r_name, r); @@ -593,8 +593,7 @@ static void quirk_s3_64M(struct pci_dev *dev) =20 if ((r->start & 0x3ffffff) || r->end !=3D r->start + 0x3ffffff) { r->flags |=3D IORESOURCE_UNSET; - r->start =3D 0; - r->end =3D 0x3ffffff; + resource_set_range(r, 0, SZ_64M); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3= _64M); @@ -1329,8 +1328,7 @@ static void quirk_dunord(struct pci_dev *dev) struct resource *r =3D &dev->resource[1]; =20 r->flags |=3D IORESOURCE_UNSET; - r->start =3D 0; - r->end =3D 0xffffff; + resource_set_range(r, 0, SZ_16M); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000,= quirk_dunord); =20 @@ -2327,8 +2325,7 @@ static void quirk_tc86c001_ide(struct pci_dev *dev) =20 if (r->start & 0x8) { r->flags |=3D IORESOURCE_UNSET; - r->start =3D 0; - r->end =3D 0xf; + resource_set_range(r, 0, SZ_16); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, @@ -2356,8 +2353,7 @@ static void quirk_plx_pci9050(struct pci_dev *dev) pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid= bit 7 bug\n", bar); r->flags |=3D IORESOURCE_UNSET; - r->start =3D 0; - r->end =3D 0xff; + resource_set_range(r, 0, SZ_256); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, @@ -3509,13 +3505,13 @@ static void quirk_intel_ntb(struct pci_dev *dev) if (rc) return; =20 - dev->resource[2].end =3D dev->resource[2].start + ((u64) 1 << val) - 1; + resource_set_size(&dev->resource[2], (resource_size_t)1 << val); =20 rc =3D pci_read_config_byte(dev, 0x00D1, &val); if (rc) return; =20 - dev->resource[4].end =3D dev->resource[4].start + ((u64) 1 << val) - 1; + resource_set_size(&dev->resource[4], (resource_size_t)1 << val); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 909e6a7c3cc3..004405edf290 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -243,8 +243,7 @@ static void reassign_resources_sorted(struct list_head = *realloc_head, add_size =3D add_res->add_size; align =3D add_res->min_align; if (!resource_size(res)) { - res->start =3D align; - res->end =3D res->start + add_size - 1; + resource_set_range(res, align, add_size); if (pci_assign_resource(add_res->dev, idx)) reset_resource(res); } else { @@ -937,8 +936,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_= size_t min_size, return; } =20 - b_res->start =3D min_align; - b_res->end =3D b_res->start + size0 - 1; + resource_set_range(b_res, min_align, size0); b_res->flags |=3D IORESOURCE_STARTALIGN; if (bus->self && size1 > size0 && realloc_head) { add_to_list(realloc_head, bus->self, b_res, size1-size0, @@ -1127,8 +1125,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, * Reserve some resources for CardBus. We reserve a fixed amount * of bus space for CardBus bridges. */ - b_res->start =3D pci_cardbus_io_size; - b_res->end =3D b_res->start + pci_cardbus_io_size - 1; + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; if (realloc_head) { b_res->end -=3D pci_cardbus_io_size; @@ -1140,8 +1137,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, b_res =3D &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; if (b_res->parent) goto handle_b_res_2; - b_res->start =3D pci_cardbus_io_size; - b_res->end =3D b_res->start + pci_cardbus_io_size - 1; + resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size); b_res->flags |=3D IORESOURCE_IO | IORESOURCE_STARTALIGN; if (realloc_head) { b_res->end -=3D pci_cardbus_io_size; @@ -1174,8 +1170,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, * Otherwise, allocate one region of twice the size. */ if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { - b_res->start =3D pci_cardbus_mem_size; - b_res->end =3D b_res->start + pci_cardbus_mem_size - 1; + resource_set_range(b_res, pci_cardbus_mem_size, + pci_cardbus_mem_size); b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_STARTALIGN; if (realloc_head) { @@ -1192,8 +1188,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus, b_res =3D &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; if (b_res->parent) goto handle_done; - b_res->start =3D pci_cardbus_mem_size; - b_res->end =3D b_res->start + b_res_3_size - 1; + resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size); b_res->flags |=3D IORESOURCE_MEM | IORESOURCE_STARTALIGN; if (realloc_head) { b_res->end -=3D b_res_3_size; @@ -1772,7 +1767,7 @@ static void adjust_bridge_window(struct pci_dev *brid= ge, struct resource *res, return; } =20 - res->end =3D res->start + new_size - 1; + resource_set_size(res, new_size); =20 /* If the resource is part of the add_list, remove it now */ if (add_list) @@ -1935,8 +1930,8 @@ static void pci_bus_distribute_available_resources(st= ruct pci_bus *bus, * what is available). */ align =3D pci_resource_alignment(dev, res); - io.end =3D align ? io.start + ALIGN_DOWN(io_per_b, align) - 1 - : io.start + io_per_b - 1; + resource_set_size(&io, align ? ALIGN_DOWN(io_per_b, align) + : io_per_b); =20 /* * The x_per_b holds the extra resource space that can be @@ -1948,15 +1943,15 @@ static void pci_bus_distribute_available_resources(= struct pci_bus *bus, =20 res =3D &dev->resource[PCI_BRIDGE_MEM_WINDOW]; align =3D pci_resource_alignment(dev, res); - mmio.end =3D align ? mmio.start + ALIGN_DOWN(mmio_per_b, align) - 1 - : mmio.start + mmio_per_b - 1; + resource_set_size(&mmio, align ? ALIGN_DOWN(mmio_per_b, align) + : mmio_per_b); mmio.start -=3D resource_size(res); =20 res =3D &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; align =3D pci_resource_alignment(dev, res); - mmio_pref.end =3D align ? mmio_pref.start + - ALIGN_DOWN(mmio_pref_per_b, align) - 1 - : mmio_pref.start + mmio_pref_per_b - 1; + resource_set_size(&mmio_pref, + align ? ALIGN_DOWN(mmio_pref_per_b, align) + : mmio_pref_per_b); mmio_pref.start -=3D resource_size(res); =20 pci_bus_distribute_available_resources(b, add_list, io, mmio, diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index c6d933ddfd46..ca14576bf2bf 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -211,8 +211,7 @@ static int pci_revert_fw_address(struct resource *res, = struct pci_dev *dev, =20 start =3D res->start; end =3D res->end; - res->start =3D fw_addr; - res->end =3D res->start + size - 1; + resource_set_range(res, fw_addr, size); res->flags &=3D ~IORESOURCE_UNSET; =20 root =3D pci_find_parent_resource(dev, res); @@ -463,7 +462,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) if (ret) return ret; =20 - res->end =3D res->start + pci_rebar_size_to_bytes(size) - 1; + resource_set_size(res, pci_rebar_size_to_bytes(size)); =20 /* Check if the new config works by trying to assign everything. */ if (dev->bus->self) { @@ -475,7 +474,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) =20 error_resize: pci_rebar_set_size(dev, resno, old); - res->end =3D res->start + pci_rebar_size_to_bytes(old) - 1; + resource_set_size(res, pci_rebar_size_to_bytes(old)); return ret; } EXPORT_SYMBOL(pci_resize_resource); --=20 2.39.2