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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 06/21] drm/mediatek: Turn off the layers with zero width or height Date: Fri, 14 Jun 2024 10:46:05 +0800 Message-ID: <20240614024620.19011-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.321300-8.000000 X-TMASE-MatchedRID: bu1PPMrU5TklLXaRonFeEbttJwl7IC+W5TbwqVVpF+NiOMENWKv3dMm/ fWkgSnuR6eam2BAjyzTnYcKpCyR3r6XzgcphDfm8H5YQyOg71ZZMkOX0UoduuX5h6y4KCSJc+xj xs2OXeAZguHEjDCmmHgPWoj/mrDhSVWO7fs8MQC7Da1qWPNOExvpV/0XEKBthmyiLZetSf8nyb6 HMFK1qe3YJEUfDojP/WBd6ltyXuvuU+BjJn6Gia+aEGiPC9uneL0I2I+zGN0c+m7Q7PraiUqTxT 2MLk80ywwkbURPDer405wrSJuSig8jyq973Zc05gc5QdoR+jv6AhOcaQrQ0U1GyRcoeF18qmKP0 zzpTAeGwod8xOMKmvMCBO+zxAW5pftwZ3X11IV0= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.321300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 436BB31C2E4532709AA393D704F92811D184E1352C434136C5CF94B0AA1D23F22000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 777b7bc86a0a ("UPSTREAM: drm/mediatek: Add ovl_adaptor support for M= T8195") Fixes: fa97fe71f6f9 ("UPSTREAM: drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index ecb8246833a7..39bcc73326f0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 29673611fa75..9796fd1d51f2 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -159,7 +159,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (idx >=3D 4) return; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZ= E(idx)); return; } --=20 2.18.0