From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D6BA3201 for ; Fri, 14 Jun 2024 02:46:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333189; cv=none; b=GtwfH6dueGkq7Zr3mRHBmof966G7H+ZFYedb/T2c/bu886wW2EvjrI1mwMUBktVANQASqf1noEafws30iQ9d7A3QJQwNthjDnN+kPeXb03VXS3I7Gm0BzmZzGMQzNvAGW9IxopCPdVRjazmaGZ9mYSctFch4XLZxx+tCYCZqk+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333189; c=relaxed/simple; bh=TI9GKcx7TMqGRUXhEOhVdRzcCG1/S1/FTau2nYfb+p0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t+lWir/ttFAlpuZv2esAXp4LtJwBU4t1U5Oomz+x9KTH+jcRdz2XTggH4VIqz+HE69cl8tiRT5xg4ssf2OxIFgssiOQcQc9HW+HJvG8CWpSshXLl7pnuclQciIVGpKeSK23Iq9x3Sk8ptUGPDStqaYovvw3og+tnO0JuRgdoQTg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=iJ3hBxiL; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iJ3hBxiL" X-UUID: 4982f0f829f811efa22eafcdcd04c131-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VrnEiZMzhbeTqsOlS9Sgz5XKj3UyAknKvFxKQ7N/8V0=; b=iJ3hBxiLYXUqC3cZkmzoswl0C9cEurBhmkuQ4/kWLk4TrOPfCj0jEWs473ShFMLmlPcdho9x7GE66F+N92jHsBwVhEKxa3RIRhfloyssbWJJunZBguZvNszvD2vuBXRTP+8q6+jWWWoVPDBPRLpQZ/rfc+fQyjnbl6fnZCOEeG0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:0bbb7623-0ebd-4bb1-bf43-8a44db40fa33,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:393d96e,CLOUDID:a1fe1185-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4982f0f829f811efa22eafcdcd04c131-20240614 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1638844803; Fri, 14 Jun 2024 10:46:23 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:22 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 01/21] soc: mediatek: Disable 9-bit alpha in ETHDR Date: Fri, 14 Jun 2024 10:46:00 +0800 Message-ID: <20240614024620.19011-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung When 9-bit alpha is enabled, its value will be converted from 0-255 to 0-256 (255 =3D not defined). This is designed for special HDR related calculation, which should be disabled by default, otherwise, alpha blending will not work correctly. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 3 +-- drivers/soc/mediatek/mtk-mmsys.c | 1 + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index ac4132210585..29673611fa75 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -50,7 +50,6 @@ =20 #define MIXER_INX_MODE_BYPASS 0 #define MIXER_INX_MODE_EVEN_EXTEND 1 -#define DEFAULT_9BIT_ALPHA 0x100 #define MIXER_ALPHA_AEN BIT(8) #define MIXER_ALPHA 0xff #define ETHDR_CLK_NUM 13 @@ -169,7 +168,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, - DEFAULT_9BIT_ALPHA, + MIXER_ALPHA, pending->x & 1 ? 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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 02/21] drm/mediatek: Add OVL compatible name for MT8195 Date: Fri, 14 Jun 2024 10:46:01 +0800 Message-ID: <20240614024620.19011-3-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Add OVL compatible name for MT8195. Without this commit, DRM won't work after modifying the device tree. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 610fe1c0a23d..34d1a3aacde5 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -763,6 +763,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8192-disp-ovl", .data =3D (void *)MTK_DISP_OVL }, + { .compatible =3D "mediatek,mt8195-disp-ovl", + .data =3D (void *)MTK_DISP_OVL }, { .compatible =3D "mediatek,mt8183-disp-ovl-2l", .data =3D (void *)MTK_DISP_OVL_2L }, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7A6A184121 for ; Fri, 14 Jun 2024 02:46:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333192; cv=none; b=UmiwRqbe2SXgr8twizzhkFkdYiZyutRE7zPfgT/WxOIBeEfRUuEk2B8XNTPRN+khxsdoEsyJJp2Bnf/8uJGBSla2vCZs30W7UBKBLAiIs+ix5WlF6QjPuqlJZUYrJkjh4KGeQhH5/iuiR7NqsjaIcAALKGhangfCvqc80+cnE1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333192; c=relaxed/simple; bh=v6jiytDVtHyiivA7Ge8empHdmaxu6UTUDxzrajpeTW0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MM8IKjA2WEUvqZAaOEeUJIbHkaGph43WEEYtcsr64p0a8T5F/HnolSVWadC70qUXitD89MvColORd/QY51aRWsk6kQHEPAHnUG/BcL3WJjQ0AKU5hstS/GPnn0ymwSVzp+sK9YFOPKi1nZTAFtiYz06NA9WhRAffxPX5mwhhbvQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=FbPZD0uG; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="FbPZD0uG" X-UUID: 4b6afa3229f811efa22eafcdcd04c131-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=V3C92UuwK8e6w9duRcMMIFA0kj1SNfPRX4QDnnx85jo=; b=FbPZD0uGSNc/WLmSW504aMo8SrA/3ImqkN1qXIdeQ2CwA62QRN/u50pu1MGhl5kHTuiOg3m7knH8QrzlXgEXZeASxkVCr5WXQfSqNN0BQN2HU2LX5G2lJBnyavVrQIB3v7N2KJYBcgfRmfIldjOB7alOzpZQSC1C4B0p0zpYWYw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:3bdf6aaa-bb4e-4971-b36c-1d74f771489f,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:393d96e,CLOUDID:9fc6f893-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES: 1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 4b6afa3229f811efa22eafcdcd04c131-20240614 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1790255519; Fri, 14 Jun 2024 10:46:26 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:22 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , "Bibby Hsieh" , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 03/21] drm/mediatek: Add missing plane settings when async update Date: Fri, 14 Jun 2024 10:46:02 +0800 Message-ID: <20240614024620.19011-4-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.918200-8.000000 X-TMASE-MatchedRID: OgX40jBOMA++g7B0zLCl84zb2GR6Ttd38/hTakhR/NCCsBeCv8CM/eNl jrsvvgvDJZBJhgUbO4znftxNodBrx9m0JHSAKf2wA9lly13c/gHt/okBLaEo+NwQ5VDi3O9Bo8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtpWAvGJ/ULwFBW8LgMmswZUJNg7w8knTeIVlaBsGiozAecR p7tGEPcwkqRRLprSfLwwiKS/7Mw1dnuZPtGJ5FPjOVSX7sckW+wZBgUyJVEbl6Fw8/PpTMRaVvm iAyeA2kc5MSfkiJFI5p3LlElBHTlw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.918200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 897ED056EA6719E8EF52DC5115A0F01C163687F9D63FCD59976AE5BA9BC937482000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Fix an issue that plane coordinate was not saved when calling async update. Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic up= date") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_plane.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 95e1b17091f0..d20770162736 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -228,6 +228,8 @@ static void mtk_plane_atomic_async_update(struct drm_pl= ane *plane, plane->state->src_y =3D new_state->src_y; plane->state->src_h =3D new_state->src_h; plane->state->src_w =3D new_state->src_w; + plane->state->dst.x1 =3D new_state->dst.x1; + plane->state->dst.y1 =3D new_state->dst.y1; =20 mtk_plane_update_new_state(new_state, new_plane_state); swap(plane->state->fb, new_state->fb); --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C61161836F9 for ; Fri, 14 Jun 2024 02:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333190; cv=none; b=CpwyKDed11IusauHQO3jaYfW9t1iMKOYy0GPrtjnOA89IgrkipikM1wEpNkPbRSWacYftfiLE8HeRmDpDAwXMS/97d00mL15FDIyaJDyxaNxQEItd8p4uj1+nAJz2JL2tw0GmM3mJCNNS8SZIZjlCt9V0N8rfl7/egw9IsvN4AI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333190; c=relaxed/simple; bh=UTsBO1qXZUduXiFWMlA85vB3ALhlyPZgNWdVdj9oB0w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TWmZ9RiubumNkILmZkITgLniqOF9hgxzJG1W6Lt1JSftaBKxQ10i7orfczlF5FexqIcLRcM0qTWjtb8AUbL/0cu9x526vAD67bnDqj8pujzAPAdQ2kxDAJprEQQ27kUf3vq5G8cgxNFdi9tyjsyUV7081w8N1Kx8PnPvjLhFYec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=MYL07Jtt; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MYL07Jtt" X-UUID: 496a007029f811efa22eafcdcd04c131-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=q1VEYsaTRBuapIDGlm2Ds9ITMgUQ0qhzoxCFj/P5Sug=; b=MYL07JttS/BA0nMDmle7dsAGkb7Mv/2w6eRX1m1iyJkzsEO8gePKkRW/XcYsv/04bRnQp2VY5yFh+jUEaq/MlYEbxwxGZpg/+rmiwlb+9sOP/5lrA1270yvSGM+0/jzSF5C2VNScjnRvrxTt2HPmott4Vh/Ly/oAvH+kNbT4A/E=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:1a00732c-2686-4d1e-b9f1-6490829a7bb8,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:393d96e,CLOUDID:94df9188-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 496a007029f811efa22eafcdcd04c131-20240614 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1757014030; Fri, 14 Jun 2024 10:46:23 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:22 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 04/21] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property Date: Fri, 14 Jun 2024 10:46:03 +0800 Message-ID: <20240614024620.19011-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Always add DRM_MODE_ROTATE_0 to rotation property to meet IGT's (Intel GPU Tools) requirement. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 6 +++++- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------ drivers/gpu/drm/mediatek/mtk_plane.c | 2 +- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 792fd1b004ee..2d9cdcb7100c 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -193,7 +193,11 @@ unsigned int mtk_ddp_comp_supported_rotations(struct m= tk_ddp_comp *comp) if (comp->funcs && comp->funcs->supported_rotations) return comp->funcs->supported_rotations(comp->dev); =20 - return 0; + /* + * In order to pass IGT tests, DRM_MODE_ROTATE_0 is required when + * rotation is not supported. + */ + return DRM_MODE_ROTATE_0; } =20 static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 14c9b30c599b..20faac97f910 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -296,27 +296,20 @@ int mtk_ovl_layer_check(struct device *dev, unsigned = int idx, struct mtk_plane_state *mtk_state) { struct drm_plane_state *state =3D &mtk_state->base; - unsigned int rotation =3D 0; =20 - rotation =3D drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - rotation &=3D ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) !=3D 0) + /* check if any unsupported rotation is set */ + if (state->rotation & ~mtk_ovl_supported_rotations(dev)) return -EINVAL; =20 /* * TODO: Rotating/reflecting YUV buffers is not supported at this time. * Only RGB[AX] variants are supported. + * Since DRM_MODE_ROTATE_0 means "no rotation", we should not + * reject layers with this property. */ - if (state->fb->format->is_yuv && rotation !=3D 0) + if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) return -EINVAL; =20 - state->rotation =3D rotation; - return 0; } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index d20770162736..713e17473930 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -346,7 +346,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_p= lane *plane, return err; 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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 05/21] drm/mediatek: Set DRM mode configs accordingly Date: Fri, 14 Jun 2024 10:46:04 +0800 Message-ID: <20240614024620.19011-6-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Set DRM mode configs limitation according to the hardware capabilities and pass the IGT checks as below: - The test "graphics.IgtKms.kms_plane" requires a frame buffer with width of 4512 pixels (> 4096). - The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is defined, and run the test with cursor size from 1x1 to 512x512. Please notice that the test conditions may change as IGT is updated. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 34d1a3aacde5..3737180e1e53 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -298,6 +298,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .conn_routes =3D mt8188_mtk_ddp_main_routes, .num_conn_routes =3D ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { @@ -312,6 +315,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 0_driver_data =3D { .main_path =3D mt8195_mtk_ddp_main, .main_len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 1, + .min_height =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data =3D { @@ -319,6 +325,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 1_driver_data =3D { .ext_len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), .mmsys_id =3D 1, .mmsys_dev_num =3D 2, + .max_width =3D 8191, + .min_width =3D 2, /* 2-pixel align when ethdr is bypassed */ + .min_height =3D 1, }; =20 static const struct of_device_id mtk_drm_of_ids[] =3D { @@ -497,6 +506,15 @@ static int mtk_drm_kms_init(struct drm_device *drm) for (j =3D 0; j < private->data->mmsys_dev_num; j++) { priv_n =3D private->all_drm_private[j]; =20 + if (priv_n->data->max_width) + drm->mode_config.max_width =3D priv_n->data->max_width; + + if (priv_n->data->min_width) + drm->mode_config.min_width =3D priv_n->data->min_width; + + if (priv_n->data->min_height) + drm->mode_config.min_height =3D priv_n->data->min_height; + if (i =3D=3D CRTC_MAIN && priv_n->data->main_len) { ret =3D mtk_crtc_create(drm, priv_n->data->main_path, priv_n->data->main_len, j, @@ -524,6 +542,10 @@ static int mtk_drm_kms_init(struct drm_device *drm) } } =20 + /* IGT will check if the cursor size is configured */ + drm->mode_config.cursor_width =3D drm->mode_config.max_width; + drm->mode_config.cursor_height =3D drm->mode_config.max_height; + /* Use OVL device for all DMA memory allocations */ crtc =3D drm_crtc_from_index(drm, 0); if (crtc) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 78d698ede1bf..ce897984de51 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,10 @@ struct mtk_mmsys_driver_data { bool shadow_register; unsigned int mmsys_id; unsigned int mmsys_dev_num; + + u16 max_width; + u16 min_width; + u16 min_height; }; =20 struct mtk_drm_private { --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7753A8479 for ; Fri, 14 Jun 2024 02:46:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; 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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 06/21] drm/mediatek: Turn off the layers with zero width or height Date: Fri, 14 Jun 2024 10:46:05 +0800 Message-ID: <20240614024620.19011-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.321300-8.000000 X-TMASE-MatchedRID: bu1PPMrU5TklLXaRonFeEbttJwl7IC+W5TbwqVVpF+NiOMENWKv3dMm/ fWkgSnuR6eam2BAjyzTnYcKpCyR3r6XzgcphDfm8H5YQyOg71ZZMkOX0UoduuX5h6y4KCSJc+xj xs2OXeAZguHEjDCmmHgPWoj/mrDhSVWO7fs8MQC7Da1qWPNOExvpV/0XEKBthmyiLZetSf8nyb6 HMFK1qe3YJEUfDojP/WBd6ltyXuvuU+BjJn6Gia+aEGiPC9uneL0I2I+zGN0c+m7Q7PraiUqTxT 2MLk80ywwkbURPDer405wrSJuSig8jyq973Zc05gc5QdoR+jv6AhOcaQrQ0U1GyRcoeF18qmKP0 zzpTAeGwod8xOMKmvMCBO+zxAW5pftwZ3X11IV0= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.321300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 436BB31C2E4532709AA393D704F92811D184E1352C434136C5CF94B0AA1D23F22000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung We found that IGT (Intel GPU Tool) will try to commit layers with zero width or height and lead to undefined behaviors in hardware. Disable the layers in such a situation. Fixes: 777b7bc86a0a ("UPSTREAM: drm/mediatek: Add ovl_adaptor support for M= T8195") Fixes: fa97fe71f6f9 ("UPSTREAM: drm/mediatek: Add ETHDR support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index ecb8246833a7..39bcc73326f0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; =20 - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { mtk_merge_stop_cmdq(merge, cmdq_pkt); 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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 07/21] drm/mediatek: Support more 10bit formats in OVL Date: Fri, 14 Jun 2024 10:46:06 +0800 Message-ID: <20240614024620.19011-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.049500-8.000000 X-TMASE-MatchedRID: B7xIh5hTocBURz1zjvDwXGNW0DAjL5p+Wot5Z16+u77YgrGDwuFJdvlY oV6p/cSxvvJoxo0uTMSN/3dDbj3CNYpsQeZV7e/ejtK7dC6UBnm5+1figft3Lpsoi2XrUn/Jn6K dMrRsL14qtq5d3cxkNVM+K9HKQZqORz3Zpy8z1laTio96HttPkRjni6QORDoz0H4t6uVZq+0= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.049500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B641DA7291654C8B41B03CA92D6E266D353995BC9A60B46C5265FC9135DB1E452000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support more 10bit formats in OVL. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 ++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 20faac97f910..878bfb966ed7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -71,6 +71,22 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) =20 +static inline bool is_10bit_rgb(u32 fmt) +{ + switch (fmt) { + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + return true; + } + return false; +} + static const u32 mt8173_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -88,12 +104,18 @@ static const u32 mt8173_formats[] =3D { static const u32 mt8195_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRX1010102, DRM_FORMAT_BGRA1010102, DRM_FORMAT_ABGR8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX1010102, + DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, DRM_FORMAT_RGB565, @@ -253,9 +275,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, i= nt idx, u32 format, reg =3D readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); reg &=3D ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); =20 - if (format =3D=3D DRM_FORMAT_RGBA1010102 || - format =3D=3D DRM_FORMAT_BGRA1010102 || - format =3D=3D DRM_FORMAT_ARGB2101010) + if (is_10bit_rgb(format)) bit_depth =3D OVL_CON_CLRFMT_10_BIT; =20 reg |=3D OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); @@ -368,17 +388,23 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; 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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 08/21] drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195 Date: Fri, 14 Jun 2024 10:46:07 +0800 Message-ID: <20240614024620.19011-9-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support RGBA8888 and RGBX8888 formats in OVL on MT8195. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 878bfb966ed7..946b87ec48ca 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -114,6 +114,8 @@ static const u32 mt8195_formats[] =3D { DRM_FORMAT_XBGR8888, DRM_FORMAT_XBGR2101010, DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX1010102, DRM_FORMAT_RGBA1010102, DRM_FORMAT_RGB888, --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 824E8184114 for ; Fri, 14 Jun 2024 02:46:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333192; cv=none; b=XuiyiOct9myaEmZ4IniMZlPNqr+M130YtFKAd+Qmm9451vQcLXH3vab4nA9fBfaaWE4v0u6gnLTvZ3jF206vGveZhvYe8HBHXfteuAzpK1I8zSchQU5Rfq8xdYTk6px9Mf50SWW8SOtQfVto3W6WpWI3gx6BfwnNMGXnjAK6U6o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333192; c=relaxed/simple; bh=h7qkTDcDvM81yW0Q4HeerFpQ2fQxn5NQ1Wwb84eJJNA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QuxsuhdIg/PxbRqoT7X2Az/6JPx/cqyPsO1mhE8sDBId8IaDuCeLeuKQvF6aezN9VNFkr+HC+/rguToRWiL7Re4m8OtJYkRbvmcJfxV7zoGlyCs6ANStvxpRXPLAHxvgIzjTBBZ13m85tWquEeiUYCQhW9qzn1fTZIU/m8GpKqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=UoLiLvMk; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="UoLiLvMk" X-UUID: 4b6e66ea29f811efa22eafcdcd04c131-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=l/o9K3vrdwxYHQkFOoOv4lDaI8xltdq3SzLh9rTzdiE=; b=UoLiLvMkFGEm3oA4txwxIjyvtxjmrA2ztuyQxAZnjueB62lRMSUPlgEqrvDcqhFqeFKt2EUvrhTWhhif6CrIz9NUL+Fxt3rq6ES6Emt3iy3t/fxT1WQ97X9pq30AagIO0j3QPuU0IuJhxOvhbqzNKAld1GDIKm/TLmVgu8ex49s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:a127629c-64be-4bf4-8491-405a1ecc6b9a,IP:0,U RL:0,TC:0,Content:-25,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:-55 X-CID-META: VersionHash:393d96e,CLOUDID:bb3d8f44-4544-4d06-b2b2-d7e12813c598,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4b6e66ea29f811efa22eafcdcd04c131-20240614 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 660319255; Fri, 14 Jun 2024 10:46:26 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:23 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , "Bibby Hsieh" , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 09/21] drm/mediatek: Fix XRGB setting error in OVL Date: Fri, 14 Jun 2024 10:46:08 +0800 Message-ID: <20240614024620.19011-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--10.300700-8.000000 X-TMASE-MatchedRID: YlFttd9FXlxk8mKJ5urUT/SZ/2axrnPBMZpQS7dE0dbn3ZLCt3rRSU/3 ZkXeY1OAief1bXK4GioSqo3ZUfrHh25/NyTKlG69y7TSWcbz49aH7D1bP/FcOmI4wQ1Yq/d0ixZ NU2JZ49sDpwq8Ju73uXQp8BZ5yX4A0gsu93e+95/uykw7cfAoIPpV/0XEKBthmyiLZetSf8mfop 0ytGwvXiq2rl3dzGQ1qdk2nO+ebu9cJj1z0Bi0+OOtQE7p5cguXENRtXAnSsoLfLq6W2rnbw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--10.300700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 9207DF7928467F56B1EFB7B01E56E301FF6EA7079216B570293EEBCFCB9E80B62000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung CONST_BLD must be enabled for XRGB formats although the alpha channel can be ignored, or OVL will still read the value from memory. This error only affects CRC generation. Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver= ") Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 946b87ec48ca..fd390fb83d0e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -38,6 +38,7 @@ #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) +#define OVL_CONST_BLEND BIT(28) #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 @@ -428,6 +429,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; union overlay_pitch { @@ -449,6 +451,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, if (state->base.fb && state->base.fb->format->has_alpha) con |=3D OVL_CON_AEN | OVL_CON_ALPHA; =20 + /* CONST_BLD must be enabled for XRGB formats although the alpha channel + * can be ignored, or OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (state->base.fb && !state->base.fb->format->has_alpha) + ignore_pixel_alpha =3D OVL_CONST_BLEND; + if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; addr +=3D (pending->height - 1) * pending->pitch; @@ -464,8 +474,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq= _reg, ovl->regs, - DISP_REG_OVL_PITCH(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pi= xel_alpha, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD7971850B3 for ; Fri, 14 Jun 2024 02:46:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333194; cv=none; b=cJ+fargGIFkV89TCTxqxL54ouul9ESzVHHmiMu4pRezBRea6O/ZYezpvimCVRZwGA4lp4n8tjEqWO8zEuR9WW3M7TIH0NcxbnlgNrarGzkggAoiLs31i8oB9ky2hUGnYukVwLXU8A9JbBuzD+Fvn1byuvjUll64t0p9wiGzE29k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333194; c=relaxed/simple; bh=+iPBECd+g2hUqYzlijq8QgoWl7j2fHLJQBlqQspzKO0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gBaqlkxfbzXXDxXfvOjuLMBIVD6Ya7NgkQbA9YADRuhZuCKgfuMlfCFmBQYNQglxozIAANDprI9KA9PYjP+4lpjTmkQ6a0e4WWwsm3q4AEgHvSxUAZ5HwNTMfOMAvKl87hTuxNRDhJ3CRE0NozcJkUExBhRXH6xenBwWViklD0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=BJg6bZuq; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="BJg6bZuq" X-UUID: 49e7a5f229f811efa54bbfbb386b949c-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DjFKUi2wtajmjAzUBQErieaH7TUuWPwc9BP5pjVN8B0=; b=BJg6bZuq69GHhvKGH5rFMYJ7NvZk2eEmL87TQGcySarIjIbSM5H7ETFc76hj6ItY+B2zFcviwl4F22jlgKr3SURr8jM1M+AF+fdZBHdn5y5UK+oM3164nrTpVohuX9HF19Sb1sYJE07OK9YsrO5l3r5GsK6Lr5bqp7buMaH1AIQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:6c6e3b65-9400-441b-8817-62a19cea6f43,IP:0,U RL:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-35 X-CID-META: VersionHash:393d96e,CLOUDID:c4df9188-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 49e7a5f229f811efa54bbfbb386b949c-20240614 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 234012777; Fri, 14 Jun 2024 10:46:24 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 13 Jun 2024 19:46:23 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:23 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 10/21] drm/mediatek: Fix XRGB setting error in Mixer Date: Fri, 14 Jun 2024 10:46:09 +0800 Message-ID: <20240614024620.19011-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Although the alpha channel in XRGB formats can be ignored, ALPHA_CON must be configured accordingly when using XRGB formats or it will still affects CRC generation. Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195") Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 9796fd1d51f2..902dec03a7dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -153,6 +153,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, unsigned int offset =3D (pending->x & 1) << 31 | pending->y << 16 | pendi= ng->x; unsigned int align_width =3D ALIGN_DOWN(pending->width, 2); unsigned int alpha_con =3D 0; + bool replace_src_a =3D false; =20 dev_dbg(dev, "%s+ idx:%d", __func__, idx); =20 @@ -172,8 +173,15 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, if (state->base.fb && state->base.fb->format->has_alpha) alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; =20 - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, - MIXER_ALPHA, + if (state->base.fb && !state->base.fb->format->has_alpha) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a =3D true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_= ALPHA, pending->x & 1 ? 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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 11/21] drm/mediatek: Add new color format MACROs in OVL Date: Fri, 14 Jun 2024 10:46:10 +0800 Message-ID: <20240614024620.19011-12-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.032700-8.000000 X-TMASE-MatchedRID: B7xIh5hTocA/mJEvNFL+dbqQyAveNtg65hCwQ3LNHZ0vM0Gdq0fzqfMT uIrC6WWhPkn/V88HF8sSqo3ZUfrHh5Coy9iDotiwHcQQBuf4ZFvtMsBKGEjbqZsoi2XrUn/Jn6K dMrRsL14qtq5d3cxkNWqnMjmJR+9JCQBf3hdsghh5wY7hpybcOB9VaJFic4bCpj6vpo5Zq+s= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.032700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 840A6161F61534913DE749BAA662769628037593C2C1F54BF2FFFC234EF60B802000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Define new color formats to hide the bit operation in the MACROs to make the switch statement more concise. Change the MACROs to align the naming rule in DRM. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index fd390fb83d0e..1923bbd96014 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -55,8 +55,10 @@ #define OVL_CON_BYTE_SWAP BIT(24) #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB (1 << 12) -#define OVL_CON_CLRFMT_RGBA8888 (2 << 12) -#define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_ARGB8888 (2 << 12) +#define OVL_CON_CLRFMT_RGBA8888 (3 << 12) +#define OVL_CON_CLRFMT_ABGR8888 (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SW= AP) +#define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SW= AP) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -393,22 +395,22 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) case DRM_FORMAT_RGBA8888: case DRM_FORMAT_RGBX1010102: case DRM_FORMAT_RGBA1010102: - return OVL_CON_CLRFMT_ARGB8888; + return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: - return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_CLRFMT_BGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - return OVL_CON_CLRFMT_RGBA8888; + return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + return OVL_CON_CLRFMT_ABGR8888; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20621184126 for ; Fri, 14 Jun 2024 02:46:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333193; cv=none; b=d/kaXBhcFpX5G/zMhCKrNFAUio+DvuaAa4lop4zf94bXEahga04T5R/JIs77bUbhjzYdbXkTA4arqfbKImPMw1GuMVYodl2rD8p9MUq3U+b4r0+95ALPcWzaN5PZTgsmiHHCkXewt2JsSeNHMx7TWYjY+LinO+T60rf/0m+PsLA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333193; c=relaxed/simple; bh=Dbgk/yS5uy6GQVFaPI5W8rBUT0ppa+EieurkgWDxeac=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tEhCRK+cVa/KjiZ+mPg4eVTVqTIH6KSO4RCd928qXSNfgyt15jVAnmdI8PWWgnYMM6q3/wEPGqBT4tj/v4/IEFut7QZHf5jqF1k18BYORohmjjdWNbkN2vgU3EQbs8KZyexAUdt18h0yU8UPFfuVMV1eUcGHBtLh2bi9w1OzGIc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=G6YRFFYs; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="G6YRFFYs" X-UUID: 4a84278829f811efa54bbfbb386b949c-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=P2qkrOr5qvVcuU8Akj5R1+oKaguq9iNgCCld5Y8r5lk=; b=G6YRFFYshJCf9sCTTFJt+9P3OcFG/6hjS4G8gmIGrp8FCreMN/qQPnCXBC3dpTKpnjmUpl4SoX2qBLCopIKVEDBiiFsrP1k5xTTzGp6+tI/14ExTJHodH6LwYTmiL/LfeRvCT7geWjGv64nbFaIZD5t/9yMEXlImQDlejNcrakc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:72fc24cc-9937-4d39-9ceb-496567f4fcee,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:393d96e,CLOUDID:c5df9188-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4a84278829f811efa54bbfbb386b949c-20240614 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 720227250; Fri, 14 Jun 2024 10:46:25 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:23 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 12/21] drm/mediatek: Support DRM plane alpha in OVL Date: Fri, 14 Jun 2024 10:46:11 +0800 Message-ID: <20240614024620.19011-13-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Set the plane alpha according to DRM plane property. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 1923bbd96014..2316d4a6dca7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -450,8 +450,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, } =20 con =3D ovl_fmt_convert(ovl, fmt); - if (state->base.fb && state->base.fb->format->has_alpha) - con |=3D OVL_CON_AEN | OVL_CON_ALPHA; + if (state->base.fb) { + con |=3D OVL_CON_AEN; + con |=3D state->base.alpha & OVL_CON_ALPHA; + } =20 /* CONST_BLD must be enabled for XRGB formats although the alpha channel * can be ignored, or OVL will still read the value from memory. --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 201E3186E3A for ; Fri, 14 Jun 2024 02:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333195; cv=none; b=r+0GxrhOEv6knLyWL/9Iyd8ZZdREDsiWd9gfxHDgQ+0kSEQjDmsvy1jKcZAvtsp2h0Gr0D4RiprP7jK3mIl05zNPXYXKma8PpWNxENV6C8i39mVCO+x7vUnBCJ+x3OUrAaM2/TBL6MeN8K4GNoOucBxaEO9d9wWZ7p8V4CVrOEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333195; c=relaxed/simple; bh=O9KZOHgPNTuNTVMzQClAklJ1R17kkW6CjDWPmaPteEE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q6Xc5QY7MyJzThRpP/8MKY2odNX2OL4EQ+4a/vD6NuX+FkN48hBtFfBieyoLa634egYCBILA3wonfK+RkHad20HVIBcczbT5sto3Gbo+MEb382+IKEFQD6hvpYrq04loBFLqmyJUrwT1/+Z6ttGJO91ZA+brHaQgK3vwU4j4qsw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=c5+F+s/W; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="c5+F+s/W" X-UUID: 4a23fa8429f811efa54bbfbb386b949c-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ouy4lU9oOVI28u04JH2HzIyEL8H3VB78Q2q2iEqMies=; b=c5+F+s/WXjX4zUTOVeyGe+bkTQGu4GaoTfxNWFUgcc2yx+fvnwL3eYjHYRHNC3E6EZ12SgK/LUD/IA7rhTeL6G2GCF+uqkA7iAYCP9OoI/OOrZYHSseGBxreN8XQlkZ0qZAzinYamFmLlV1JkQ8nPStY6MNTIhF5X2yJvmonA8Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:bc3d05b3-0d1a-41bc-a595-183d79d46ed4,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:393d96e,CLOUDID:e8fe1185-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4a23fa8429f811efa54bbfbb386b949c-20240614 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 92460829; Fri, 14 Jun 2024 10:46:24 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:23 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 13/21] drm/mediatek: Support DRM plane alpha in Mixer Date: Fri, 14 Jun 2024 10:46:12 +0800 Message-ID: <20240614024620.19011-14-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Set the plane alpha according to DRM plane property. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 902dec03a7dd..7eaafd44f320 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -170,8 +170,10 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, return; } =20 - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; + if (state->base.fb) { + alpha_con |=3D MIXER_ALPHA_AEN; + alpha_con |=3D state->base.alpha & MIXER_ALPHA; + } =20 if (state->base.fb && !state->base.fb->format->has_alpha) { /* --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF818187547 for ; Fri, 14 Jun 2024 02:46:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333196; cv=none; b=hGfraQ7F/PUpLe6cN8NzZPf9GBNbH3uf/HFbld2yjJnU6GnfEPDyDCTkgRJ3BVddtabPoEBHkANZxo2/lpX35xWVef5Cqqo7+/X0GooKyaLAt5k3LwKjoS5emdBcuE9WxFjlo6yejYa0zkt8VELO2ABMXz4mMikkU9w/J2XWcmc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333196; c=relaxed/simple; bh=REYsVMNMXZTTP7/Vw8gaZi+NbCMSXNkwGH5ntrVRidk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eZxTIMT4zK3vJn7fF04qCg+ra7h2hBtH7cSlxL4Y7Ava9YFS8wR4rYbMHhndpFXMkqA/pxsBEZoF6EV2SK76g7RcvabrlkyVe2kb/R0ZwooSGMmJoYq5SbqWVsWyRI3LDbRK4Izj/KmR1fSGjXeQfJmaUTkFVP9tBJiQLxguX4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=jUVWhhfP; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jUVWhhfP" X-UUID: 4ab5dd4629f811efa54bbfbb386b949c-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=toZI1eMYvUVCsfzTbCuF8F4eC4xSRVwzzC5k4uSZ54g=; b=jUVWhhfPWTuWsQvuAbwaorZRfe2HQbN60Sd77eYtsjsAUWqHw+pPiLFr6D6gWE+HUkokZxpINj5I6TDV6xB//wJ4mH3lur4I3wgrQJJyrcYQ4FSPGGdc5NvNaeiNMirb0+bfk+lHyMKyp4vfGD10YOdgHaFt61JzQE2NkEJpsa4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:c76c087d-8acc-4430-918c-f814330720d1,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:393d96e,CLOUDID:e9fe1185-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4ab5dd4629f811efa54bbfbb386b949c-20240614 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 251409021; Fri, 14 Jun 2024 10:46:25 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:24 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 14/21] drm/mediatek: Support "None" blending in OVL Date: Fri, 14 Jun 2024 10:46:13 +0800 Message-ID: <20240614024620.19011-15-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support "None" alpha blending mode on MediaTek's chips. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 2316d4a6dca7..6567806cf4e2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -431,6 +431,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int blend_mode =3D state->base.pixel_blend_mode; unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; @@ -460,7 +461,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, * For RGB888 related formats, whether CONST_BLD is enabled or not won't * affect the result. Therefore we use !has_alpha as the condition. */ - if (state->base.fb && !state->base.fb->format->has_alpha) + if ((state->base.fb && !state->base.fb->format->has_alpha) || + blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) ignore_pixel_alpha =3D OVL_CONST_BLEND; =20 if (pending->rotation & DRM_MODE_REFLECT_Y) { --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88CC7184136 for ; Fri, 14 Jun 2024 02:46:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333193; cv=none; b=SKngwhA7aeFOt8G8F3UxQ68lkPP9mZLWACp1rUlLU1fCCywZOC+/skBvqAjgKCOoarEtLBoWmLgq3YuEx592MEKGdODtHva3Tw/Rm/We/nq9mEVTwVNmb3thtH6xpN7xYquCaHETIF1cfafQ1YcDJDGMm+Ozrv3wN/tlpYIvxmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333193; c=relaxed/simple; bh=dTggPV7sZaEvU0IiodIBgCnYwX1dIfQGHvo2TqzQqjg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mfakpwUZ/Ji2jyOwvUnWWol074Eu/8XqsjOVBAlyT67ARyRKXhmqCg/CGyfMRysCJZ3JsCEHu3of3ylRqWEJo/4d1NIMO9KZFMcuHVTF0EiFhF09ClbacQailNWs1VpUYSHxYI3riLERKP/4QKzrLp0gWSIY8jwdFLqkLYrV6BI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=VgLrKIl9; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="VgLrKIl9" X-UUID: 4b67c3ee29f811efa22eafcdcd04c131-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dj4y3TjMpJOFW7mABZnCDxfHdozH/Jr9EVuCNDNHtk8=; b=VgLrKIl9bDE3Im93NM1eurOjJLi+zj+q8djYmiWZPOU1JVpv3PG58gblFxeXxQOugWEEtxaz1CK/P6CjvMe0Q0qaxM5MtKdPXoe/HsaqYwJQ5QtQ0Te7QYxqL71aGysuBZ136HWMhWc3sgyMTevVqVC255oLFo8vjEcEfir5QDc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:f35ad39e-4cfc-44f7-b573-557a33c62ff6,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:393d96e,CLOUDID:9ec6f893-e2c0-40b0-a8fe-7c7e47299109,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4b67c3ee29f811efa22eafcdcd04c131-20240614 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1521459447; Fri, 14 Jun 2024 10:46:26 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:24 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , "Bibby Hsieh" , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 15/21] drm/mediatek: Support "None" blending in Mixer Date: Fri, 14 Jun 2024 10:46:14 +0800 Message-ID: <20240614024620.19011-16-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.904600-8.000000 X-TMASE-MatchedRID: B7xIh5hTocDX3tqA7xZNm8ULzBBTAHAlG9Itfzsy8/WOUV82NDH4AlO4 BD7nLMxnTiQecD9aKoSRYJdMgDxPlopsQeZV7e/elUgQqGVMqmwk227IvqakhZsoi2XrUn/Jn6K dMrRsL14qtq5d3cxkNaGL6FinfedKXOIkAKiucmJZmVQnF9pSCWIbWLMPCbj4iY7MY8aB/ufMpj /sWaNtu8RH5snjo2MJUqFRtWIorbGQJHt+yuvvF6DE4wLr4uZ8dATQdtPksR+3/JiWOe6GXXSWg Q2GpXdZbxffl9hhCBw= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.904600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: FD0522F46D4E455882CE90A124D6603712A181DCE2A92C0AF48E82A4F385B26F2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support "None" alpha blending mode on MediaTek's chips. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 7eaafd44f320..907c0ed34c64 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ =20 +#include #include #include #include @@ -175,7 +176,8 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, alpha_con |=3D state->base.alpha & MIXER_ALPHA; } =20 - if (state->base.fb && !state->base.fb->format->has_alpha) { + if ((state->base.fb && !state->base.fb->format->has_alpha) || + state->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) { /* * Mixer doesn't support CONST_BLD mode, * use a trick to make the output equivalent --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C051218C336 for ; Fri, 14 Jun 2024 02:46:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333198; cv=none; b=mtiT4k7+WVU1r44Nxh+iPColiKZFEzkjcc1q5Bl6mrnafyp807DUzFp8KkxBvRQlNqIK6kOzm4W1Sna5fH3Lf4AzMTYlE9wx6qcmJZot89Sk0lEFC6+1yTxOhW1xqR3Sxh+w3pP8aKif3So/7e6VC7GFFN4bULZP4xhrTE/lIK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333198; c=relaxed/simple; bh=YcdZuR+RacmkUA7kfFOnGGSr950smFBvlPHiHrXrVPM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=miuIYNPivUQ7OqdffUsqV1Zz8NUtQUpXkmmI8XNszN6syEyVUFzz3y98Cl39iBG0L1FD5vArP/oaM3lGCxWCVco+QzRV2ERExkTak4Wu6Qov25SR/cTxSbHLDxToH+2/lA7uIhj299Ru11aXhLM1ZpK8nBoUwFPOT8NJV6Lf3HY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=NrmyakvY; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="NrmyakvY" X-UUID: 4c57adb429f811efa54bbfbb386b949c-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wdYlW6V7N1ZnqYspQYd1Bp4Lc0EvqUX5TVai0ZgIkI8=; b=NrmyakvYDCNEfSaQDt/eQIQ6KPPH9t+2LG82R2iPqxVEe6VDgU9yZrPKokOKXqEOGll5IYkt5WQgsCCSUqwowweyOTMIKVW6x8dZza0UjmkM0lpyK8rQnXVbB2A0EE82GoknhJsO4QbT7/de+BAPmta44NQYkHBitkhcn/3GiAc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:bbcde55f-43a7-4fec-9728-852da78e19d6,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:393d96e,CLOUDID:f1df9188-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4c57adb429f811efa54bbfbb386b949c-20240614 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1409050143; Fri, 14 Jun 2024 10:46:28 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:24 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , "Bibby Hsieh" , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 16/21] drm/mediatek: Support "Pre-multiplied" blending in OVL Date: Fri, 14 Jun 2024 10:46:15 +0800 Message-ID: <20240614024620.19011-17-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.881100-8.000000 X-TMASE-MatchedRID: tzdmYTDShTnX3tqA7xZNm8ULzBBTAHAlG9Itfzsy8/XYgrGDwuFJdmb6 PphVtfZg2PMzbXOaAnoaTIVsbS1pG/QPRH4blNMc3fn7n/ZHGqaH7D1bP/FcOkJqedX9vt/ZUfo Sav+4bRBhQDhAoaA0nWnhMuTEcViwrxpSystEXJIdxBAG5/hkW30tCKdnhB589yM15V5aWpj6C0 ePs7A07Xi4XEoPXecx9nksz8t8qUkZaNbuPmnonYrTzSDyjr5uR93lYgjwMSw= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.881100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 97FD793FADBDEEF81A9FAB80CC259AADD20A2DBC9367500A0997AC349DD263AE2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support "Pre-multiplied" alpha blending mode on in OVL. Before this patch, only the "coverage" mode is supported. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 42 ++++++++++++++++++++----- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 6567806cf4e2..47d0b039a616 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -52,8 +52,12 @@ #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) =20 +#define OVL_CON_CLRFMT_MAN BIT(23) #define OVL_CON_BYTE_SWAP BIT(24) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) + +/* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */ +#define OVL_CON_RGB_SWAP BIT(25) + #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_ARGB8888 (2 << 12) #define OVL_CON_CLRFMT_RGBA8888 (3 << 12) @@ -61,6 +65,11 @@ #define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SW= AP) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_CLRFMT_PARGB8888 ((3 << 12) | OVL_CON_CLRFMT_MAN) +#define OVL_CON_CLRFMT_PABGR8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_RGB_S= WAP) +#define OVL_CON_CLRFMT_PBGRA8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_BYTE_= SWAP) +#define OVL_CON_CLRFMT_PRGBA8888 (OVL_CON_CLRFMT_PABGR8888 | OVL_CON_BYTE_= SWAP) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -74,6 +83,8 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) =20 +#define OVL_COLOR_ALPHA GENMASK(31, 24) + static inline bool is_10bit_rgb(u32 fmt) { switch (fmt) { @@ -298,7 +309,13 @@ void mtk_ovl_config(struct device *dev, unsigned int w, if (w !=3D 0 && h !=3D 0) mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_= OVL_ROI_BGCLR); + + /* + * The background color must be opaque black (ARGB), + * otherwise the alpha blending will have no effect + */ + mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_ROI_BGCLR); =20 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); @@ -374,7 +391,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int= idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt) +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, + unsigned int blend_mode) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -395,22 +413,30 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) case DRM_FORMAT_RGBA8888: case DRM_FORMAT_RGBX1010102: case DRM_FORMAT_RGBA1010102: - return OVL_CON_CLRFMT_RGBA8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PRGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: - return OVL_CON_CLRFMT_BGRA8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_BGRA8888 : + OVL_CON_CLRFMT_PBGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - return OVL_CON_CLRFMT_ARGB8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - return OVL_CON_CLRFMT_ABGR8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ABGR8888 : + OVL_CON_CLRFMT_PABGR8888; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: @@ -450,7 +476,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt); + con =3D ovl_fmt_convert(ovl, fmt, blend_mode); if (state->base.fb) { con |=3D OVL_CON_AEN; con |=3D state->base.alpha & OVL_CON_ALPHA; --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF501836FF for ; Fri, 14 Jun 2024 02:46:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333191; cv=none; b=o1hiiVg6uxUssntXq6sNuyiEpWGEhYIRg2eGBUTeuINIaoyDN0ajdFWJ+qRNSNOgwliZH3eImXmpoByiPBeBgJzCueSI2G8Bxyn4vMLEuzLmXIok8dgnNmLmCk/jAO7DjYcMc0htIY/zbQ/lIp38OjwlDL2h0x5zgFF3Igb5BDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333191; c=relaxed/simple; bh=W9mkbK981tdKavozQbDAgBX3AO8YGGD2JX3tkgOjylE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=af6lZ3dA+S/U63iQ9on9wmgGilVYZOfWAqC7QmGlzUFVGFRsrTCGERidWuGLaPNzzJfKyW4tPdC6FveOa6ndyCxImaBr+W4vDgavVH6NhAxg7H5uhi+f1QVvEqzaOJHqz43E3OejhnyhnEik5nutPvhJAW4bEXFZNAh2B19pBr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=e4q5APeN; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="e4q5APeN" X-UUID: 4ada668e29f811efa22eafcdcd04c131-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hZ/Qs0CYaYvctmHej2mww2135O8yTz6EYmrmcl3biZ4=; b=e4q5APeNOz3IPorqD2dhxS0sTphh4SCWjF7CFyOu1sGIu/PrIXBmRcw1wpCDgwd12ZvOVTsjft7NhTzj3tIux/VerJzKyQfStONfXn/f0d9vcDTmrg9zzQgjFUI2bXiJrDIJohCMHx9zSrmOhAH+f/5RkoxvQkFweGnbGG97LBQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:2476f21e-e4c7-4aa3-b20d-3b2cfd6db204,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:393d96e,CLOUDID:e5fe1185-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4ada668e29f811efa22eafcdcd04c131-20240614 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 419297461; Fri, 14 Jun 2024 10:46:25 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 13 Jun 2024 19:46:24 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:24 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 17/21] drm/mediatek: Support "Pre-multiplied" blending in Mixer Date: Fri, 14 Jun 2024 10:46:16 +0800 Message-ID: <20240614024620.19011-18-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support "Pre-multiplied" alpha blending mode in Mixer. Before this patch, only the coverage mode is supported. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 907c0ed34c64..0aa6b23287e5 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -176,6 +178,11 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, alpha_con |=3D state->base.alpha & MIXER_ALPHA; } =20 + if (state->base.pixel_blend_mode !=3D DRM_MODE_BLEND_COVERAGE) + alpha_con |=3D PREMULTI_SOURCE; + else + alpha_con |=3D NON_PREMULTI_SOURCE; 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Fri, 14 Jun 2024 10:46:25 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 13 Jun 2024 19:46:24 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:24 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 18/21] drm/mediatek: Support alpha blending in display driver Date: Fri, 14 Jun 2024 10:46:17 +0800 Message-ID: <20240614024620.19011-19-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support "Pre-multiplied" and "None" blend mode on MediaTek's chips by adding correct blend mode property when the planes init. Before this patch, only the "Coverage" mode (default) is supported. For more information, there are three pixel blend modes in DRM driver: "None", "Pre-multiplied", and "Coverage". To understand the difference between these modes, let's take a look at the following two approaches to do alpha blending: 1. Straight: dst.RGB =3D src.RGB * src.A + dst.RGB * (1 - src.A) This is straightforward and easy to understand, when the source layer is compositing with the destination layer, it's alpha will affect the result. This is also known as "post-multiplied", or "Coverage" mode. 2. Pre-multiplied: dst.RGB =3D src.RGB + dst.RGB * (1 - src.A) Since the source RGB have already multiplied its alpha, only destination RGB need to multiply it. This is the "Pre-multiplied" mode in DRM. For the "None" blend mode in DRM, it means the pixel alpha is ignored when compositing the layers, only the constant alpha for the composited layer will take effects. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_plane.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 713e17473930..9762bba23273 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -354,6 +354,17 @@ int mtk_plane_init(struct drm_device *dev, struct drm_= plane *plane, DRM_INFO("Create rotation property failed\n"); } =20 + err =3D drm_plane_create_alpha_property(plane); + if (err) + DRM_ERROR("failed to create property: alpha\n"); + + err =3D drm_plane_create_blend_mode_property(plane, + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE)); + if (err) + DRM_ERROR("failed to create property: blend_mode\n"); + drm_plane_helper_add(plane, &mtk_plane_helper_funcs); =20 return 0; --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2BD918757F for ; Fri, 14 Jun 2024 02:46:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333198; cv=none; b=mi54w5NIEpXVPWDwdbuzYQ1S0bY48krorRqOo+LZEScxEh1XnHu+DIyoV/NtIbH2yzHNGqv9qkP+DSNuLck+3ryqiGnwqJP0Z1qQoeePlw8FriA8njkLHm/7cgwYw2cPOKg7bYYYUkJlevMCvsknC5dKkcMVs6IsyRAH43cpY5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333198; c=relaxed/simple; bh=o51mMWb0slXLvfWK7eVp7auFMtAjOlqhHg2EQqGvzx4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FDZ0LBvWkw+rubek2mCbh40+i6POHhWoW8aiiiXTCx5xKXU84VBW30pwo7qkZkt/282bwsjurOGZJ6xarD146TkDZIfK4CKlIffyN/wWFsn4sehD7eWSIWAJv7wzN9IpevIacxudlBRS9j+xAngmP2RrNgFBCCX8PivLhNZ3hqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=d+L+m4O7; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="d+L+m4O7" X-UUID: 4b41edea29f811efa54bbfbb386b949c-20240614 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Ao9jS17e9M7jlrIapVQFUckGlNp1mV6mNd4hbF0y6Cs=; b=d+L+m4O7c9ZZXrVhVJfB+38qcJJDVjDv4W+5ldGkXjDnTQ6P8u+DsFgxopyhGiWxOGGyVby41ICZkQWRQqUAFquBPwBPXfz3Vb8pEfOwecGBPGBqz6UmJr7i1wKB7RWuywUsscNoKe6B7TwwiWDzVe1dpy0Y9/bjtx/prJYrawA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:f53a7a4c-bd10-4d33-b7f5-ef2d51cef893,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:393d96e,CLOUDID:c13d8f44-4544-4d06-b2b2-d7e12813c598,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES: 1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 4b41edea29f811efa54bbfbb386b949c-20240614 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 557539261; Fri, 14 Jun 2024 10:46:26 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:24 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , "Bibby Hsieh" , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 19/21] drm/mediatek: Support CRC in display driver Date: Fri, 14 Jun 2024 10:46:18 +0800 Message-ID: <20240614024620.19011-20-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--12.457000-8.000000 X-TMASE-MatchedRID: Cj9nGn0d44FLCiMVfxYIMFVN8laWo90MnhD9A3Sa7pYs/uUAk6xP7MRr vjvFKTaxGJHAl8RgcXDdzcJEB3Zs4ah+3Rlbev+J4bl1FkKDELdaav/yaeMwblwpnAAvAwaz8nC r2kQcW0FH4+svrgES5rAVENKWqLqVv4HUAvTXzN8R7kPXQyW0tiseSAhqf1rRDpCUEeEFm7DeTU cydIM+R0XIqM69vN5fM2ZXtJf8lih55Kivg4hQPhWCVBr+Ay98aN2KuTwsCwIUHVz/b87KIw2yB nqOBZsS1aYQghjejxGDvpNQRtj+jy1+34qxqAZfoS0guoV6SZcuhg66Itb65c2mvbig5LjGIe/o 8I0yOxLhZtas1avqAa0Pj/9cOH4s1RbX+21X57PBVprK8rvWX5Vl8bxyvq1eRQ0dAChl/lzGWez n4kdsTDbd1vp8bzss/VGpY18IOpTrbEGb+5Q/ecqXjImgj58bcnzIcyHHRpokt9BigJAcVoQmEN BkUZwTjhvtkHstsIAMH8agz7oVHMlcp2KsixOJogGd8wIUGIJU3K6aV1ad7Zsoi2XrUn/Jn6KdM rRsL14qtq5d3cxkNd1HmwYL7TlVkKiJstLRW2JMnoefo+a4yggfiZk7OZuBcd5UzlUbuco= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.457000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: F4321D5CBDD4A73D8C9AED354DEA36D1A43A2677FB1EA695C274295B58075B312000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Register CRC related function pointers to support CRC retrieval. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_crtc.c | 279 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_crtc.h | 38 ++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 5 + 3 files changed, 322 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 0df9bf695f65..5dcd8b95b81e 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 #include "mtk_crtc.h" #include "mtk_ddp_comp.h" @@ -74,6 +75,9 @@ struct mtk_crtc { /* lock for display hardware access */ struct mutex hw_lock; bool config_updating; + + struct mtk_ddp_comp *crc_provider; + struct drm_vblank_work crc_work; bool sec_on; }; =20 @@ -894,6 +898,88 @@ static void mtk_crtc_update_output(struct drm_crtc *cr= tc, } } =20 +static void mtk_crtc_crc_work(struct kthread_work *base) +{ + struct drm_vblank_work *work =3D to_drm_vblank_work(base); + struct mtk_crtc *mtk_crtc =3D + container_of(work, typeof(*mtk_crtc), crc_work); + struct mtk_ddp_comp *comp =3D mtk_crtc->crc_provider; + + if (!comp) { + DRM_WARN("%s(crtc-%d): no crc provider\n", + __func__, drm_crtc_index(&mtk_crtc->base)); + return; + } + + if (mtk_crtc->base.crc.opened) { + u64 vblank =3D drm_crtc_vblank_count(&mtk_crtc->base); + + comp->funcs->crc_read(comp->dev); + + /* could take more than 50ms to finish */ + drm_crtc_add_crc_entry(&mtk_crtc->base, true, vblank, + comp->funcs->crc_entry(comp->dev)); + + drm_vblank_work_schedule(&mtk_crtc->crc_work, vblank + 1, true); + } else { + comp->funcs->crc_stop(comp->dev); + } +} + +static int mtk_crtc_set_crc_source(struct drm_crtc *crtc, const char *src) +{ + struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); + struct mtk_ddp_comp *comp =3D mtk_crtc->crc_provider; + + if (!comp) { + DRM_ERROR("%s(crtc-%d): no crc provider\n", + __func__, drm_crtc_index(crtc)); + return -ENOENT; + } + + if (!src) + return -EINVAL; + + if (strcmp(src, "auto") !=3D 0) { + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", + __func__, drm_crtc_index(crtc), src); + return -EINVAL; + } + + comp->funcs->crc_start(comp->dev); + + /* + * skip the first crc because the first frame (vblank + 1) is configured + * by mtk_crtc_ddp_hw_init() when atomic enable + */ + drm_vblank_work_schedule(&mtk_crtc->crc_work, + drm_crtc_vblank_count(crtc) + 2, false); + return 0; +} + +static int mtk_crtc_verify_crc_source(struct drm_crtc *crtc, const char *s= rc, + size_t *cnt) +{ + struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); + struct mtk_ddp_comp *comp =3D mtk_crtc->crc_provider; + + if (!comp) { + DRM_ERROR("%s(crtc-%d): no crc provider\n", + __func__, drm_crtc_index(crtc)); + return -ENOENT; + } + + if (src && strcmp(src, "auto") !=3D 0) { + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", + __func__, drm_crtc_index(crtc), src); + return -EINVAL; + } + + *cnt =3D comp->funcs->crc_cnt(comp->dev); + + return 0; +} + int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state) { @@ -942,6 +1028,8 @@ static void mtk_crtc_atomic_enable(struct drm_crtc *cr= tc, =20 drm_crtc_vblank_on(crtc); mtk_crtc->enabled =3D true; + + drm_vblank_work_init(&mtk_crtc->crc_work, crtc, mtk_crtc_crc_work); } =20 static void mtk_crtc_atomic_disable(struct drm_crtc *crtc, @@ -1035,6 +1123,8 @@ static const struct drm_crtc_funcs mtk_crtc_funcs =3D= { .atomic_destroy_state =3D mtk_crtc_destroy_state, .enable_vblank =3D mtk_crtc_enable_vblank, .disable_vblank =3D mtk_crtc_disable_vblank, + .set_crc_source =3D mtk_crtc_set_crc_source, + .verify_crc_source =3D mtk_crtc_verify_crc_source, }; =20 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs =3D { @@ -1228,6 +1318,13 @@ int mtk_crtc_create(struct drm_device *drm_dev, cons= t unsigned int *path, =20 if (comp->funcs->ctm_set) has_ctm =3D true; + + if (comp->funcs->crc_cnt && + comp->funcs->crc_entry && + comp->funcs->crc_read && + comp->funcs->crc_start && + comp->funcs->crc_stop) + mtk_crtc->crc_provider =3D comp; } =20 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, @@ -1379,3 +1476,185 @@ int mtk_crtc_create(struct drm_device *drm_dev, con= st unsigned int *path, =20 return 0; } + +void mtk_crtc_init_crc(struct mtk_crtc_crc *crc, const u32 *crc_offset_tab= le, + size_t crc_count, u32 reset_offset, u32 reset_mask) +{ + crc->ofs =3D crc_offset_table; + crc->cnt =3D crc_count; + crc->rst_ofs =3D reset_offset; + crc->rst_msk =3D reset_mask; + crc->va =3D kcalloc(crc->cnt, sizeof(*crc->va), GFP_KERNEL); + if (!crc->va) { + DRM_ERROR("failed to allocate memory for crc\n"); + crc->cnt =3D 0; + } +} + +void mtk_crtc_read_crc(struct mtk_crtc_crc *crc, void __iomem *reg) +{ + if (!crc->cnt || !crc->ofs || !crc->va) + return; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + /* sync to see the most up-to-date copy of the DMA buffer */ + dma_sync_single_for_cpu(crc->cmdq_client.chan->mbox->dev, + crc->pa, crc->cnt * sizeof(*crc->va), + DMA_FROM_DEVICE); +#endif +} + +void mtk_crtc_destroy_crc(struct mtk_crtc_crc *crc) +{ + if (!crc->cnt) + return; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (crc->pa) { + dma_unmap_single(crc->cmdq_client.chan->mbox->dev, + crc->pa, crc->cnt * sizeof(*crc->va), + DMA_TO_DEVICE); + crc->pa =3D 0; + } + if (crc->cmdq_client.chan) { + mtk_drm_cmdq_pkt_destroy(&crc->cmdq_handle); + mbox_free_channel(crc->cmdq_client.chan); + crc->cmdq_client.chan =3D NULL; + } +#endif + kfree(crc->va); + crc->va =3D NULL; + crc->cnt =3D 0; +} + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +/** + * mtk_crtc_create_crc_cmdq - Create a CMDQ thread for syncing the CRCs + * @dev: Kernel device node of the CRC provider + * @crc: Pointer of the CRC to init + * + * This function will create a looping thread on GCE (Global Command Engin= e) to + * keep the CRC up to date by monitoring the assigned event (usually the f= rame + * done event) of the CRC provider, and read the CRCs from the registers t= o a + * shared memory for the workqueue to read. To start/stop the looping thre= ad, + * please call `mtk_crtc_start_crc_cmdq()` and `mtk_crtc_stop_crc_cmdq()` + * defined blow. + * + * The reason why we don't update the CRCs with CPU is that the front porc= h of + * 4K60 timing in CEA-861 is less than 60us, and register read/write speed= is + * relatively unreliable comparing to GCE due to the bus design. + * + * We must create a new thread instead of using the original one for plane + * update is because: + * 1. We cannot add another wait-for-event command at the end of cmdq pack= et, or + * the cmdq callback will delay for too long + * 2. Will get the CRC of the previous frame if using the existed wait-for= -event + * command which is at the beginning of the packet + */ +void mtk_crtc_create_crc_cmdq(struct device *dev, struct mtk_crtc_crc *crc) +{ + int i; + + if (!crc->cnt) { + dev_warn(dev, "%s: not support\n", __func__); + goto cleanup; + } + + if (!crc->ofs) { + dev_warn(dev, "%s: not defined\n", __func__); + goto cleanup; + } + + crc->cmdq_client.client.dev =3D dev; + crc->cmdq_client.client.tx_block =3D false; + crc->cmdq_client.client.knows_txdone =3D true; + crc->cmdq_client.client.rx_callback =3D NULL; + crc->cmdq_client.chan =3D mbox_request_channel(&crc->cmdq_client.client, = 0); + if (IS_ERR(crc->cmdq_client.chan)) { + dev_warn(dev, "%s: failed to create mailbox client\n", __func__); + crc->cmdq_client.chan =3D NULL; + goto cleanup; + } + + if (mtk_drm_cmdq_pkt_create(&crc->cmdq_client, &crc->cmdq_handle, PAGE_SI= ZE)) { + dev_warn(dev, "%s: failed to create cmdq packet\n", __func__); + goto cleanup; + } + + if (!crc->va) { + dev_warn(dev, "%s: no memory\n", __func__); + goto cleanup; + } + + /* map the entry to get a dma address for cmdq to store the crc */ + crc->pa =3D dma_map_single(crc->cmdq_client.chan->mbox->dev, + crc->va, crc->cnt * sizeof(*crc->va), + DMA_FROM_DEVICE); + + if (dma_mapping_error(crc->cmdq_client.chan->mbox->dev, crc->pa)) { + dev_err(dev, "%s: failed to map dma\n", __func__); + goto cleanup; + } + + if (crc->cmdq_event) + cmdq_pkt_wfe(&crc->cmdq_handle, crc->cmdq_event, true); + + for (i =3D 0; i < crc->cnt; i++) { + /* put crc to spr1 register */ + cmdq_pkt_read_s(&crc->cmdq_handle, crc->cmdq_reg->subsys, + crc->cmdq_reg->offset + crc->ofs[i], + CMDQ_THR_SPR_IDX1); + + /* copy spr1 register to physical address of the crc */ + cmdq_pkt_assign(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_HIGH(crc->pa + i * sizeof(*crc->va))); + cmdq_pkt_write_s(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_LOW(crc->pa + i * sizeof(*crc->va)), + CMDQ_THR_SPR_IDX1); + } + /* reset crc */ + mtk_ddp_write_mask(&crc->cmdq_handle, ~0, crc->cmdq_reg, 0, + crc->rst_ofs, crc->rst_msk); + + /* clear reset bit */ + mtk_ddp_write_mask(&crc->cmdq_handle, 0, crc->cmdq_reg, 0, + crc->rst_ofs, crc->rst_msk); + + /* jump to head of the cmdq packet */ + cmdq_pkt_jump(&crc->cmdq_handle, crc->cmdq_handle.pa_base); + + return; +cleanup: + mtk_crtc_destroy_crc(crc); +} + +/** + * mtk_crtc_start_crc_cmdq - Start the GCE looping thread for CRC update + * @crc: Pointer of the CRC information + */ +void mtk_crtc_start_crc_cmdq(struct mtk_crtc_crc *crc) +{ + if (!crc->cmdq_client.chan) + return; + + dma_sync_single_for_device(crc->cmdq_client.chan->mbox->dev, + crc->cmdq_handle.pa_base, + crc->cmdq_handle.cmd_buf_size, + DMA_TO_DEVICE); + mbox_send_message(crc->cmdq_client.chan, &crc->cmdq_handle); + mbox_client_txdone(crc->cmdq_client.chan, 0); +} + +/** + * mtk_crtc_stop_crc_cmdq - Stop the GCE looping thread for CRC update + * @crc: Pointer of the CRC information + */ +void mtk_crtc_stop_crc_cmdq(struct mtk_crtc_crc *crc) +{ + if (!crc->cmdq_client.chan) + return; + + /* remove all the commands from the cmdq packet */ + mbox_flush(crc->cmdq_client.chan, 2000); +} +#endif diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek= /mtk_crtc.h index 0b0be01c25f2..fc95209994a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_crtc.h @@ -14,6 +14,34 @@ #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 =20 +/** + * struct mtk_crtc_crc - crc related information + * @ofs: register offset of crc + * @rst_ofs: register offset of crc reset + * @rst_msk: register mask of crc reset + * @cnt: count of crc + * @va: pointer to the start of crc array + * @pa: physical address of the crc for gce to access + * @cmdq_event: the event to trigger the cmdq + * @cmdq_reg: address of the register that cmdq is going to access + * @cmdq_client: handler to control cmdq (mbox channel, thread ...etc.) + * @cmdq_handle: cmdq packet to store the commands + */ +struct mtk_crtc_crc { + const u32 *ofs; + u32 rst_ofs; + u32 rst_msk; + size_t cnt; + u32 *va; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + dma_addr_t pa; + u32 cmdq_event; + struct cmdq_client_reg *cmdq_reg; + struct cmdq_client cmdq_client; + struct cmdq_pkt cmdq_handle; +#endif +}; + void mtk_crtc_commit(struct drm_crtc *crtc); int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path, unsigned int path_len, int priv_data_index, @@ -26,4 +54,14 @@ void mtk_crtc_async_update(struct drm_crtc *crtc, struct= drm_plane *plane, struct drm_atomic_state *plane_state); struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc); =20 +void mtk_crtc_init_crc(struct mtk_crtc_crc *crc, const u32 *crc_offset_tab= le, + size_t crc_count, u32 reset_offset, u32 reset_mask); +void mtk_crtc_read_crc(struct mtk_crtc_crc *crc, void __iomem *reg); +void mtk_crtc_destroy_crc(struct mtk_crtc_crc *crc); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +void mtk_crtc_create_crc_cmdq(struct device *dev, struct mtk_crtc_crc *crc= ); +void mtk_crtc_start_crc_cmdq(struct mtk_crtc_crc *crc); +void mtk_crtc_stop_crc_cmdq(struct mtk_crtc_crc *crc); +#endif + #endif /* MTK_CRTC_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 2d9cdcb7100c..f3250b9567a0 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -89,6 +89,11 @@ struct mtk_ddp_comp_funcs { void (*remove)(struct device *dev, struct mtk_mutex *mutex); unsigned int (*encoder_index)(struct device *dev); enum drm_mode_status (*mode_valid)(struct device *dev, const struct drm_d= isplay_mode *mode); + size_t (*crc_cnt)(struct device *dev); + u32 *(*crc_entry)(struct device *dev); + void (*crc_read)(struct device *dev); + void (*crc_start)(struct device *dev); + void (*crc_stop)(struct device *dev); }; =20 struct mtk_ddp_comp { --=20 2.18.0 From nobody Thu Sep 19 19:39:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E7C918754D for ; Fri, 14 Jun 2024 02:46:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718333197; cv=none; b=JeU0rYYWupnLYno5qKzTgHaik/zxnOSZiuI2y9yAvVX1VbEkK0GUGTL40PQLGw/iw7fX9DcGE0xvzv4fhsrwHfeli74Z00eY/h27M12U+M+XZghoGEGNHlEJnhtx/HLTl8i0BlfWTHhRLCv5vwzQ87Yiygr5jTH30Rberf/RB8g= ARC-Message-Signature: i=1; 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Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 20/21] drm/mediatek: Support CRC in OVL Date: Fri, 14 Jun 2024 10:46:19 +0800 Message-ID: <20240614024620.19011-21-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--18.755200-8.000000 X-TMASE-MatchedRID: A8b3BrqdBHwl5/wzaArBEKKa0xB73sAA7yWPaQc4INS0rcU5V/oSe4yv o/OB/UWI0R+/GIIn918gBcG4U0AQa68O8b+klXu8oMfp2vHck9WRS1J577nsgY8D7T+G1GV/+UG EI8sthRoZB0R4cFpbTeKOmN63egZIkKjL2IOi2LCHZXNSWjgdU09nxZsOR/FTnp9KgXcu34zx32 HnCwVczyACA5ub2VruiIlayt+3hhzD/HB6o7/l2Fz+axQLnAVBMVx/3ZYby79pG3YgOhBCuRsYD extMHGuK2J8/Pd5Ox73liFAN6Qn3gW/eUHwJTrId7Dt86/2u/gHsnt0u0M2AEpv30toAMb6OATX kqj2pKHlztime3+UZcjVNRvJeEXUNq34+vFNn4UshGpBsK6H7rmnDa2zGPi0RQ0dAChl/lzdhEE ZJRcD0S2TF8JaS5nzcBOyDww4NUgfE8yM4pjsDwtuKBGekqUpPjKoPgsq7cA= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--18.755200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 5C887E11E826B64D7F9AAF803D9975B04553B7439DC7F57062EB2A2C81FCC0652000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung We choose OVL as the CRC generator from other hardware components that are also capable of calculating CRCs, since its frame done event triggers vblanks, it can be used as a signal to know when is safe to retrieve CRC of the frame. Please note that position of the hardware component that is chosen as CRC generator in the display path is significant. For example, while OVL is the first module in VDOSYS0, its CRC won't be affected by the modules after it, which means effects applied by PQ, Gamma, Dither or any other components after OVL won't be calculated in CRC generation. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 5 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 5 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 209 ++++++++++++++++++++++-- 3 files changed, 209 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index dc2b36a8bdd6..c583869b110a 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -365,6 +365,11 @@ static const struct mtk_ddp_comp_funcs ddp_ovl =3D { .clk_enable =3D mtk_ovl_clk_enable, .clk_disable =3D mtk_ovl_clk_disable, .config =3D mtk_ovl_config, + .crc_cnt =3D mtk_ovl_crc_cnt, + .crc_entry =3D mtk_ovl_crc_entry, + .crc_read =3D mtk_ovl_crc_read, + .crc_start =3D mtk_ovl_crc_start, + .crc_stop =3D mtk_ovl_crc_stop, .start =3D mtk_ovl_start, .stop =3D mtk_ovl_stop, .register_vblank_cb =3D mtk_ovl_register_vblank_cb, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 082ac18fe04a..a03d7a10847a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -105,6 +105,11 @@ void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); const u32 *mtk_ovl_get_formats(struct device *dev); size_t mtk_ovl_get_num_formats(struct device *dev); +size_t mtk_ovl_crc_cnt(struct device *dev); +u32 *mtk_ovl_crc_entry(struct device *dev); +void mtk_ovl_crc_read(struct device *dev); +void mtk_ovl_crc_start(struct device *dev); +void mtk_ovl_crc_stop(struct device *dev); =20 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex); void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 47d0b039a616..f43b31eec8ad 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -24,12 +24,20 @@ #define OVL_FME_CPL_INT BIT(1) #define DISP_REG_OVL_INTSTA 0x0008 #define DISP_REG_OVL_EN 0x000c +#define OVL_EN BIT(0) +#define OVL_OP_8BIT_MODE BIT(4) +#define OVL_HG_FOVL_CK_ON BIT(8) +#define OVL_HF_FOVL_CK_ON BIT(10) +#define DISP_REG_OVL_TRIG 0x0010 +#define OVL_CRC_EN BIT(8) +#define OVL_CRC_CLR BIT(9) #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 #define OVL_LAYER_SMI_ID_EN BIT(0) #define OVL_BGCLR_SEL_IN BIT(2) #define OVL_LAYER_AFBC_EN(n) BIT(4+n) +#define OVL_OUTPUT_CLAMP BIT(26) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) @@ -42,7 +50,26 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CRC 0x0270 +#define OVL_CRC_OUT_MASK GENMASK(30, 0) #define DISP_REG_OVL_CLRFMT_EXT 0x02D0 +#define DISP_REG_OVL_CLRFMT_EXT1 0x02D8 +#define OVL_CLRFMT_EXT1_CSC_EN(n) (1 << (((n) * 4) + 1)) +#define DISP_REG_OVL_Y2R_PARA_R0(n) (0x0134 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_RMY (GENMASK(14, 0)) +#define DISP_REG_OVL_Y2R_PARA_G0(n) (0x013c + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_GMU (GENMASK(30, 16)) +#define DISP_REG_OVL_Y2R_PARA_B1(n) (0x0148 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_BMV (GENMASK(14, 0)) +#define DISP_REG_OVL_Y2R_PARA_YUV_A_0(n) (0x014c + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_YA (GENMASK(10, 0)) +#define OVL_Y2R_PARA_C_CF_UA (GENMASK(26, 16)) +#define DISP_REG_OVL_Y2R_PARA_YUV_A_1(n) (0x0150 + 0x28 * (n)) +#define OVL_Y2R_PARA_C_CF_VA (GENMASK(10, 0)) +#define DISP_REG_OVL_Y2R_PRE_ADD2(n) (0x0154 + 0x28 * (n)) +#define DISP_REG_OVL_R2R_R0(n) (0x0500 + 0x40 * (n)) +#define DISP_REG_OVL_R2R_G1(n) (0x0510 + 0x40 * (n)) +#define DISP_REG_OVL_R2R_B2(n) (0x0520 + 0x40 * (n)) #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0= x04) @@ -58,6 +85,8 @@ /* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */ #define OVL_CON_RGB_SWAP BIT(25) =20 +#define OVL_CON_MTX_AUTO_DIS BIT(26) +#define OVL_CON_MTX_EN BIT(27) #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_ARGB8888 (2 << 12) #define OVL_CON_CLRFMT_RGBA8888 (3 << 12) @@ -70,6 +99,7 @@ #define OVL_CON_CLRFMT_PABGR8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_RGB_S= WAP) #define OVL_CON_CLRFMT_PBGRA8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_BYTE_= SWAP) #define OVL_CON_CLRFMT_PRGBA8888 (OVL_CON_CLRFMT_PABGR8888 | OVL_CON_BYTE_= SWAP) +#define OVL_CON_MTX_PROGRAMMABLE (8 << 16) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -139,6 +169,10 @@ static const u32 mt8195_formats[] =3D { DRM_FORMAT_YUYV, }; =20 +static const u32 mt8195_ovl_crc_ofs[] =3D { + DISP_REG_OVL_CRC, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -149,12 +183,15 @@ struct mtk_disp_ovl_data { const u32 *formats; size_t num_formats; bool supports_clrfmt_ext; + const u32 *crc_ofs; + size_t crc_cnt; }; =20 /* * struct mtk_disp_ovl - DISP_OVL driver structure * @crtc: associated crtc to report vblank events to * @data: platform data + * @crc: crc related information */ struct mtk_disp_ovl { struct drm_crtc *crtc; @@ -164,8 +201,49 @@ struct mtk_disp_ovl { const struct mtk_disp_ovl_data *data; void (*vblank_cb)(void *data); void *vblank_cb_data; + resource_size_t regs_pa; + struct mtk_crtc_crc crc; }; =20 +size_t mtk_ovl_crc_cnt(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + return ovl->crc.cnt; +} + +u32 *mtk_ovl_crc_entry(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + return ovl->crc.va; +} + +void mtk_ovl_crc_read(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + mtk_crtc_read_crc(&ovl->crc, ovl->regs); +} + +void mtk_ovl_crc_start(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_crtc_start_crc_cmdq(&ovl->crc); +#endif +} + +void mtk_ovl_crc_stop(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_crtc_stop_crc_cmdq(&ovl->crc); +#endif +} + static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv =3D dev_id; @@ -245,15 +323,27 @@ void mtk_ovl_clk_disable(struct device *dev) void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + unsigned int reg =3D readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); =20 - if (ovl->data->smi_id_en) { - unsigned int reg; + if (ovl->data->smi_id_en) + reg |=3D OVL_LAYER_SMI_ID_EN; =20 - reg =3D readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); - reg =3D reg | OVL_LAYER_SMI_ID_EN; - writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + /* + * When doing Y2R conversion, it's common to get an output + * that is larger than 10 bits (negative numbers). + * Enable this bit to clamp the output to 10 bits per channel + * (should always be enabled) + */ + reg |=3D OVL_OUTPUT_CLAMP; + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + + reg =3D OVL_EN; + if (ovl->data->crc_cnt) { + /* enable crc and its related clocks */ + writel_relaxed(OVL_CRC_EN, ovl->regs + DISP_REG_OVL_TRIG); + reg |=3D OVL_OP_8BIT_MODE | OVL_HG_FOVL_CK_ON | OVL_HF_FOVL_CK_ON; } - writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_EN); } =20 void mtk_ovl_stop(struct device *dev) @@ -491,6 +581,83 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) ignore_pixel_alpha =3D OVL_CONST_BLEND; =20 + /* + * OVL only supports 8 bits data in CRC calculation, transform 10-bit + * RGB to 8-bit RGB by leveraging the ability of the Y2R (YUV-to-RGB) + * hardware to multiply coefficients, although there is nothing to do + * with the YUV format. + */ + if (ovl->data->supports_clrfmt_ext) { + u32 y2r_coef =3D 0, y2r_offset =3D 0, r2r_coef =3D 0, csc_en =3D 0; + + if (is_10bit_rgb(fmt)) { + con |=3D OVL_CON_MTX_AUTO_DIS | OVL_CON_MTX_EN | OVL_CON_MTX_PROGRAMMAB= LE; + + /* + * Y2R coefficient setting + * bit 13 is 2^1, bit 12 is 2^0, bit 11 is 2^-1, + * bit 10 is 2^-2 =3D 0.25 + */ + y2r_coef =3D BIT(10); + + /* -1 in 10bit */ + y2r_offset =3D GENMASK(10, 0) - 1; + + /* + * R2R coefficient setting + * bit 19 is 2^1, bit 18 is 2^0, bit 17 is 2^-1, + * bit 20 is 2^2 =3D 4 + */ + r2r_coef =3D BIT(20); + + /* CSC_EN is for R2R */ + csc_en =3D OVL_CLRFMT_EXT1_CSC_EN(idx); + + /* + * 1. YUV input data - 1 and shift right for 2 bits to remove it + * [R'] [0.25 0 0] [Y in - 1] + * [G'] =3D [ 0 0.25 0] * [U in - 1] + * [B'] [ 0 0 0.25] [V in - 1] + * + * 2. shift left for 2 bit letting the last 2 bits become 0 + * [R out] [ 4 0 0] [R'] + * [G out] =3D [ 0 4 0] * [G'] + * [B out] [ 0 0 4] [B'] + */ + } + + mtk_ddp_write_mask(cmdq_pkt, y2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_R0(idx), + OVL_Y2R_PARA_C_CF_RMY); + mtk_ddp_write_mask(cmdq_pkt, (y2r_coef << 16), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_G0(idx), + OVL_Y2R_PARA_C_CF_GMU); + mtk_ddp_write_mask(cmdq_pkt, y2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_B1(idx), + OVL_Y2R_PARA_C_CF_BMV); + + mtk_ddp_write_mask(cmdq_pkt, y2r_offset, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx), + OVL_Y2R_PARA_C_CF_YA); + mtk_ddp_write_mask(cmdq_pkt, (y2r_offset << 16), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx), + OVL_Y2R_PARA_C_CF_UA); + mtk_ddp_write_mask(cmdq_pkt, y2r_offset, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_1(idx), + OVL_Y2R_PARA_C_CF_VA); + + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_R0(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_G1(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_B2(idx)); + + mtk_ddp_write_mask(cmdq_pkt, csc_en, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT1, + OVL_CLRFMT_EXT1_CSC_EN(idx)); + } + if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; addr +=3D (pending->height - 1) * pending->pitch; @@ -602,15 +769,31 @@ static int mtk_disp_ovl_probe(struct platform_device = *pdev) dev_err(dev, "failed to ioremap ovl\n"); return PTR_ERR(priv->regs); } + + priv->data =3D of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + if (priv->data->crc_cnt) { + mtk_crtc_init_crc(&priv->crc, + priv->data->crc_ofs, priv->data->crc_cnt, + DISP_REG_OVL_TRIG, OVL_CRC_CLR); + } + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret =3D cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); if (ret) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); -#endif - - priv->data =3D of_device_get_match_data(dev); - platform_set_drvdata(pdev, priv); =20 + if (priv->data->crc_cnt) { + if (of_property_read_u32_index(dev->of_node, + "mediatek,gce-events", 0, + &priv->crc.cmdq_event)) { + dev_warn(dev, "failed to get gce-events for crc\n"); + } + priv->crc.cmdq_reg =3D &priv->cmdq_reg; + mtk_crtc_create_crc_cmdq(dev, &priv->crc); + } +#endif ret =3D devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, IRQF_TRIGGER_NONE, dev_name(dev), priv); if (ret < 0) { @@ -631,6 +814,10 @@ static int mtk_disp_ovl_probe(struct platform_device *= pdev) =20 static void mtk_disp_ovl_remove(struct platform_device *pdev) { + struct device *dev =3D &pdev->dev; + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + mtk_crtc_destroy_crc(&ovl->crc); component_del(&pdev->dev, &mtk_disp_ovl_component_ops); pm_runtime_disable(&pdev->dev); } @@ -701,6 +888,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .formats =3D mt8195_formats, .num_formats =3D ARRAY_SIZE(mt8195_formats), .supports_clrfmt_ext =3D true, + .crc_ofs =3D mt8195_ovl_crc_ofs, + .crc_cnt =3D ARRAY_SIZE(mt8195_ovl_crc_ofs), }; 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Fri, 14 Jun 2024 10:46:26 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 14 Jun 2024 10:46:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 14 Jun 2024 10:46:25 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Bibby Hsieh , CK Hu , "Nancy . Lin" , Sean Paul , Jason Chen , Fei Shao , , , , , Hsiao Chien Sung Subject: [PATCH v9 21/21] drm/mediatek: Support CRC in OVL adaptor Date: Fri, 14 Jun 2024 10:46:20 +0800 Message-ID: <20240614024620.19011-22-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240614024620.19011-1-shawn.sung@mediatek.com> References: <20240614024620.19011-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung We choose Mixer as CRC generator in OVL adaptor since its frame done event will trigger vblanks, we can know when is safe to retrieve CRC of the frame. In OVL adaptor, there's no image procession after Mixer, unlike the OVL in VDOSYS0, Mixer's CRC will include all the effects that are applied to the frame. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 5 ++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 5 ++ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 35 +++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.c | 72 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 7 ++ 5 files changed, 124 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index c583869b110a..1207f855bf76 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -422,6 +422,11 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor= =3D { .clk_enable =3D mtk_ovl_adaptor_clk_enable, .clk_disable =3D mtk_ovl_adaptor_clk_disable, .config =3D mtk_ovl_adaptor_config, + .crc_cnt =3D mtk_ovl_adaptor_crc_cnt, + .crc_entry =3D mtk_ovl_adaptor_crc_entry, + .crc_read =3D mtk_ovl_adaptor_crc_read, + .crc_start =3D mtk_ovl_adaptor_crc_start, + .crc_stop =3D mtk_ovl_adaptor_crc_stop, .start =3D mtk_ovl_adaptor_start, .stop =3D mtk_ovl_adaptor_stop, .layer_nr =3D mtk_ovl_adaptor_layer_nr, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index a03d7a10847a..0ef32bc3b996 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -140,6 +140,11 @@ const u32 *mtk_ovl_adaptor_get_formats(struct device *= dev); size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev, const struct drm_display_mode *mode); +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev); +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev); +void mtk_ovl_adaptor_crc_read(struct device *dev); +void mtk_ovl_adaptor_crc_start(struct device *dev); +void mtk_ovl_adaptor_crc_stop(struct device *dev); =20 void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 39bcc73326f0..6c73007518ba 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -208,6 +208,41 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, = unsigned int idx, mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); } =20 +size_t mtk_ovl_adaptor_crc_cnt(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + return mtk_ethdr_crc_cnt(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0= ]); +} + +u32 *mtk_ovl_adaptor_crc_entry(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + return mtk_ethdr_crc_entry(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHD= R0]); +} + +void mtk_ovl_adaptor_crc_read(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + mtk_ethdr_crc_read(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +void mtk_ovl_adaptor_crc_start(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + mtk_ethdr_crc_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + +void mtk_ovl_adaptor_crc_stop(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + mtk_ethdr_crc_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]); +} + void mtk_ovl_adaptor_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 0aa6b23287e5..84e0756f2e88 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -25,6 +25,9 @@ #define MIX_FME_CPL_INTEN BIT(1) #define MIX_INTSTA 0x8 #define MIX_EN 0xc +#define MIX_TRIG 0x10 +#define MIX_TRIG_CRC_EN BIT(8) +#define MIX_TRIG_CRC_RST BIT(9) #define MIX_RST 0x14 #define MIX_ROI_SIZE 0x18 #define MIX_DATAPATH_CON 0x1c @@ -40,6 +43,11 @@ #define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) + +/* CRC register offsets for odd and even lines */ +#define MIX_CRC_ODD 0x110 +#define MIX_CRC_EVEN 0x114 + #define MIX_FUNC_DCM0 0x120 #define MIX_FUNC_DCM1 0x124 #define MIX_FUNC_DCM_ENABLE 0xffffffff @@ -82,6 +90,7 @@ struct mtk_ethdr { void *vblank_cb_data; int irq; struct reset_control *reset_ctl; + struct mtk_crtc_crc crc; }; =20 static const char * const ethdr_clk_str[] =3D { @@ -100,6 +109,50 @@ static const char * const ethdr_clk_str[] =3D { "vdo_be_async", }; =20 +static const u32 ethdr_crc_ofs[] =3D { + MIX_CRC_ODD, + MIX_CRC_EVEN, +}; + +size_t mtk_ethdr_crc_cnt(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + + return priv->crc.cnt; +} + +u32 *mtk_ethdr_crc_entry(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + + return priv->crc.va; +} + +void mtk_ethdr_crc_read(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + + mtk_crtc_read_crc(&priv->crc, priv->ethdr_comp[ETHDR_MIXER].regs); +} + +void mtk_ethdr_crc_start(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_crtc_start_crc_cmdq(&priv->crc); +#endif +} + +void mtk_ethdr_crc_stop(struct device *dev) +{ + struct mtk_ethdr *priv =3D dev_get_drvdata(dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + mtk_crtc_stop_crc_cmdq(&priv->crc); +#endif +} + void mtk_ethdr_register_vblank_cb(struct device *dev, void (*vblank_cb)(void *), void *vblank_cb_data) @@ -261,6 +314,9 @@ void mtk_ethdr_start(struct device *dev) struct mtk_ethdr_comp *mixer =3D &priv->ethdr_comp[ETHDR_MIXER]; =20 writel(1, mixer->regs + MIX_EN); + + if (priv->crc.cnt) + writel(MIX_TRIG_CRC_EN, mixer->regs + MIX_TRIG); } =20 void mtk_ethdr_stop(struct device *dev) @@ -322,6 +378,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; =20 + mtk_crtc_init_crc(&priv->crc, ethdr_crc_ofs, ARRAY_SIZE(ethdr_crc_ofs), + MIX_TRIG, MIX_TRIG_CRC_RST); + for (i =3D 0; i < ETHDR_ID_MAX; i++) { priv->ethdr_comp[i].dev =3D dev; priv->ethdr_comp[i].regs =3D of_iomap(dev->of_node, i); @@ -330,6 +389,16 @@ static int mtk_ethdr_probe(struct platform_device *pde= v) &priv->ethdr_comp[i].cmdq_base, i); if (ret) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); + + if (i =3D=3D ETHDR_MIXER) { + if (of_property_read_u32_index(dev->of_node, + "mediatek,gce-events", i, + &priv->crc.cmdq_event)) { + dev_warn(dev, "failed to get gce-events for crc\n"); + } + priv->crc.cmdq_reg =3D &priv->ethdr_comp[i].cmdq_base; + mtk_crtc_create_crc_cmdq(dev, &priv->crc); + } #endif dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i); } @@ -370,6 +439,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev) =20 static int mtk_ethdr_remove(struct platform_device *pdev) { + struct mtk_ethdr *priv =3D dev_get_drvdata(&pdev->dev); + + mtk_crtc_destroy_crc(&priv->crc); component_del(&pdev->dev, &mtk_ethdr_component_ops); return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediate= k/mtk_ethdr.h index 81af9edea3f7..6c479c460ac0 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.h +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h @@ -22,4 +22,11 @@ void mtk_ethdr_register_vblank_cb(struct device *dev, void mtk_ethdr_unregister_vblank_cb(struct device *dev); void mtk_ethdr_enable_vblank(struct device *dev); void mtk_ethdr_disable_vblank(struct device *dev); + +size_t mtk_ethdr_crc_cnt(struct device *dev); +u32 *mtk_ethdr_crc_entry(struct device *dev); +void mtk_ethdr_crc_read(struct device *dev); +void mtk_ethdr_crc_start(struct device *dev); +void mtk_ethdr_crc_stop(struct device *dev); + #endif --=20 2.18.0