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([5.2.194.157]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cbb05b465sm308861a12.18.2024.06.13.04.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 04:40:32 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: Alisa-Dariana Roman , Jonathan Cameron , Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Alexandru Tachici , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Subject: [PATCH v4 5/5] iio: adc: ad7192: Add clock provider Date: Thu, 13 Jun 2024 14:40:01 +0300 Message-Id: <20240613114001.270233-6-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613114001.270233-1-alisa.roman@analog.com> References: <20240613114001.270233-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Internal clock of AD719X devices can be made available on MCLK2 pin. Add clock provider to support this functionality. Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 90 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index c30ffe47cd70..36e3fe50c455 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -203,6 +204,7 @@ struct ad7192_state { struct regulator *avdd; struct regulator *vref; struct clk *mclk; + struct clk_hw int_clk_hw; u16 int_vref_mv; u32 aincom_mv; u32 fclk; @@ -403,6 +405,90 @@ static const char *const ad7192_clock_names[] =3D { "mclk" }; =20 +static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) +{ + return container_of(hw, struct ad7192_state, int_clk_hw); +} + +static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return AD7192_INT_FREQ_MHZ; +} + +static int ad7192_clk_output_is_enabled(struct clk_hw *hw) +{ + struct ad7192_state *st =3D clk_hw_to_ad7192(hw); + + return st->clock_sel =3D=3D AD7192_CLK_INT_CO; +} + +static int ad7192_clk_prepare(struct clk_hw *hw) +{ + struct ad7192_state *st =3D clk_hw_to_ad7192(hw); + int ret; + + st->mode &=3D ~AD7192_MODE_CLKSRC_MASK; + st->mode |=3D AD7192_CLK_INT_CO; + + ret =3D ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return ret; + + st->clock_sel =3D AD7192_CLK_INT_CO; + + return 0; +} + +static void ad7192_clk_unprepare(struct clk_hw *hw) +{ + struct ad7192_state *st =3D clk_hw_to_ad7192(hw); + int ret; + + st->mode &=3D ~AD7192_MODE_CLKSRC_MASK; + st->mode |=3D AD7192_CLK_INT; + + ret =3D ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret) + return; + + st->clock_sel =3D AD7192_CLK_INT; +} + +static const struct clk_ops ad7192_int_clk_ops =3D { + .recalc_rate =3D ad7192_clk_recalc_rate, + .is_enabled =3D ad7192_clk_output_is_enabled, + .prepare =3D ad7192_clk_prepare, + .unprepare =3D ad7192_clk_unprepare, +}; + +static int ad7192_register_clk_provider(struct ad7192_state *st) +{ + struct device *dev =3D &st->sd.spi->dev; + struct clk_init_data init =3D {}; + const char *clk_name; + int ret; + + if (!IS_ENABLED(CONFIG_COMMON_CLK)) + return 0; + + ret =3D device_property_read_string(dev, "clock-output-names", &clk_name); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get clock-output-names\n"); + + init.name =3D clk_name; + init.ops =3D &ad7192_int_clk_ops; + + st->int_clk_hw.init =3D &init; + ret =3D devm_clk_hw_register(dev, &st->int_clk_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &st->int_clk_hw); +} + static int ad7192_clock_setup(struct ad7192_state *st) { struct device *dev =3D &st->sd.spi->dev; @@ -414,6 +500,10 @@ static int ad7192_clock_setup(struct ad7192_state *st) if (ret < 0) { st->clock_sel =3D AD7192_CLK_INT; st->fclk =3D AD7192_INT_FREQ_MHZ; + + ret =3D ad7192_register_clk_provider(st); + if (ret) + return ret; } else { st->clock_sel =3D AD7192_CLK_EXT_MCLK1_2 + ret; =20 --=20 2.34.1