From nobody Sun Feb 8 22:39:34 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23A1C16F0FD; Wed, 12 Jun 2024 13:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718198667; cv=none; b=Vq3bUANleZQUx9dFGIHR/a4retNYb6jZz8549A8ruN+nkpVBYur3aiwj1F+5VXpvS7OVs0fdbfGPhQ9YI9ue1LHwwsVjFh2OD3wTIS4kp4asp5c0+tYqHtOxQEXuIx35mKJcCcd/+51urTm8ytb7/8PJa5z1KsnN9Z4EmwAIFuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718198667; c=relaxed/simple; bh=JvXngxu9HGFoJkMNN0xeWKtg0wICDR1DqTnlIDWqeJU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aa/jaF7ZwtC8jRq7Fb3evoxJWFVBP8CenqroQxwr20k0D6yz8ABmqV+yHcq7ffoYHwajE1UGlxEjIyXnqDr1rygVLxs1wGCiDdC51VYAVyjb19Oo6N1sA2Bg8EKwt9ItITiki9icPqljM/giSVG8/do/F6wnv7ct6ckX92ZghWQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Ktr5eKa8; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Ktr5eKa8" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOJGx115247; Wed, 12 Jun 2024 08:24:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718198659; bh=OHWXyPTnN5KSXLCf0hjbD7yaww2UVLY19MKqQgfbez0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ktr5eKa8q7j5Nwn/DmniKSjYcih1XuByd2UNnjZ40y0LqhlqBTECg5bIDPoltotU7 nfRlA+jKuud6DGnxquR/9S4xmBz0NI+3eZWHAH3F+9wgaK43EYi16CurFlN/ZV/ty7 xN16akj60u2cW0Jzdw59XRE9fXAo8HBWh0c67c98= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45CDOJKP094545 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Jun 2024 08:24:19 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 12 Jun 2024 08:24:19 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 12 Jun 2024 08:24:19 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOAmr046478; Wed, 12 Jun 2024 08:24:15 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 1/8] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi Date: Wed, 12 Jun 2024 18:54:02 +0530 Message-ID: <20240612132409.2477888-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240612132409.2477888-1-s-vadapalli@ti.com> References: <20240612132409.2477888-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The AM62P and J722S SoCs share most of the peripherals. With the aim of reusing the existing k3-am62p-{mcu,main,thermal,wakeup}.dtsi files for J722S SoC, rename them to indicate that they are shared with the J722S SoC. The peripherals that are not shared will be moved in the upcoming patches to the respective k3-{soc}-{mcu,main,wakeup}.dtsi files without "common" in the filename, emphasizing that they are not shared. Signed-off-by: Siddharth Vadapalli Acked-by: Andrew Davis Acked-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-2-s-vadapalli@ti.com/ Changes since v5: - k3-am62p.dtsi is left as-is, instead of changing it to k3-am62p-j722s-common.dtsi. - Renamed k3-am62p-thermal.dtsi to k3-am62p-j722s-common-thermal.dtsi. ...k3-am62p-main.dtsi =3D> k3-am62p-j722s-common-main.dtsi} | 3 ++- .../{k3-am62p-mcu.dtsi =3D> k3-am62p-j722s-common-mcu.dtsi} | 3 ++- ...2p-thermal.dtsi =3D> k3-am62p-j722s-common-thermal.dtsi} | 0 ...m62p-wakeup.dtsi =3D> k3-am62p-j722s-common-wakeup.dtsi} | 3 ++- arch/arm64/boot/dts/ti/k3-am62p.dtsi | 8 ++++---- 5 files changed, 10 insertions(+), 7 deletions(-) rename arch/arm64/boot/dts/ti/{k3-am62p-main.dtsi =3D> k3-am62p-j722s-comm= on-main.dtsi} (99%) rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi =3D> k3-am62p-j722s-commo= n-mcu.dtsi} (98%) rename arch/arm64/boot/dts/ti/{k3-am62p-thermal.dtsi =3D> k3-am62p-j722s-c= ommon-thermal.dtsi} (100%) rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi =3D> k3-am62p-j722s-co= mmon-wakeup.dtsi} (97%) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62p-j722s-common-main.dtsi similarity index 99% rename from arch/arm64/boot/dts/ti/k3-am62p-main.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 900d1f9530a2..bf6384ba824a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree file for the AM62P main domain peripherals + * Device Tree file for the MAIN domain peripherals shared by AM62P and J7= 22S + * * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ */ =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62p-j722s-common-mcu.dtsi similarity index 98% rename from arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index b973b550eb9d..1d4e5fc8b4e0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree file for the AM62P MCU domain peripherals + * Device Tree file for the MCU domain peripherals shared by AM62P and J72= 2S + * * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ */ =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi b/arch/arm64/boot= /dts/ti/k3-am62p-j722s-common-thermal.dtsi similarity index 100% rename from arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-j722s-common-wakeup.dtsi similarity index 97% rename from arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index c71d9624ea27..f6ec6e8e171d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree file for the AM62P wakeup domain peripherals + * Device Tree file for the WAKEUP domain peripherals shared by AM62P and = J722S + * * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ */ =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/= k3-am62p.dtsi index 94babc412575..2d11c80107b5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -116,10 +116,10 @@ cbass_wakeup: bus@b00000 { }; }; =20 - #include "k3-am62p-thermal.dtsi" + #include "k3-am62p-j722s-common-thermal.dtsi" }; =20 /* Now include peripherals for each bus segment */ -#include "k3-am62p-main.dtsi" -#include "k3-am62p-mcu.dtsi" -#include "k3-am62p-wakeup.dtsi" +#include "k3-am62p-j722s-common-main.dtsi" +#include "k3-am62p-j722s-common-mcu.dtsi" +#include "k3-am62p-j722s-common-wakeup.dtsi" --=20 2.40.1 From nobody Sun Feb 8 22:39:34 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC77017D357; Wed, 12 Jun 2024 13:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718198671; cv=none; b=cVBkHE1wUGyczI+m0Tm/EF5Op3lPxLD2gXmzVkZkMUvAcrV6X0XHTtT4gRve4eluNHz3gssga+Fc6yH+mtdg82FVQKAjK48a/9bJ1WE8NonrF0A9WABAut4NubDbBgHB9Ov8d38sLpVuC5EF67xZLRAr6nBuCPnFLmiHCyZRij0= ARC-Message-Signature: i=1; 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Wed, 12 Jun 2024 08:24:23 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOAms046478; Wed, 12 Jun 2024 08:24:20 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 2/8] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi Date: Wed, 12 Jun 2024 18:54:03 +0530 Message-ID: <20240612132409.2477888-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240612132409.2477888-1-s-vadapalli@ti.com> References: <20240612132409.2477888-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The USB1 instance of USB controller on AM62P is different from the USB1 instance of USB controller on J722S. Thus, move the USB1 instance from the shared "k3-am62p-j722s-common-main.dtsi" file to the AM62p specific "k3-am62p-main.dtsi" file. Include "k3-am62p-main.dtsi" in "k3-am62p.dtsi". Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-3-s-vadapalli@ti.com/ Changes since v5: - Since this v6 series contains "k3-am62p.dtsi" rather than "k3-am62p-j722s-common.dtsi", the equivalent change of the v5 patch applies to "k3-am62p.dtsi" in the current patch. - Collected Acked-by tag from Roger Quadros .../dts/ti/k3-am62p-j722s-common-main.dtsi | 26 -------------- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 34 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 3 ++ 3 files changed, 37 insertions(+), 26 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index bf6384ba824a..80d2e559a473 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -662,32 +662,6 @@ usb0: usb@31000000 { }; }; =20 - usbss1: usb@f910000 { - compatible =3D "ti,am62-usb"; - reg =3D <0x00 0x0f910000 0x00 0x800>, - <0x00 0x0f918000 0x00 0x400>; - clocks =3D <&k3_clks 162 3>; - clock-names =3D "ref"; - ti,syscon-phy-pll-refclk =3D <&usb1_phy_ctrl 0x0>; - #address-cells =3D <2>; - #size-cells =3D <2>; - power-domains =3D <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - ranges; - status =3D "disabled"; - - usb1: usb@31100000 { - compatible =3D "snps,dwc3"; - reg =3D <0x00 0x31100000 0x00 0x50000>; - interrupts =3D , /* irq.0 */ - ; /* irq.0 */ - interrupt-names =3D "host", "peripheral"; - maximum-speed =3D "high-speed"; - dr_mode =3D "otg"; - snps,usb2-gadget-lpm-disable; - snps,usb2-lpm-disable; - }; - }; - fss: bus@fc00000 { compatible =3D "simple-bus"; reg =3D <0x00 0x0fc00000 0x00 0x70000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62p-main.dtsi new file mode 100644 index 000000000000..9caab7db5440 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the AM62P MAIN domain peripherals + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&cbass_main { + usbss1: usb@f910000 { + compatible =3D "ti,am62-usb"; + reg =3D <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks =3D <&k3_clks 162 3>; + clock-names =3D "ref"; + ti,syscon-phy-pll-refclk =3D <&usb1_phy_ctrl 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + power-domains =3D <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status =3D "disabled"; + + usb1: usb@31100000 { + compatible =3D "snps,dwc3"; + reg =3D <0x00 0x31100000 0x00 0x50000>; + interrupts =3D , /* irq.0 */ + ; /* irq.0 */ + interrupt-names =3D "host", "peripheral"; + maximum-speed =3D "high-speed"; + dr_mode =3D "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/= k3-am62p.dtsi index 2d11c80107b5..75a15c368c11 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -123,3 +123,6 @@ cbass_wakeup: bus@b00000 { #include "k3-am62p-j722s-common-main.dtsi" #include "k3-am62p-j722s-common-mcu.dtsi" #include "k3-am62p-j722s-common-wakeup.dtsi" + +/* Include AM62P specific peripherals */ +#include "k3-am62p-main.dtsi" --=20 2.40.1 From nobody Sun Feb 8 22:39:34 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24D2917D357; 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charset="utf-8" Introduce the "k3-j722s-main.dtsi" file to contain main domain peripherals that are specific to J722S SoC and are not shared with AM62P. The USB1 instance of the USB controller on J722S is different from that on AM62P. Thus, add the USB1 node in "k3-j722s-main.dtsi". Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-4-s-vadapalli@ti.com/ Changes since v5: - Collected Acked-by tag from Roger Quadros arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi new file mode 100644 index 000000000000..84378fc839d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S MAIN domain peripherals + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&cbass_main { + usbss1: usb@f920000 { + compatible =3D "ti,j721e-usb"; + reg =3D <0x00 0x0f920000 0x00 0x100>; + power-domains =3D <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 278 3>, <&k3_clks 278 1>; + clock-names =3D "ref", "lpm"; + assigned-clocks =3D <&k3_clks 278 3>; /* USB2_REFCLK */ + assigned-clock-parents =3D <&k3_clks 278 4>; /* HF0SC0 */ + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb1: usb@31200000{ + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x31200000 0x00 0x10000>, + <0x00 0x31210000 0x00 0x10000>, + <0x00 0x31220000 0x00 0x10000>; + reg-names =3D "otg", + "xhci", + "dev"; + interrupts =3D , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq */ + interrupt-names =3D "host", + "peripheral", + "otg"; + maximum-speed =3D "super-speed"; + dr_mode =3D "otg"; + }; + }; +}; --=20 2.40.1 From nobody Sun Feb 8 22:39:34 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CA317DE23; Wed, 12 Jun 2024 13:24:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Update "k3-j722s.dtsi" to include "k3-am62p-j722s-common-{}".dtsi files in order to reuse the nodes shared with AM62P. Also include the J722S specific "k3-j722s-main.dtsi". Since the J7 family of SoCs has the k3-{soc}.dtsi file organized as: k3-{soc}.dtsi =3D CPU + Cache + CBASS-Ranges + "Peripheral-Includes" switch the "k3-j722s.dtsi" file to the same convention. Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-5-s-vadapalli@ti.com/ Changes since v5: - Rather than including "k3-am62p-j722s-common.dtsi" which is the equivalent of "k3-am62p.dtsi" in the current series, k3-j722s.dtsi includes "k3-am62p-j722s-common-{}.dtsi" and "k3-j722s-main.dtsi". Also, to match the J7 family of SoCs, the CPU, Cache and CBASS-Ranges are included in "k3-j722s.dtsi". arch/arm64/boot/dts/ti/k3-j722s.dtsi | 158 ++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index c75744edb143..1bcbc9152ff0 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -10,11 +10,133 @@ #include #include =20 -#include "k3-am62p5.dtsi" +#include "k3-pinctrl.h" =20 / { model =3D "Texas Instruments K3 J722S SoC"; compatible =3D "ti,j722s"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; =20 cbass_main: bus@f0000 { compatible =3D "simple-bus"; @@ -74,9 +196,43 @@ cbass_main: bus@f0000 { <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Periph= eral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + bootph-all; + }; + + cbass_wakeup: bus@b00000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Wind= ow */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + bootph-all; + }; }; + + #include "k3-am62p-j722s-common-thermal.dtsi" }; =20 +/* Include peripherals shared with AM62P */ +#include "k3-am62p-j722s-common-main.dtsi" +#include "k3-am62p-j722s-common-mcu.dtsi" +#include "k3-am62p-j722s-common-wakeup.dtsi" + +/* Include J722S specific peripherals */ +#include "k3-j722s-main.dtsi" + /* Main domain overrides */ =20 &inta_main_dmss { --=20 2.40.1 From nobody Sun Feb 8 22:39:34 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2C8E17E440; Wed, 12 Jun 2024 13:24:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718198684; cv=none; b=JWgZ7dcxqwISV/+0X89lzHytaYx8QQPbX0CnWtFSw/IQd8lS2nA7+3eNiXfP4H6ngJJEwzIB4rVuKNysx2LTAvK7xDFLrWMIjQ3WxjF4dmiKW9BUNNnBwNzhQJwRECsdiUdPM7xk4UdHOyNsbH5Q9ZYsLtvAxv9PvXjyYeRxils= ARC-Message-Signature: i=1; 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Wed, 12 Jun 2024 08:24:36 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOAmv046478; Wed, 12 Jun 2024 08:24:33 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 5/8] arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi Date: Wed, 12 Jun 2024 18:54:06 +0530 Message-ID: <20240612132409.2477888-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240612132409.2477888-1-s-vadapalli@ti.com> References: <20240612132409.2477888-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Since the MAIN domain peripherals specific to J722S SoC are present in the "k3-j722s-main.dtsi" file, move the overrides for the MAIN domain from the "k3-j722s.dtsi" file to the "k3-j722s-main.dtsi" file. Signed-off-by: Siddharth Vadapalli --- This patch has been newly introduced in this series and doesn't have a Changelog. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 11 +++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 84378fc839d6..b75dab8230c2 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -38,3 +38,14 @@ usb1: usb@31200000{ }; }; }; + +/* MAIN domain overrides */ + +&inta_main_dmss { + ti,interrupt-ranges =3D <7 71 21>; +}; + +&oc_sram { + reg =3D <0x00 0x70000000 0x00 0x40000>; + ranges =3D <0x00 0x00 0x70000000 0x40000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index 1bcbc9152ff0..14c6c6a332ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -232,14 +232,3 @@ cbass_wakeup: bus@b00000 { =20 /* Include J722S specific peripherals */ #include "k3-j722s-main.dtsi" - -/* Main domain overrides */ - -&inta_main_dmss { - ti,interrupt-ranges =3D <7 71 21>; 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Wed, 12 Jun 2024 08:24:37 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 6/8] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Date: Wed, 12 Jun 2024 18:54:07 +0530 Message-ID: <20240612132409.2477888-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240612132409.2477888-1-s-vadapalli@ti.com> References: <20240612132409.2477888-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The SERDES0 and SERDES1 instances of SERDES on J722S are single lane SERDES which are individually muxed across different peripherals. LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is muxed between PCIe and CPSW. Define the lane-muxing macros to be used as the idle state values. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-6-s-vadapalli@ti.com/ Changes since v5: - Collected Reviewed-by tag from Roger Quadros arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3= -serdes.h index a011ad893b44..ef3606068140 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,12 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 =20 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0 +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */ --=20 2.40.1 From nobody Sun Feb 8 22:39:34 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E550917E8F2; Wed, 12 Jun 2024 13:24:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718198693; cv=none; b=b6stImzM1zxWrWpLeVILTTFeOnAi3w6KaZ6L7OTFwuqGUVGx1jvEorupOVddWUIT9IPXkbHVJ3/gweAhpRZz7YMY9AYNAEvp2n4Yrxqs7LPRGDrwLWjOhYEWIT+OUusXoGnk6HcTy6Xb8/cMCRStW6bpFh8tLbYZv0skmQThbZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718198693; c=relaxed/simple; bh=Q+8FM93nKywVlI/nXL2/Vx49wacxNg9AwN+P6tSTrOI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l7bs6rhgZr2qVJM7TEJsCuqq8wMyRTo+xUpRxfPGD0XnsKlo9xFK9s4M4oXwFFQZL8c9O8NGTmYnGDP3HHin6yGbliM7Q3VlieBtKSfU4xo7IgNOPNDlELtSKMx6uE7OI1Q7SL48BE5GK8P27zj0p60MN/O+kaVWlfiOZAoiZ+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=N8DIxdKk; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="N8DIxdKk" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOkeV115313; Wed, 12 Jun 2024 08:24:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718198686; bh=kYN9IxkRa7Hxu1t+XCG1/vaKL4/nK6uH3vOzUxeK6Ug=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N8DIxdKk7XwBchIUGAS8aOLtzaq9Ceg43ouxZHl4R/z72ml5ldImDKCKVsiC/laDd a3CZSf4R7W+4/8fn+tKjw0lAQBh5VCJ9LTwUcVrY/MNSR3re6GCH0ZArdRZf2MNe8d /zy72yv15eY5IEzNd0KiS8pl9k9tjLMJ3b35ZwiM= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45CDOjCI065630 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Jun 2024 08:24:45 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 12 Jun 2024 08:24:45 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 12 Jun 2024 08:24:45 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOAmx046478; Wed, 12 Jun 2024 08:24:41 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 7/8] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support Date: Wed, 12 Jun 2024 18:54:08 +0530 Message-ID: <20240612132409.2477888-8-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240612132409.2477888-1-s-vadapalli@ti.com> References: <20240612132409.2477888-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller. Since SERDES and PCIe are not present on AM62P SoC, add the device-tree nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi" file. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-7-s-vadapalli@ti.com/ Changes since v5: - Collected Acked-by tag from Roger Quadros arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 133 ++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index b75dab8230c2..e1465daa0c96 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -5,7 +5,123 @@ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti= .com/ */ =20 +#include +#include + +/ { + serdes_refclk: clk-0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + }; +}; + &cbass_main { + serdes_wiz0: phy@f000000 { + compatible =3D "ti,am64-wiz-10g"; + ranges =3D <0x0f000000 0x0 0x0f000000 0x00010000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <1>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + + assigned-clocks =3D <&k3_clks 279 1>; + assigned-clock-parents =3D <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x0f000000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; /* Needs lane config */ + }; + }; + + serdes_wiz1: phy@f010000 { + compatible =3D "ti,am64-wiz-10g"; + ranges =3D <0x0f010000 0x0 0x0f010000 0x00010000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <1>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + + assigned-clocks =3D <&k3_clks 280 1>; + assigned-clock-parents =3D <&k3_clks 280 5>; + + serdes1: serdes@f010000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x0f010000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz1 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 280 1>, + <&k3_clks 280 1>, + <&k3_clks 280 1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; /* Needs lane config */ + }; + }; + + pcie0_rc: pcie@f102000 { + compatible =3D "ti,j722s-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + ranges =3D <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + max-link-speed =3D <3>; + num-lanes =3D <1>; + power-domains =3D <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names =3D "fck", "pcie_refclk"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb010>; + cdns,no-bar-match-nbits =3D <64>; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + status =3D "disabled"; + }; + usbss1: usb@f920000 { compatible =3D "ti,j721e-usb"; reg =3D <0x00 0x0f920000 0x00 0x100>; @@ -39,6 +155,23 @@ usb1: usb@31200000{ }; }; =20 +&main_conf { + serdes_ln_ctrl: mux-controller@4080 { + compatible =3D "reg-mux"; + reg =3D <0x4080 0x14>; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x00 0x3>, /* SERDES0 lane0 select */ + <0x10 0x3>; /* SERDES1 lane0 select */ + }; +}; + +&wkup_conf { + pcie0_ctrl: pcie0-ctrl@4070 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4070 0x4>; + }; +}; + /* MAIN domain overrides */ =20 &inta_main_dmss { --=20 2.40.1 From nobody Sun Feb 8 22:39:34 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 291DC17D37E; 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charset="utf-8" Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0 of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to interface with the Type-C port via the USB hub, by configuring the pin P05 of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed mode of operation with Lane 0 of the SERDES0 instance of SERDES. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-7-s-vadapalli@ti.com/ Changes since v5: - Collected Acked-by tag from Roger Quadros arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 73 +++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index bf3c246d13d1..253b02f0437d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -9,7 +9,9 @@ /dts-v1/; =20 #include +#include #include "k3-j722s.dtsi" +#include "k3-serdes.h" =20 / { compatible =3D "ti,j722s-evm", "ti,j722s"; @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TX= C */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; }; =20 &cpsw3g { @@ -301,6 +309,13 @@ exp1: gpio@23 { "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + + p05-hog { + /* P05 - USB2.0_MUX_SEL */ + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_HIGH>; + output-high; + }; }; }; =20 @@ -384,3 +399,61 @@ &sdhci1 { status =3D "okay"; bootph-all; }; + +&serdes_ln_ctrl { + idle-states =3D , + ; +}; + +&serdes0 { + status =3D "okay"; + serdes0_usb_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + status =3D "okay"; + serdes1_pcie_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz1 1>; + }; +}; + +&pcie0_rc { + reset-gpios =3D <&exp1 18 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes1_pcie_link>; + phy-names =3D "pcie-phy"; + status =3D "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status =3D "okay"; +}; + +&usb0 { + dr_mode =3D "otg"; + usb-role-switch; +}; + +&usbss1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_usb1_pins_default>; + ti,vbus-divider; + status =3D "okay"; +}; + +&usb1 { + dr_mode =3D "host"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb_link>; + phy-names =3D "cdns3,usb3-phy"; +}; --=20 2.40.1