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Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 28ae10c24a5f..7b619db07694 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5116,6 +5116,13 @@ gic_its: msi-controller@17040000 { }; }; =20 + cpucp_mbox: mailbox@17430000 { + compatible =3D "qcom,x1e80100-cpucp-mbox"; + reg =3D <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + apps_rsc: rsc@17500000 { compatible =3D "qcom,rpmh-rsc"; reg =3D <0 0x17500000 0 0x10000>, @@ -5299,6 +5306,25 @@ frame@1780d000 { }; }; =20 + sram: sram@18b4e000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x18b4e000 0x0 0x400>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x18b4e000 0x400>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x200>; + }; + + cpu_scp_lpri1: scp-sram-section@200 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x200 0x200>; + }; + }; + system-cache-controller@25000000 { compatible =3D "qcom,x1e80100-llcc"; reg =3D <0 0x25000000 0 0x200000>, --=20 2.34.1