From nobody Thu Feb 12 14:10:04 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1A8616F0FB; Wed, 12 Jun 2024 11:23:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718191400; cv=none; b=Iuze3wh9sHSIMCP1TuhAK1YM5S1wxWxA6tiC5Sj0Fol5q296cTG8jKXFweiJ0q0Dv1CYcnh+7HNkuFTWpCmrb10M+VDJmMCbUxAbtRu+eNpouy7jFtrOP5U7zEvRZ8mCnPTVuW8KSCPgv+o6aHO3yqGizuKKJBlHyl5I9RPrcKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718191400; c=relaxed/simple; bh=eyqk4BWKM+w8zgI+2BHLFLdZGQatPIJSvGdKBMHkdnQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lPNZWuaFVGtpJsf7AkOddaHef/msG1JEQb9he6uVgyb4d2bYe8WUjDUGZ/+yI9WcjG2IBu872706KjtRx7AgqpDE4bCUjFRPJQ5jB1opiRLWcq1ATfljdCZ9t8utY938i75knO7CRSXwRNR2oPbwg/NL18uthf+DRej+FJalkzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=R19Yq5TI; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="R19Yq5TI" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45CBNCwP080336; Wed, 12 Jun 2024 06:23:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718191392; bh=650Q/oEA4q0guSCa793ebYVf7QtXHsuFmq4zcJ/TXek=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=R19Yq5TIeFdUD4hvyy0acdnq7K8stejhKcBaJfMX9E0HGmWmZZdzijVJf8QhreDxF uSaJFZJ1nEf2DT/ohbt4R1ly5yrvWc0Od8fX3eWMHfuN5SgGBDqg4N2Gliny8GmLeb Stcjx+U3U8yo29oLWgAVqTjHdYxIe6OPprfDYk+U= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45CBNCk9022931 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Jun 2024 06:23:12 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 12 Jun 2024 06:23:11 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 12 Jun 2024 06:23:12 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [10.24.69.66]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CBMxe4120263; Wed, 12 Jun 2024 06:23:08 -0500 From: Beleswar Padhi To: , CC: , , , , , , , , , , Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j722s-evm: Add memory carveouts for R5F and C7x Date: Wed, 12 Jun 2024 16:52:59 +0530 Message-ID: <20240612112259.1131653-3-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240612112259.1131653-1-b-padhi@ti.com> References: <20240612112259.1131653-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Apurva Nandan The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. The Inter-Processor communication between the main A72 cores and these R5F and DSP remote cores is achieved through shared memory and Mailboxes. Thus, add the memory carveouts and enable the mailbox clusters required for communication. Signed-off-by: Apurva Nandan [ Added and enabled mailbox instances ] Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 140 ++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 253b02f0437de..643a017833572 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -51,12 +51,71 @@ secure_ddr: optee@9e800000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a20000= 00 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x1c00000>; + alignment =3D <0x1000>; + no-map; + }; }; =20 vmain_pd: regulator-0 { @@ -400,6 +459,87 @@ &sdhci1 { bootph-all; }; =20 +&mailbox0_cluster0 { + status =3D "okay"; + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; +}; + +&c7x_1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region =3D <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; +}; + &serdes_ln_ctrl { idle-states =3D , ; --=20 2.34.1