From nobody Thu Feb 12 14:10:54 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22FE03B192; Tue, 11 Jun 2024 16:21:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718122882; cv=none; b=rvA9qMtvHbIt6OpD7PZf3I+8WXTxRy/F1b4Qjs2QBWA3CWUftIGMuYgA1XWT9YnbfkWesFwGzWUpxGmBg9S87EsdPLCkBIrMM6JYZgv/9xChWJ1GZfbYYjVfXfY0vA7a7eCtDtHxIIUlYyoZK1GifcATvgNJlcbgIBWpGlpLgyA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718122882; c=relaxed/simple; bh=vZkZeJSRWsSlA3r72qLOgkTOis1ylOjAsa45W57y/jk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Urqa827zz3D8p/JwFqH+ZMFSBg7q/vx2okSTjD5yvKlojjfLR2FpdTiaGRAwPx+vL+BuDxbdwOaR7I1+gn5yp4LKk3Nq29GHo0HtvyfzUpxyCzWXYtZlEqx4KrUEq3OYa3DvJWKVWcNiJWYRMn/K9n9vtGtpkRhsAcJ1BxRVgtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=nQgaEm7X; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="nQgaEm7X" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45BBkVGZ017594; Tue, 11 Jun 2024 18:20:55 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= PLilViIb1Wrvxygr4/yl4pIC2TFoQ5rU0JcHSUgX2vk=; b=nQgaEm7XMOtwnIIw xFGdC2Vwcwr5nV5q9CgaXOnga8VOSaF2xyaztHD36EopXt2ItD73A48HqDgGNX11 O+h4TYviz/0sCo8+GAV8D6qFwBEw8BN7nQkJh+/nUwq0AuE4zcNBUwe5NSAUed3T MHwX/R1l6DF08fV1IxpbwPNZDm6Jh0Rw+VX6Zjh+MuU7umzykCd4D6kAIU5wehHK +7yiSKaRM2xKOdp54eLmFtJwe6u1hgqRiUu0ub3aM+TgC7JY5gcqYyvG4ocOHveT 6gjMrnMeONuDHmrgHct07GehzNM3lEldCJM7Ww3RYHcn00UeyxR24clHXQctueca 1W7S4g== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp2kvb2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 18:20:55 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7C82240044; Tue, 11 Jun 2024 18:20:48 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4C5EA21B504; Tue, 11 Jun 2024 18:20:12 +0200 (CEST) Received: from localhost (10.48.86.111) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 18:20:12 +0200 From: Valentin Caron To: Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue CC: , , , , , Valentin Caron Subject: [PATCH 1/2] dt-bindings: rtc: stm32: introduce new st,stm32mp25-rtc compatible Date: Tue, 11 Jun 2024 18:19:57 +0200 Message-ID: <20240611161958.469209-2-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611161958.469209-1-valentin.caron@foss.st.com> References: <20240611161958.469209-1-valentin.caron@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_09,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" Introduce new st,stm32mp25-rtc compatible. It is based on st,stm32mp1-rtc. Difference is that stm32mp25 SoC implements a triple protection on RTC registers: - Secure bit based protection - Privileged context based protection - Compartment ID filtering based protection This driver will now check theses configurations before probing to avoid exceptions and fake reads on register. Link: https://www.st.com/resource/en/reference_manual/rm0457-stm32mp25xx-ad= vanced-armbased-3264bit-mpus-stmicroelectronics.pdf#page=3D4081 Signed-off-by: Valentin Caron --- Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Docu= mentation/devicetree/bindings/rtc/st,stm32-rtc.yaml index 4703083d1f11f..65a8a93ef5753 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -15,6 +15,7 @@ properties: - st,stm32-rtc - st,stm32h7-rtc - st,stm32mp1-rtc + - st,stm32mp25-rtc =20 reg: maxItems: 1 @@ -90,7 +91,9 @@ allOf: properties: compatible: contains: - const: st,stm32mp1-rtc + anyOf: + - const: st,stm32mp1-rtc + - const: st,stm32mp25-rtc =20 then: properties: --=20 2.25.1 From nobody Thu Feb 12 14:10:54 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 201B41CFB2; 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charset="utf-8" Introduce new st,stm32mp25-rtc compatible. It is based on st,stm32mp1-rtc. Difference is that stm32mp25 soc implements a triple protection on RTC registers: - Secure bit based protection - Privileged context based protection - Compartment ID filtering based protection This driver will now check theses configurations before probing to avoid exceptions and fake reads on register. At this time, driver needs only to check two resources: INIT and ALARM_A. Other resources are not used. Resource isolation framework (RIF) is a comprehensive set of hardware blocks designed to enforce and manage isolation of STM32 hardware resources, like memory and peripherals. Link: https://www.st.com/resource/en/reference_manual/rm0457-stm32mp25xx-ad= vanced-armbased-3264bit-mpus-stmicroelectronics.pdf#page=3D4081 Signed-off-by: Valentin Caron --- drivers/rtc/rtc-stm32.c | 78 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index 76753c71d92ee..98b07969609d2 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -83,6 +84,18 @@ #define STM32_RTC_VERR_MAJREV_SHIFT 4 #define STM32_RTC_VERR_MAJREV GENMASK(7, 4) =20 +/* STM32_RTC_SECCFGR bit fields */ +#define STM32_RTC_SECCFGR 0x20 +#define STM32_RTC_SECCFGR_ALRA_SEC BIT(0) +#define STM32_RTC_SECCFGR_INIT_SEC BIT(14) +#define STM32_RTC_SECCFGR_SEC BIT(15) + +/* STM32_RTC_RXCIDCFGR bit fields */ +#define STM32_RTC_RXCIDCFGR(x) (0x80 + 0x4 * (x)) +#define STM32_RTC_RXCIDCFGR_CFEN BIT(0) +#define STM32_RTC_RXCIDCFGR_CID GENMASK(6, 4) +#define STM32_RTC_RXCIDCFGR_CID1 1 + /* STM32_RTC_WPR key constants */ #define RTC_WPR_1ST_KEY 0xCA #define RTC_WPR_2ND_KEY 0x53 @@ -120,6 +133,7 @@ struct stm32_rtc_data { bool has_pclk; bool need_dbp; bool need_accuracy; + bool rif_protected; }; =20 struct stm32_rtc { @@ -134,6 +148,14 @@ struct stm32_rtc { int irq_alarm; }; =20 +struct stm32_rtc_rif_resource { + unsigned int num; + u32 bit; +}; + +static const struct stm32_rtc_rif_resource STM32_RTC_RES_ALRA =3D {0, STM3= 2_RTC_SECCFGR_ALRA_SEC}; +static const struct stm32_rtc_rif_resource STM32_RTC_RES_INIT =3D {5, STM3= 2_RTC_SECCFGR_INIT_SEC}; + static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) { const struct stm32_rtc_registers *regs =3D &rtc->data->regs; @@ -553,6 +575,7 @@ static const struct stm32_rtc_data stm32_rtc_data =3D { .has_pclk =3D false, .need_dbp =3D true, .need_accuracy =3D false, + .rif_protected =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -575,6 +598,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data =3D= { .has_pclk =3D true, .need_dbp =3D true, .need_accuracy =3D false, + .rif_protected =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -606,6 +630,7 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .has_pclk =3D true, .need_dbp =3D false, .need_accuracy =3D true, + .rif_protected =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -624,14 +649,57 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .clear_events =3D stm32mp1_rtc_clear_events, }; =20 +static const struct stm32_rtc_data stm32mp25_data =3D { + .has_pclk =3D true, + .need_dbp =3D false, + .need_accuracy =3D true, + .rif_protected =3D true, + .regs =3D { + .tr =3D 0x00, + .dr =3D 0x04, + .cr =3D 0x18, + .isr =3D 0x0C, /* named RTC_ICSR on stm32mp25 */ + .prer =3D 0x10, + .alrmar =3D 0x40, + .wpr =3D 0x24, + .sr =3D 0x50, + .scr =3D 0x5C, + .verr =3D 0x3F4, + }, + .events =3D { + .alra =3D STM32_RTC_SR_ALRA, + }, + .clear_events =3D stm32mp1_rtc_clear_events, +}; + static const struct of_device_id stm32_rtc_of_match[] =3D { { .compatible =3D "st,stm32-rtc", .data =3D &stm32_rtc_data }, { .compatible =3D "st,stm32h7-rtc", .data =3D &stm32h7_rtc_data }, { .compatible =3D "st,stm32mp1-rtc", .data =3D &stm32mp1_data }, + { .compatible =3D "st,stm32mp25-rtc", .data =3D &stm32mp25_data }, {} }; MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); =20 +static int stm32_rtc_check_rif(struct stm32_rtc *stm32_rtc, + struct stm32_rtc_rif_resource res) +{ + u32 rxcidcfgr =3D readl_relaxed(stm32_rtc->base + STM32_RTC_RXCIDCFGR(res= .num)); + u32 seccfgr; + + /* Check if RTC available for our CID */ + if ((rxcidcfgr & STM32_RTC_RXCIDCFGR_CFEN) && + (FIELD_GET(STM32_RTC_RXCIDCFGR_CID, rxcidcfgr) !=3D STM32_RTC_RXCIDCF= GR_CID1)) + return -EACCES; + + /* Check if RTC available for non secure world */ + seccfgr =3D readl_relaxed(stm32_rtc->base + STM32_RTC_SECCFGR); + if ((seccfgr & STM32_RTC_SECCFGR_SEC) | (seccfgr & res.bit)) + return -EACCES; + + return 0; +} + static int stm32_rtc_init(struct platform_device *pdev, struct stm32_rtc *rtc) { @@ -787,6 +855,16 @@ static int stm32_rtc_probe(struct platform_device *pde= v) regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, rtc->dbp_mask); =20 + if (rtc->data->rif_protected) { + ret =3D stm32_rtc_check_rif(rtc, STM32_RTC_RES_INIT); + if (!ret) + ret =3D stm32_rtc_check_rif(rtc, STM32_RTC_RES_ALRA); + if (ret) { + dev_err(&pdev->dev, "Failed to probe RTC due to RIF configuration\n"); + goto err; + } + } + /* * After a system reset, RTC_ISR.INITS flag can be read to check if * the calendar has been initialized or not. INITS flag is reset by a --=20 2.25.1