From nobody Thu Feb 12 17:27:22 2026 Received: from fgw23-7.mail.saunalahti.fi (fgw23-7.mail.saunalahti.fi [62.142.5.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15164176FB3 for ; Tue, 11 Jun 2024 09:31:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.142.5.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718098298; cv=none; b=VtVntZMYne8/IhEvjNO0wnUG6FwT7Zp6aq6hivFX1NXv/0eGOI/lRy7gkEXQ32MXp7GGWSqIp8v7knSsoPUx6mDbyIM1h1fm2TwJPysOA8WCoJwFfUeE8Fm4CkzVtYfDLnFtbZxLsn4I2x06f4yWnu6Thh0u7Ecf7exsB1q5Chk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718098298; c=relaxed/simple; bh=FC2Kl+hbpeiZTZFGRoCBKZ3Bw50AAGllg4iHaBq5Tm4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s+yAM/u+6Z7QD/qI6m9v+u4vpYgd8Iq+h89V3JIxyu4CnmTjNSDHXGyzk+r/VoLyWQCrMOVUQ12K6cTZFHfat94kUfVj/WF6NFmoDZQdgQuslqO6Wngpt28SKkotJH+sPFa9HV9VKSu3hC90l8VfXefWWM08moamUyT9BuOYpNQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com; spf=fail smtp.mailfrom=gmail.com; arc=none smtp.client-ip=62.142.5.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=gmail.com Received: from localhost (88-113-25-87.elisa-laajakaista.fi [88.113.25.87]) by fgw20.mail.saunalahti.fi (Halon) with ESMTP id 6519693c-27d5-11ef-8d69-005056bd6ce9; Tue, 11 Jun 2024 12:31:34 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Jacky Huang , Linus Walleij , Tomer Maimon , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org Cc: Shan-Chun Hung , Avi Fishman , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Andy Shevchenko Subject: [PATCH v1 3/4] pinctrl: nuvoton: Convert to use struct group_desc Date: Tue, 11 Jun 2024 12:30:24 +0300 Message-ID: <20240611093127.90210-4-andy.shevchenko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240611093127.90210-1-andy.shevchenko@gmail.com> References: <20240611093127.90210-1-andy.shevchenko@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Andy Shevchenko The pin control core header provides struct group_desc. Utilize it instead of open coded variants in the driver. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/nuvoton/pinctrl-ma35.c | 66 ++++++++++++-------------- 1 file changed, 31 insertions(+), 35 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvot= on/pinctrl-ma35.c index 62e877b76a25..7c2b0039d1e4 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c +++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c @@ -106,13 +106,6 @@ struct ma35_pin_setting { unsigned int nconfigs; }; =20 -struct ma35_pin_group { - const char *name; - unsigned int npins; - unsigned int *pins; - struct ma35_pin_setting *settings; -}; - struct ma35_pin_bank { void __iomem *reg_base; struct clk *clk; @@ -141,7 +134,7 @@ struct ma35_pinctrl { struct pinctrl_dev *pctl; const struct ma35_pinctrl_soc_info *info; struct regmap *regmap; - struct ma35_pin_group *groups; + struct group_desc *groups; unsigned int ngroups; struct pinfunction *functions; unsigned int nfunctions; @@ -160,7 +153,7 @@ static const char *ma35_get_group_name(struct pinctrl_d= ev *pctldev, unsigned int { struct ma35_pinctrl *npctl =3D pinctrl_dev_get_drvdata(pctldev); =20 - return npctl->groups[selector].name; + return npctl->groups[selector].grp.name; } =20 static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int s= elector, @@ -171,19 +164,19 @@ static int ma35_get_group_pins(struct pinctrl_dev *pc= tldev, unsigned int selecto if (selector >=3D npctl->ngroups) return -EINVAL; =20 - *pins =3D npctl->groups[selector].pins; - *npins =3D npctl->groups[selector].npins; + *pins =3D npctl->groups[selector].grp.pins; + *npins =3D npctl->groups[selector].grp.npins; =20 return 0; } =20 -static struct ma35_pin_group *ma35_pinctrl_find_group_by_name( - const struct ma35_pinctrl *npctl, const char *name) +static struct group_desc * +ma35_pinctrl_find_group_by_name(const struct ma35_pinctrl *npctl, const ch= ar *name) { int i; =20 for (i =3D 0; i < npctl->ngroups; i++) { - if (!strcmp(npctl->groups[i].name, name)) + if (!strcmp(npctl->groups[i].grp.name, name)) return &npctl->groups[i]; } return NULL; @@ -195,9 +188,10 @@ static int ma35_pinctrl_dt_node_to_map_func(struct pin= ctrl_dev *pctldev, unsigned int *num_maps) { struct ma35_pinctrl *npctl =3D pinctrl_dev_get_drvdata(pctldev); - struct ma35_pin_group *grp; + struct ma35_pin_setting *setting; struct pinctrl_map *new_map; struct device_node *parent; + struct group_desc *grp; int map_num =3D 1; int i; =20 @@ -211,7 +205,7 @@ static int ma35_pinctrl_dt_node_to_map_func(struct pinc= trl_dev *pctldev, return -EINVAL; } =20 - map_num +=3D grp->npins; + map_num +=3D grp->grp.npins; new_map =3D devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), GFP_KER= NEL); if (!new_map) return -ENOMEM; @@ -223,6 +217,8 @@ static int ma35_pinctrl_dt_node_to_map_func(struct pinc= trl_dev *pctldev, if (!parent) return -EINVAL; =20 + setting =3D grp->data; + new_map[0].type =3D PIN_MAP_TYPE_MUX_GROUP; new_map[0].data.mux.function =3D parent->name; new_map[0].data.mux.group =3D np->name; @@ -231,9 +227,9 @@ static int ma35_pinctrl_dt_node_to_map_func(struct pinc= trl_dev *pctldev, new_map++; for (i =3D 0; i < grp->npins; i++) { new_map[i].type =3D PIN_MAP_TYPE_CONFIGS_PIN; - new_map[i].data.configs.group_or_pin =3D pin_get_name(pctldev, grp->pins= [i]); - new_map[i].data.configs.configs =3D grp->settings[i].configs; - new_map[i].data.configs.num_configs =3D grp->settings[i].nconfigs; + new_map[i].data.configs.group_or_pin =3D pin_get_name(pctldev, grp->grp.= pins[i]); + new_map[i].data.configs.configs =3D setting[i].configs; + new_map[i].data.configs.num_configs =3D setting[i].nconfigs; } dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, (*map)->data.mux.group, map_num); @@ -281,12 +277,12 @@ static int ma35_pinmux_set_mux(struct pinctrl_dev *pc= tldev, unsigned int selecto unsigned int group) { struct ma35_pinctrl *npctl =3D pinctrl_dev_get_drvdata(pctldev); - struct ma35_pin_group *grp =3D &npctl->groups[group]; - struct ma35_pin_setting *setting =3D grp->settings; + struct group_desc *grp =3D &npctl->groups[group]; + struct ma35_pin_setting *setting =3D grp->data; u32 i, regval; =20 dev_dbg(npctl->dev, "enable function %s group %s\n", - npctl->functions[selector].name, npctl->groups[group].name); + npctl->functions[selector].name, grp->grp.name); =20 for (i =3D 0; i < grp->npins; i++) { regmap_read(npctl->regmap, setting->offset, ®val); @@ -980,17 +976,16 @@ static const struct pinconf_ops ma35_pinconf_ops =3D { .is_generic =3D true, }; =20 -static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_p= in_group *grp, +static int ma35_pinctrl_parse_groups(struct device_node *np, struct group_= desc *grp, struct ma35_pinctrl *npctl, u32 index) { struct ma35_pin_setting *pin; unsigned long *configs; unsigned int nconfigs; + unsigned int *pins; int i, j, count, ret; u32 *elems; =20 - grp->name =3D np->name; - ret =3D pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs); if (ret) return ret; @@ -1003,21 +998,22 @@ static int ma35_pinctrl_parse_groups(struct device_n= ode *np, struct ma35_pin_gro if (!elems) return -ENOMEM; =20 + grp->grp.name =3D np->name; + ret =3D of_property_read_u32_array(np, "nuvoton,pins", elems, count); if (ret) return -EINVAL; + grp->grp.npins =3D count / 3; =20 - grp->npins =3D count / 3; - - grp->pins =3D devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->pins), GF= P_KERNEL); - if (!grp->pins) + pins =3D devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERN= EL); + if (!pins) return -ENOMEM; + grp->grp.pins =3D pins; =20 - grp->settings =3D devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->setti= ngs), GFP_KERNEL); - if (!grp->settings) + pin =3D devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL= ); + if (!pin) return -ENOMEM; - - pin =3D grp->settings; + grp->data =3D pin; =20 for (i =3D 0, j =3D 0; i < count; i +=3D 3, j++) { pin->offset =3D elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE; @@ -1025,7 +1021,7 @@ static int ma35_pinctrl_parse_groups(struct device_no= de *np, struct ma35_pin_gro pin->muxval =3D elems[i + 2]; pin->configs =3D configs; pin->nconfigs =3D nconfigs; - grp->pins[j] =3D npctl->info->get_pin_num(pin->offset, pin->shift); + pins[j] =3D npctl->info->get_pin_num(pin->offset, pin->shift); pin++; } return 0; @@ -1036,7 +1032,7 @@ static int ma35_pinctrl_parse_functions(struct device= _node *np, struct ma35_pinc { struct device_node *child; struct pinfunction *func; - struct ma35_pin_group *grp; + struct group_desc *grp; static u32 grp_index; const char **groups; u32 ret, i =3D 0; --=20 2.45.2