From nobody Thu Feb 12 15:47:49 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC62B174EE3; Tue, 11 Jun 2024 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095089; cv=none; b=JVWhgEsVKv5h+DJpRNPehXfBXrvFy7sNr7zCVT1Yc3AI7o+2smgw9x68HreeX0a3JVV9pxHVYnMoMyQQ8WHgVSa62SDvpy4TL+11kpGdbngIgPPl1zVJwXj6Map3gdVBdM/nQcEfEFMFrc4n0UaaVkgH/Q5TUC6YcEU7YM8uGVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095089; c=relaxed/simple; bh=7BYihXQBuufqkwpNgBcCE/uLyRVIlbtJP8Cq26n3umo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q6d7wMHXm+hXxLZ5Co4xq/T14szStNx85JKk06cicZgFOqlj8IKru5S8Jp4mznyBHLeYXDiU+m6Au/HekrIJHZyNXoMsmUjrehNN6CQQaL/9rZPTzBp1Fa+jxWD7VHAC1QnIhCTfVNQfWJvHxoxg7ddfoD7D1SxNoEqpWlFjN7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=H8ClqFHy; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="H8ClqFHy" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7YHI6027547; Tue, 11 Jun 2024 10:37:40 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= RmDzsMQhZ0rQkoG+NfxdcgkuNRhG+uLFD5UX9v+sIl8=; b=H8ClqFHyn+VuzgdH ckM88DP87fXvaSz1ua9a2qihiSP1DD4wRexr2hSG1/tm81moh2PKtPFEKlkB/tf6 GrKihJKTlYawSELVgZyMy/nAW2Mgu1UT/VWSGUjjGpLRmzJE2uTOfzcl/JO94HVn d6rkoJYKGp66mK4WA5QOoUjsY/gMvgYGM7L7IBe+8m2sEWMD2YSEdl/MdEIBBHEL xvKE8e9t6FqUE9KjVOfPsgg/RGcthTM0IjDSTiLNmNzRsOuzPY2DsK1jxs6Xj7Kj Y5yEjOZ7WngvHSPNavOAPkX97dyv7kcazTQKMbSw5H4kLY7EX04vcCF1F9GeNhfy UL9xXA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp41s44-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:37:39 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3D5FB4002D; Tue, 11 Jun 2024 10:37:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D9FFD210F68; Tue, 11 Jun 2024 10:36:19 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:36:18 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 1/8] dt-bindings: net: add STM32MP13 compatible in documentation for stm32 Date: Tue, 11 Jun 2024 10:35:59 +0200 Message-ID: <20240611083606.733453-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier Reviewed-by: Conor Dooley --- .../devicetree/bindings/net/stm32-dwmac.yaml | 43 ++++++++++++++++--- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Docum= entation/devicetree/bindings/net/stm32-dwmac.yaml index 7ccf75676b6d5..f6e5e0626a3fb 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -22,18 +22,17 @@ select: enum: - st,stm32-dwmac - st,stm32mp1-dwmac + - st,stm32mp13-dwmac required: - compatible =20 -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: - items: - enum: - st,stm32mp1-dwmac + - st,stm32mp13-dwmac - const: snps,dwmac-4.20a - items: - enum: @@ -75,12 +74,15 @@ properties: st,syscon: $ref: /schemas/types.yaml#/definitions/phandle-array items: - - items: + - minItems: 2 + items: - description: phandle to the syscon node which encompases the g= lue register - description: offset of the control register + - description: field to set mask in register description: Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register + encompases the glue register, the offset of the control register and + the mask to set bitfield in control register =20 st,ext-phyclk: description: @@ -112,12 +114,39 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-dwmac + - st,stm32-dwmac + then: + properties: + st,syscon: + items: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dwmac + then: + properties: + st,syscon: + items: + minItems: 3 + maxItems: 3 + examples: - | #include #include - #include - #include //Example 1 ethernet0: ethernet@5800a000 { compatible =3D "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; --=20 2.25.1 From nobody Thu Feb 12 15:47:50 2026 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50779174EE4; Tue, 11 Jun 2024 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095090; cv=none; b=KJ6uVwIbY+k/ikOma2KIanJRalQpVxtGGJxkHf1lAl9gsa+N6kC2YqpcSUv4NlkYInddxBhZ02ZTJtuqrF4xZqBsM9L05vsdZfc3xRVA7ViFMisd6oj1F8SpcNmXZSS43fJXEvVczXXItHZ10uHMNVny+FlrJbPs/DolRw3g9H4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095090; c=relaxed/simple; bh=CzcWoMBzn29QzER+PxKqVEeUMc90IdZvWfmL2zf9o+A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GntuZsjUcAGap3NbAS0TQAdnu5fONKUxqbD4sXCQpINZbUxTIG88Zr6iCgdtU/MIuaaX/UddCXicsLuBlSq+w08tTb4P66ubCVL07bWbIxFT8XkLA2Mb/CqLR9ASDnDYjDW4b7QKswPzqvQePmoEljOSvpDPg0MoTmGszzwikQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=m43vXEX5; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="m43vXEX5" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7UUwQ027884; Tue, 11 Jun 2024 10:37:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= hN/g428LiD5uWJnzYnUfLINd1g5a/rCwKHJfJu6r5Uo=; b=m43vXEX5fHBVEBz6 q5KhhdR1U2YTkLbBD4NX++e0XdIInSkh0wQlYrZPZDRSP0ndK4PwY+5KY7/M25au fXAu1fA2sgZr8Rn1FGSavbKbFvCXizpfnxGjo4dcEHdv5FV4yLYhy5bxx798G347 /kKR6LBgF6q/erHFzUlg8MU0D0lF+dF3pMXJpgPQOomAZ4+h+kQVwAxbx765REHP pA0225GXTw57s55yeS2ByJwSJdBnzQyEjCiSqJ2L05EsucYHlw1j/TrkxBmWlS1c nXULGxxwKjPRzIr/+1NgLgiuGYTgAru772VpIkm0Q/XJy+Rv0CQ59+KxATaEA+91 T2hTWQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp29s3s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:37:39 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7385640047; Tue, 11 Jun 2024 10:37:34 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9C64D210F73; Tue, 11 Jun 2024 10:36:20 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:36:19 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 2/8] net: stmmac: dwmac-stm32: Separate out external clock rate validation Date: Tue, 11 Jun 2024 10:36:00 +0200 Message-ID: <20240611083606.733453-3-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" From: Marek Vasut Pull the external clock frequency validation into a separate function, to avoid conflating it with external clock DT property decoding and clock mux register configuration. This should make the code easier to read and understand. This does change the code behavior slightly. The clock mux PMCR register setting now depends solely on the DT properties which configure the clock mux between external clock and internal RCC generated clock. The mux PMCR register settings no longer depend on the supplied clock frequency, that supplied clock frequency is now only validated, and if the clock frequency is invalid for a mode, it is rejected. Previously, the code would switch the PMCR register clock mux to internal RCC generated clock if external clock couldn't provide suitable frequency, without checking whether the RCC generated clock frequency is correct. Such behavior is risky at best, user should have configured their clock correctly in the first place, so this behavior is removed here. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 +++++++++++++++---- 1 file changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-stm32.c index c92dfc4ecf570..2fd2620ebed69 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -157,25 +157,54 @@ static int stm32_dwmac_init(struct plat_stmmacenet_da= ta *plat_dat, bool resume) return stm32_dwmac_clk_enable(dwmac, resume); } =20 +static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_= dat) +{ + struct stm32_dwmac *dwmac =3D plat_dat->bsp_priv; + const u32 clk_rate =3D clk_get_rate(dwmac->clk_eth_ck); + + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + if (clk_rate =3D=3D ETH_CK_F_25M) + return 0; + break; + case PHY_INTERFACE_MODE_RMII: + if (clk_rate =3D=3D ETH_CK_F_25M || clk_rate =3D=3D ETH_CK_F_50M) + return 0; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + if (clk_rate =3D=3D ETH_CK_F_25M || clk_rate =3D=3D ETH_CK_F_125M) + return 0; + break; + default: + break; + } + + dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz", + phy_modes(plat_dat->mac_interface), clk_rate); + return -EINVAL; +} + static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac =3D plat_dat->bsp_priv; - u32 reg =3D dwmac->mode_reg, clk_rate; - int val; + u32 reg =3D dwmac->mode_reg; + int val, ret; =20 - clk_rate =3D clk_get_rate(dwmac->clk_eth_ck); dwmac->enable_eth_ck =3D false; switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - if (clk_rate =3D=3D ETH_CK_F_25M && dwmac->ext_phyclk) + if (dwmac->ext_phyclk) dwmac->enable_eth_ck =3D true; val =3D SYSCFG_PMCR_ETH_SEL_MII; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val =3D SYSCFG_PMCR_ETH_SEL_GMII; - if (clk_rate =3D=3D ETH_CK_F_25M && - (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { + if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { dwmac->enable_eth_ck =3D true; val |=3D SYSCFG_PMCR_ETH_CLK_SEL; } @@ -183,8 +212,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_dat= a *plat_dat) break; case PHY_INTERFACE_MODE_RMII: val =3D SYSCFG_PMCR_ETH_SEL_RMII; - if ((clk_rate =3D=3D ETH_CK_F_25M || clk_rate =3D=3D ETH_CK_F_50M) && - (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { + if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) { dwmac->enable_eth_ck =3D true; val |=3D SYSCFG_PMCR_ETH_REF_CLK_SEL; } @@ -195,8 +223,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_dat= a *plat_dat) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: val =3D SYSCFG_PMCR_ETH_SEL_RGMII; - if ((clk_rate =3D=3D ETH_CK_F_25M || clk_rate =3D=3D ETH_CK_F_125M) && - (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { + if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { dwmac->enable_eth_ck =3D true; val |=3D SYSCFG_PMCR_ETH_CLK_SEL; } @@ -209,6 +236,10 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_da= ta *plat_dat) return -EINVAL; } =20 + ret =3D stm32mp1_validate_ethck_rate(plat_dat); + if (ret) + return ret; + /* Need to update PMCCLRR (clear register) */ regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, dwmac->ops->syscfg_eth_mask); --=20 2.25.1 From nobody Thu Feb 12 15:47:50 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFAAD171070; Tue, 11 Jun 2024 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095089; cv=none; b=b88vZzciV8V4SvEKxgXrHe/FFJbUDUl1/XZjq6Usy4FgKddqiHxx8hHwNISDc2FfxK8zT0/0LDfiARFjhLGqNY1OEaxp4RK0ts9maLMOFAZ99LIiASejDIHdmfyQag/17LvBw7cZAs+WU2Ia4CfaM1QmV4nxLX3NoEMZg3+6VRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095089; c=relaxed/simple; bh=rGcaZ0VGv8udXfKFLKOy28TL4PVRCK+Ax7blDy7Y90o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GETGMDY4ZRYMj6k+lqZbLAc4FgR5xVEbgFeoKpx5HeOAHopht0y+9+cOh8qC7Lgn26i8Wdxiy444/QJz13LAfUqg5DvaBX27jOTPGzTSNxldKPZNiC53gNlXWlb2sbLi/wEZaT1FHfmjirRAlTeqrA6I6+e8Z16qxWznKHq4Hh8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=cPXdHUPh; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="cPXdHUPh" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7Xube012243; Tue, 11 Jun 2024 10:37:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= AmLKDPb0oT6lLe6SQe3GR2w8UgmNAhsCLM0PNSYGh9g=; b=cPXdHUPh1Ysy+xWh x69Gpz8FJl6JSBHL7auQ+lYzBcFY22aKxPcII0gmc6RqlqDK2NDKHH+HQ2M/IGqb z4mNR1QzGN4J7QyFCqlybD51OKu6k0OVsW/hrSmr1sZcb7zkOl4z4IS4PjOEi1de 6/UfZjC9x5QAblLfdcriYA2WntYWW/pCopZGwspj9xmoBX9glZ1RKIdbsUKFyC8L Fk/tZVs89pL2Eq7pp+c7dHKkLCYPpHh1Pnmzl/YuQXMzr6bkDMYfYGMsG5LZZ9CB 0cX0xuIePwonJkMOaGa1OMG3YzWbQBze6Ilm1HyO0uMPQ4Aa38jO9nin8H/69HmQ pKI6TA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp3srxn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:37:39 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4101F40046; Tue, 11 Jun 2024 10:37:34 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 618192115EF; Tue, 11 Jun 2024 10:36:21 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:36:20 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 3/8] net: stmmac: dwmac-stm32: Separate out external clock selector Date: Tue, 11 Jun 2024 10:36:01 +0200 Message-ID: <20240611083606.733453-4-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" From: Marek Vasut Pull the external clock selector into a separate function, to avoid conflating it with external clock rate validation and clock mux register configuration. This should make the code easier to read and understand. The dwmac->enable_eth_ck variable in the end indicates whether the MAC clock are supplied by external oscillator (true) or internal RCC clock IP (false). The dwmac->enable_eth_ck value is set based on multiple DT properties, some of them deprecated, some of them specific to bus mode. The following DT properties and variables are taken into account. In each case, if the property is present or true, MAC clock is supplied by external oscillator. - "st,ext-phyclk", assigned to variable dwmac->ext_phyclk - Used in any mode (MII/RMII/GMII/RGMII) - The only non-deprecated DT property of the three - "st,eth-clk-sel", assigned to variable dwmac->eth_clk_sel_reg - Valid only in GMII/RGMII mode - Deprecated property, backward compatibility only - "st,eth-ref-clk-sel", assigned to variable dwmac->eth_ref_clk_sel_reg - Valid only in RMII mode - Deprecated property, backward compatibility only The stm32mp1_select_ethck_external() function handles the aforementioned DT properties and sets dwmac->enable_eth_ck accordingly. The stm32mp1_set_mode() is adjusted to call stm32mp1_select_ethck_external() first and then only use dwmac->enable_eth_ck to determine hardware clock mux settings. No functional change intended. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 ++++++++++++++----- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-stm32.c index 2fd2620ebed69..767994061ea82 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -157,6 +157,37 @@ static int stm32_dwmac_init(struct plat_stmmacenet_dat= a *plat_dat, bool resume) return stm32_dwmac_clk_enable(dwmac, resume); } =20 +static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *pla= t_dat) +{ + struct stm32_dwmac *dwmac =3D plat_dat->bsp_priv; + + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + dwmac->enable_eth_ck =3D dwmac->ext_phyclk; + return 0; + case PHY_INTERFACE_MODE_GMII: + dwmac->enable_eth_ck =3D dwmac->eth_clk_sel_reg || + dwmac->ext_phyclk; + return 0; + case PHY_INTERFACE_MODE_RMII: + dwmac->enable_eth_ck =3D dwmac->eth_ref_clk_sel_reg || + dwmac->ext_phyclk; + return 0; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + dwmac->enable_eth_ck =3D dwmac->eth_clk_sel_reg || + dwmac->ext_phyclk; + return 0; + default: + dwmac->enable_eth_ck =3D false; + dev_err(dwmac->dev, "Mode %s not supported", + phy_modes(plat_dat->mac_interface)); + return -EINVAL; + } +} + static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_= dat) { struct stm32_dwmac *dwmac =3D plat_dat->bsp_priv; @@ -194,28 +225,25 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_d= ata *plat_dat) u32 reg =3D dwmac->mode_reg; int val, ret; =20 - dwmac->enable_eth_ck =3D false; + ret =3D stm32mp1_select_ethck_external(plat_dat); + if (ret) + return ret; + switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - if (dwmac->ext_phyclk) - dwmac->enable_eth_ck =3D true; val =3D SYSCFG_PMCR_ETH_SEL_MII; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val =3D SYSCFG_PMCR_ETH_SEL_GMII; - if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { - dwmac->enable_eth_ck =3D true; + if (dwmac->enable_eth_ck) val |=3D SYSCFG_PMCR_ETH_CLK_SEL; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: val =3D SYSCFG_PMCR_ETH_SEL_RMII; - if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) { - dwmac->enable_eth_ck =3D true; + if (dwmac->enable_eth_ck) val |=3D SYSCFG_PMCR_ETH_REF_CLK_SEL; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; case PHY_INTERFACE_MODE_RGMII: @@ -223,10 +251,8 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_da= ta *plat_dat) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: val =3D SYSCFG_PMCR_ETH_SEL_RGMII; - if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { - dwmac->enable_eth_ck =3D true; + if (dwmac->enable_eth_ck) val |=3D SYSCFG_PMCR_ETH_CLK_SEL; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); break; default: --=20 2.25.1 From nobody Thu Feb 12 15:47:50 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CD8E174EE8; Tue, 11 Jun 2024 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095091; cv=none; b=Xk9sdD2vT9TKmjZI/eZyxR+9cSikavUD26aWxGTLgwXe0uvHVFgQjtyBc8N1JwtuJY+8ITd+A/yN/TnsCt+zDmXZ2lOAP9MZhEfrDdLN0DrLJnG6tbDgOYrQ52LNn9d1fk2PhO9X/Vo0uMNlX53OU5WzqMtVPNu6xvDTlOP/b1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095091; c=relaxed/simple; bh=44rSWXOArPy/nwNCOMu/STRv8rbBnxvUb7+aOkzlfqY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IOSSkAOHMyRFXVelfmPPiNcIDgm/h32+PSJf8gp263cG4ed0HZc93GoRWwAFS8obybqFm8FCdFbPJOle/EYu7JTswsvBht9Puhv1iwFFIBCc4aCIC1GuGnINluFNISXLDbe72LAoLFv7h6u89Dv/yNGRDCHWIjff3TZg7W95uJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=O2KOsCjs; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="O2KOsCjs" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7kpCH017587; Tue, 11 Jun 2024 10:37:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= gcGnG4i9tCteB7NRoLMx/qe1YZ2BfUZUoQrTCLrUGP8=; b=O2KOsCjsKQ6pyhKc cKEyhjvEcnRyzaWEJS2eEsFIG5zkrCX5H467PaS1lY4pANSNsa4HBCI/DS86tA2S d34AzhRlV2lnVFY4cBqmrZBX5olACjX7Jkp6p7pZ8Xi4kSDj/p1vVIb/P2xwVNL3 6gAJNLqMEYlB7QXq/tCljJuZ1oF+mjz7fY4puoAMZTg5Pp6Bu7FDW2v5x12NYhtL P0/e11lFpdyRjTIXkJnB6HLC+or/5GNWPlMlfQSkDo7nqh/Rce5d/dhp17goxvvZ 1rQpNcLar45vqZS4oYdR3cU8ozxxWUSByYpCVab/lV6Ua6oHUMYLE7hoh21tp40X yeaOBA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp2htuj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:37:39 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3EA2440045; Tue, 11 Jun 2024 10:37:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 200AF2115FA; Tue, 11 Jun 2024 10:36:22 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:36:21 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 4/8] net: stmmac: dwmac-stm32: Extract PMCR configuration Date: Tue, 11 Jun 2024 10:36:02 +0200 Message-ID: <20240611083606.733453-5-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" From: Marek Vasut Pull the PMCR clock mux configuration into a separate function. This is the final change of three, which moves external clock rate validation, external clock selector decoding, and clock mux configuration into separate functions. This should make the code easier to understand. No functional change intended. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 27 ++++++++++++------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-stm32.c index 767994061ea82..aa413edd1ef71 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -219,15 +219,11 @@ static int stm32mp1_validate_ethck_rate(struct plat_s= tmmacenet_data *plat_dat) return -EINVAL; } =20 -static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) +static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac =3D plat_dat->bsp_priv; u32 reg =3D dwmac->mode_reg; - int val, ret; - - ret =3D stm32mp1_select_ethck_external(plat_dat); - if (ret) - return ret; + int val; =20 switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: @@ -262,10 +258,6 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_da= ta *plat_dat) return -EINVAL; } =20 - ret =3D stm32mp1_validate_ethck_rate(plat_dat); - if (ret) - return ret; - /* Need to update PMCCLRR (clear register) */ regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, dwmac->ops->syscfg_eth_mask); @@ -275,6 +267,21 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_da= ta *plat_dat) dwmac->ops->syscfg_eth_mask, val); } =20 +static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) +{ + int ret; + + ret =3D stm32mp1_select_ethck_external(plat_dat); + if (ret) + return ret; + + ret =3D stm32mp1_validate_ethck_rate(plat_dat); + if (ret) + return ret; + + return stm32mp1_configure_pmcr(plat_dat); +} + static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac =3D plat_dat->bsp_priv; --=20 2.25.1 From nobody Thu Feb 12 15:47:50 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D15C17556E; Tue, 11 Jun 2024 08:39:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095151; cv=none; b=hXgeem/Qg6EzgskJVJjK5aBOP4l90D6vyS2zXNJaOAMIUjftRRwg0pqFR4XYcNJSDC9XmDd1ZEwFysAVF+SxbEeY6mbNgaIR89x8y/4rcsGCImSqfIqTO+gWQz8wTn9+2b+xWr8WN/dGWXJSBPPcO39GVRlJrrwoKP+nGqG3erQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095151; c=relaxed/simple; bh=Wz7+F3RX2ErVq2AoH1Oy/dBnTV8neAuhbUlnFn1Nr6k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=imca85nNuOQRL5+JqfT5HSSZYqPmlSdMb3s3z7c4MgX2gYAkaWj03PoQrgM0FTHQgAAEn3oFQZ1m2kJ28gjugf9EgXYRzRG+4pybmbB+AHxgLijgkbb8BeFLeCKxsE2tZ2sxPq1Omba8EjdZGVTVAN0WaYjYXDCh4n/ysIaBeXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=yfwjcePS; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="yfwjcePS" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7g83u011467; Tue, 11 Jun 2024 10:38:42 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= oZt3ANozAyCi4RMnooDgV1ukrsEF0MYMZVmMcPQZSJw=; b=yfwjcePSoDlZEpN1 6GY4ERcjBxCSIunfRaNoeUJD3DhDoKOjB7VfrGBKj6zgD7JWaeYV7JzvHIe3shtZ U76StDK2g7Vc0o/VcU21G5qXOzXqzAkp/zcL0PXxnzWI4MJ+byTEba002mY+6y/Z 8xmglxoNlWij78m/8RVwbxwWFVxdRHz4P3lbiSYeKMD9LShBZo7kHgunuI9G8qHS Ob7ekrDq4sLJ0l/xPln+mIC6DIgND2BYeVt8PD/FeG8F46XT5LOWRtocp/X4JQdi Lprgf2ZpiFF9rZUc6NUTW7TF0/6w6VW+Dn8bwdLo8J13qpqtPFJA9mtdMr34q/7X 3orYmw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp3ss42-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:38:42 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id BA08440045; Tue, 11 Jun 2024 10:38:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id DF6542115F4; Tue, 11 Jun 2024 10:37:32 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:37:31 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 5/8] net: stmmac: dwmac-stm32: Clean up the debug prints Date: Tue, 11 Jun 2024 10:36:03 +0200 Message-ID: <20240611083606.733453-6-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" From: Marek Vasut Use dev_err()/dev_dbg() and phy_modes() to print PHY mode instead of pr_debug() and hand-written PHY mode decoding. This way, each debug print has associated device with it and duplicated mode decoding is removed. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-stm32.c index aa413edd1ef71..75981ac2cbb56 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -228,19 +228,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmac= enet_data *plat_dat) switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: val =3D SYSCFG_PMCR_ETH_SEL_MII; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val =3D SYSCFG_PMCR_ETH_SEL_GMII; if (dwmac->enable_eth_ck) val |=3D SYSCFG_PMCR_ETH_CLK_SEL; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: val =3D SYSCFG_PMCR_ETH_SEL_RMII; if (dwmac->enable_eth_ck) val |=3D SYSCFG_PMCR_ETH_REF_CLK_SEL; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: @@ -249,15 +246,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmac= enet_data *plat_dat) val =3D SYSCFG_PMCR_ETH_SEL_RGMII; if (dwmac->enable_eth_ck) val |=3D SYSCFG_PMCR_ETH_CLK_SEL; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); break; default: - pr_debug("SYSCFG init : Do not manage %d interface\n", - plat_dat->mac_interface); + dev_err(dwmac->dev, "Mode %s not supported", + phy_modes(plat_dat->mac_interface)); /* Do not manage others interfaces */ return -EINVAL; } =20 + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + /* Need to update PMCCLRR (clear register) */ regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, dwmac->ops->syscfg_eth_mask); @@ -291,19 +289,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_d= ata *plat_dat) switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: val =3D SYSCFG_MCU_ETH_SEL_MII; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_RMII: val =3D SYSCFG_MCU_ETH_SEL_RMII; - pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; default: - pr_debug("SYSCFG init : Do not manage %d interface\n", - plat_dat->mac_interface); + dev_err(dwmac->dev, "Mode %s not supported", + phy_modes(plat_dat->mac_interface)); /* Do not manage others interfaces */ return -EINVAL; } =20 + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + return regmap_update_bits(dwmac->regmap, reg, dwmac->ops->syscfg_eth_mask, val << 23); } --=20 2.25.1 From nobody Thu Feb 12 15:47:50 2026 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D97DE172BDE; Tue, 11 Jun 2024 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095089; cv=none; b=o/TCHFUfGtlurv+s9m0QNiH+wsFp2dteCLoLHhMAGNUMucXuhrX/eEN1PhA4/kbA5FoC9/j3PvFPq5rYT7gL/0T2KsEEQA2uWvHlT9/0KUU5rUsR3Y9dEplEcpnv5Aj1my29SXMnwq0WuLoTfhvWfOstwmrg4MUqcGLSJzHk2fQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095089; c=relaxed/simple; bh=M+fVmHCFaPcyzs+u8Y7ZQVNcblX1uciwc4OMn2nzd0Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZIoPD4wz2Hfqxr+u8u2Xi7Fh1YFSF4PWcYNspx6xBnsWCXKbJRPSLaUPV6AxB2/RiZLNp0uo0cT42KkhIIus/P9xeWuq1/8RTAkbu6XJlDxHvDZvz5lp1oIq0wNNwxCA7RDCm6FKe+3RcZoUDmy3nfbepAA9AFriQL6a4A1tKW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=4qYnqddm; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="4qYnqddm" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7ZAJR027844; Tue, 11 Jun 2024 10:37:44 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= JuDY0iqj5TDTqcNiIz4Nr9QUlzV7muTWZdShmUmLed0=; b=4qYnqddm2gJeojSn bQEx0Pb0YewJiH39IpyjqaOXQhQL4AywTouJS+BjbaL3DrqnUYr8g5oZh+4Ykulo GC88/3ja1DDBdrXHwXq3c7xYHnFb7ZsfY/Jpa+zblDfiVxNhLL+iweX7AFc0tDpg Mn3kld+/HxljYGhsdKU6BNkmBI38F/OY4BDSXdygM04Ar2K2z7DC986ibh9GqNHc 02a6q7jmRdLEc7BKJkfv/rGlcx7oleJcOaOd4XaKpUSGG91/aefAVtLEpZgrWS9n xrB296LfWqr7AslbgfGQDPv1DRY443BGtEzJR23XuLP/o0cRW4rwTsZEXr5QzVw0 J8Q6kw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp29s42-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:37:44 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EE44E40048; Tue, 11 Jun 2024 10:37:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A0403211606; Tue, 11 Jun 2024 10:37:33 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:37:32 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 6/8] net: stmmac: dwmac-stm32: Fix Mhz to MHz Date: Tue, 11 Jun 2024 10:36:04 +0200 Message-ID: <20240611083606.733453-7-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" From: Marek Vasut Trivial, fix up the comments using 'Mhz' to 'MHz'. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Christophe Roullier --- drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-stm32.c index 75981ac2cbb56..bed2be129b2d2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -58,7 +58,7 @@ * Below table summarizes the clock requirement and clock sources for * supported phy interface modes. * _______________________________________________________________________= ___ - *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from = PHY| + *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from = PHY| *| | | 25MHz | 50MHz | = | * -----------------------------------------------------------------------= ---- *| MII | - | eth-ck | n/a | n/a | @@ -367,7 +367,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwma= c, /* Gigabit Ethernet 125MHz clock selection. */ dwmac->eth_clk_sel_reg =3D of_property_read_bool(np, "st,eth-clk-sel"); =20 - /* Ethernet 50Mhz RMII clock selection */ + /* Ethernet 50MHz RMII clock selection */ dwmac->eth_ref_clk_sel_reg =3D of_property_read_bool(np, "st,eth-ref-clk-sel"); =20 --=20 2.25.1 From nobody Thu Feb 12 15:47:50 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B68F174EE7; Tue, 11 Jun 2024 08:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095090; cv=none; b=KC6Sru9j4cmSVkjsCxMTxg1uBNoxt4ET3PvpGMnuo49vqrCraamqu/2mwEKG4z0fOUsAOooiwPa6NoTG8X4b98iUhLJNdkwbBNs/ishmOCn86C7qYV0cXGtITYURZuzEPOPQ4bHoL0JlMtQWW2hJUVNIjoZ1XB/lpvv3qbY0AvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095090; c=relaxed/simple; bh=H8eiIzBHxQY9PUGjusuwqWX+XJdF4wVRO6RyxVH63Xs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I++7xZDtmWasAUq6L/uz1yq/Rfz4ao/Svot6cqwBOvAtcccqnv/2G/HMT1t57yvdJeXnmql0wHuS0Jyflg9JnJ+k7jjsbC8nKQjnQ3DE4iXUtmZLOiBjEaOEZtwj7igXvhcE+8jREypdn/mI8jzd+9seONfF7NXM0auYHF3t9vQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=FTN8aBmU; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="FTN8aBmU" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7dH5K015661; Tue, 11 Jun 2024 10:37:44 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= tKwMHB/a9GI7zhrFn6hxQvgCOtZi4d3e8K6lurTX/xA=; b=FTN8aBmUmf77FG/w zBDrcGfXaKwFKGNkGF7v3+Ue8S0YfCHfe6scdyD6W50H7GE0WJ4HD3keioMXP5lu fQ/B9G6wtgxEyvhT07kz5ww54M3ErghayWcr1peiU9gfJ4WPsiTPz5l0Uy6SXKRY DO90fu0BjIqXf86ph8sY1w3dsgPGhxtWG9CQIevhyI2XxA0ips+CYT8wWSLIfkIN WoByTmTmaaE1XPVeixiTIYh7s1HzSM3pBHapcPoxFT+w2Szak4GE9x08G2A/6Mys aBDg4PlxTOQQMV/2KUCbFGMJJjigIkYeHQOJY+fNZx5vcx4xnPVzZd0/Bvx1lLWD lo4FZw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp4htd4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:37:44 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id AF4F640049; Tue, 11 Jun 2024 10:37:38 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 62633211607; Tue, 11 Jun 2024 10:37:34 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:37:33 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 7/8] net: stmmac: dwmac-stm32: Mask support for PMCR configuration Date: Tue, 11 Jun 2024 10:36:05 +0200 Message-ID: <20240611083606.733453-8-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" Add possibility to have second argument in syscon property to manage mask. This mask will be used to address right BITFIELDS of PMCR register. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 28 +++++++++++++------ 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-stm32.c index bed2be129b2d2..09ff0be0bdcdc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -90,6 +90,7 @@ struct stm32_dwmac { int eth_ref_clk_sel_reg; int irq_pwr_wakeup; u32 mode_reg; /* MAC glue-logic mode register */ + u32 mode_mask; struct regmap *regmap; u32 speed; const struct stm32_ops *ops; @@ -102,8 +103,8 @@ struct stm32_ops { void (*resume)(struct stm32_dwmac *dwmac); int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); - u32 syscfg_eth_mask; bool clk_rx_enable_in_suspend; + u32 syscfg_clr_off; }; =20 static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume) @@ -256,13 +257,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmac= enet_data *plat_dat) =20 dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); =20 + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ + val <<=3D ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK); + /* Need to update PMCCLRR (clear register) */ - regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, - dwmac->ops->syscfg_eth_mask); + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, + dwmac->mode_mask); =20 /* Update PMCSETR (set register) */ return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val); + dwmac->mode_mask, val); } =20 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) @@ -303,7 +307,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_dat= a *plat_dat) dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); =20 return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val << 23); + SYSCFG_MCU_ETH_MASK, val << 23); } =20 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspen= d) @@ -348,8 +352,15 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *= dwmac, return PTR_ERR(dwmac->regmap); =20 err =3D of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); - if (err) + if (err) { dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); + return err; + } + + dwmac->mode_mask =3D SYSCFG_MP1_ETH_MASK; + err =3D of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); + if (err) + dev_dbg(dev, "Warning sysconfig register mask not set\n"); =20 return err; } @@ -540,8 +551,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, stm32_dwmac_suspend, stm32_dwmac_resume); =20 static struct stm32_ops stm32mcu_dwmac_data =3D { - .set_mode =3D stm32mcu_set_mode, - .syscfg_eth_mask =3D SYSCFG_MCU_ETH_MASK + .set_mode =3D stm32mcu_set_mode }; =20 static struct stm32_ops stm32mp1_dwmac_data =3D { @@ -549,7 +559,7 @@ static struct stm32_ops stm32mp1_dwmac_data =3D { .suspend =3D stm32mp1_suspend, .resume =3D stm32mp1_resume, .parse_data =3D stm32mp1_parse_data, - .syscfg_eth_mask =3D SYSCFG_MP1_ETH_MASK, + .syscfg_clr_off =3D 0x44, .clk_rx_enable_in_suspend =3D true }; =20 --=20 2.25.1 From nobody Thu Feb 12 15:47:50 2026 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDBFE176AC7; Tue, 11 Jun 2024 08:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095158; cv=none; b=kfYPW6LKLIcNULGf8KidW2I6addYSw3PxD67HDG1aId0C6BYLP+E+K0EMWdNfxldTsuMzXZ8i/HZZZTEe9NwPsWOZ0nNJFnBEj4QZA+Ma8nO/7vS7QmuAZ/GbqZNRGj74Hj7wCrKK0h0edkuoypZxs9oFVjxeQ7iuaOOhdl+Hr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718095158; c=relaxed/simple; bh=+1XqWT8gTuEmj8fP2hazFM3zcgz/1L1BGI1c6epxojQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O23cYBy78m4yGGN2gp239/I/hAWeq9OObsvQuUzyWJiTtUE+RlRC4HKdXZZBPYpfjM8qluMYDDB4eCQynK1igRZYrXZWSLpZYZhlDwgjRR8kgwDAON331vpisCfCVgs2RhcjX/WFdaF36+vagfPkV5h7VgZs6dnsjT5J3xaIKfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=5qz/Ktyq; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="5qz/Ktyq" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45B7dlRR027839; Tue, 11 Jun 2024 10:38:53 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= tczm6qTSViwTLH/qT7QMjrs9/mSv8f7on1Dp4y1LX4Y=; b=5qz/Ktyq7Fb9YXER 6RKJK2KEiwQ241jF+xpYRg1WHe07I4m5CZf0MupFPjohySQ91g9sKUWUVqvOsTq7 e9HtNBNDneSaU6c+nK5+UqaURUocMY6XJQcdjVUibsBzMszYksnrgPIOeYwo4jum xF9uzVY6TJrAOkdChq/GrrzBUjY7k7KPOmd9HPMYPIrW1cSBhmOerMElNfzybJwj d3myGoAwpIiuywHfkYcFGLNG+wwbBuW0byIqRtBG5YUk7cQSzABIP5oYa2uyBm3t IhS52WqIk7etdt9cGvCwC5ctqKN+2LjZJoXJQfI0f5rPI/8ArgWGvWIcJyJ0UbVt fc69lQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp29s9v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 10:38:52 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EBA684002D; Tue, 11 Jun 2024 10:38:48 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1E7CC21160A; Tue, 11 Jun 2024 10:37:35 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 10:37:34 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [net-next,PATCH v7 8/8] net: stmmac: dwmac-stm32: add management of stm32mp13 for stm32 Date: Tue, 11 Jun 2024 10:36:06 +0200 Message-ID: <20240611083606.733453-9-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611083606.733453-1-christophe.roullier@foss.st.com> References: <20240611083606.733453-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 Content-Type: text/plain; charset="utf-8" Add Ethernet support for STM32MP13. STM32MP13 is STM32 SOC with 2 GMACs instances. GMAC IP version is SNPS 4.20. GMAC IP configure with 1 RX and 1 TX queue. DMA HW capability register supported RX Checksum Offload Engine supported TX Checksum insertion supported Wake-Up On Lan supported TSO supported Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 32 ++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-stm32.c index 09ff0be0bdcdc..b2db0e26c4e45 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -104,6 +104,7 @@ struct stm32_ops { int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); bool clk_rx_enable_in_suspend; + bool is_mp13; u32 syscfg_clr_off; }; =20 @@ -224,11 +225,18 @@ static int stm32mp1_configure_pmcr(struct plat_stmmac= enet_data *plat_dat) { struct stm32_dwmac *dwmac =3D plat_dat->bsp_priv; u32 reg =3D dwmac->mode_reg; - int val; + int val =3D 0; =20 switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - val =3D SYSCFG_PMCR_ETH_SEL_MII; + /* + * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. + * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and + * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx + * supports only MII, ETH_SELMII is not present. + */ + if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */ + val |=3D SYSCFG_PMCR_ETH_SEL_MII; break; case PHY_INTERFACE_MODE_GMII: val =3D SYSCFG_PMCR_ETH_SEL_GMII; @@ -359,8 +367,12 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *= dwmac, =20 dwmac->mode_mask =3D SYSCFG_MP1_ETH_MASK; err =3D of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); - if (err) - dev_dbg(dev, "Warning sysconfig register mask not set\n"); + if (err) { + if (dwmac->ops->is_mp13) + dev_err(dev, "Sysconfig register mask must be set (%d)\n", err); + else + dev_dbg(dev, "Warning sysconfig register mask not set\n"); + } =20 return err; } @@ -560,12 +572,24 @@ static struct stm32_ops stm32mp1_dwmac_data =3D { .resume =3D stm32mp1_resume, .parse_data =3D stm32mp1_parse_data, .syscfg_clr_off =3D 0x44, + .is_mp13 =3D false, + .clk_rx_enable_in_suspend =3D true +}; + +static struct stm32_ops stm32mp13_dwmac_data =3D { + .set_mode =3D stm32mp1_set_mode, + .suspend =3D stm32mp1_suspend, + .resume =3D stm32mp1_resume, + .parse_data =3D stm32mp1_parse_data, + .syscfg_clr_off =3D 0x08, + .is_mp13 =3D true, .clk_rx_enable_in_suspend =3D true }; =20 static const struct of_device_id stm32_dwmac_match[] =3D { { .compatible =3D "st,stm32-dwmac", .data =3D &stm32mcu_dwmac_data}, { .compatible =3D "st,stm32mp1-dwmac", .data =3D &stm32mp1_dwmac_data}, + { .compatible =3D "st,stm32mp13-dwmac", .data =3D &stm32mp13_dwmac_data}, { } }; MODULE_DEVICE_TABLE(of, stm32_dwmac_match); --=20 2.25.1