From nobody Thu Feb 12 17:27:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AFE04D9EA for ; Mon, 10 Jun 2024 20:17:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718050675; cv=none; b=pDk73c6OsoymJV5wp6HM+qClDTSrbhADxBuJxi8wrTnGNQ4CRHuG2PsOFrNMu/cWWwHq7cQ1anWXjStPFZmheA/64HMMY0PP+9iwqwYyjGMzMwKhA3uFHoFrFT8CASbgVeJTlXlY7sxwy5/kTrUasUhatKKUMfqbGI5su0sjkfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718050675; c=relaxed/simple; bh=kLr54QFbf/02KbIzN+8gT4RlmHSZj0T4yj3bzu8+hYQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ruVv8Z5cLHarQKH6y68QCqIKz28udkJo62D05BPh7ZAFoH9gebN5nDz4KUbAtah8ZqzdZK9nQxcLoyabo2DVCs7xyFWmQCc+UlvaibM0HORkmHQVc19+ChPb4M7DhboUfjQfNxsWoQ16wBe+LMTKUNI/ZJ0VHFNWga7EXCIcFec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nPcaH5ZS; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nPcaH5ZS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718050674; x=1749586674; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kLr54QFbf/02KbIzN+8gT4RlmHSZj0T4yj3bzu8+hYQ=; b=nPcaH5ZSdvNJziepX4aGzplrsSOY1H68E4sViZYGB26Dek3q3V5qvXzd tPGm88fKBjBHZ3fL5CKkDiig41c8x5exjqpa659KUuHLxIc/WThUAIMnL e8ghDvkFk2U8egb70E+X2BYM5NgkOqz2m+GHRrhco4LBLKTcvxfUUqKfF 3PHrp/1Jl4rvPliNJI4UdK0eepHbPc9jogjW9ldX6GVZQZV2IbFCpmA1l 3RFOjuZFKx2QPEG96WohylNg7IsGoVKXT5/IUGQHfamZmArVE7fOH2XRz tE4CsP28omt5iwpD+kUd87jkFAXUKXn2Fm/HEliQ4/bo+XufJAm7kbBLG w==; X-CSE-ConnectionGUID: uRVDsYuoQ1CtkXUYOpyoZA== X-CSE-MsgGUID: HWzTxfZwTO+RTawVYhvqcw== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="18561527" X-IronPort-AV: E=Sophos;i="6.08,227,1712646000"; d="scan'208";a="18561527" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2024 13:17:51 -0700 X-CSE-ConnectionGUID: eN/u640+ToeRuuwkN9L3gQ== X-CSE-MsgGUID: BrwsKLQqSS+ofUP6RTDigA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,227,1712646000"; d="scan'208";a="39169095" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa008.fm.intel.com with ESMTP; 10 Jun 2024 13:17:51 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, namhyung@kernel.org, irogers@google.com, eranian@google.com, ak@linux.intel.com, yunying.sun@intel.com, Kan Liang Subject: [PATCH 5/8] perf/x86/uncore: Apply the unit control RB tree to MSR uncore units Date: Mon, 10 Jun 2024 13:16:16 -0700 Message-Id: <20240610201619.884021-6-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240610201619.884021-1-kan.liang@linux.intel.com> References: <20240610201619.884021-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The unit control RB tree has the unit control and unit ID information for all the MSR units. Use them to replace the box_ctl and uncore_msr_box_ctl() to get an accurate unit control address for MSR uncore units. Add intel_generic_uncore_assign_hw_event(), which utilizes the accurate unit control address from the unit control RB tree to calculate the config_base and event_base. The unit id related information should be retrieved from the unit control RB tree as well. Tested-by: Yunying Sun Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 3 ++ arch/x86/events/intel/uncore_discovery.c | 49 +++++++++++++++++++++--- arch/x86/events/intel/uncore_discovery.h | 2 + arch/x86/events/intel/uncore_snbep.c | 16 +++++--- 4 files changed, 59 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 27a0cda5cc91..bdb253a1bc3b 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -264,6 +264,9 @@ static void uncore_assign_hw_event(struct intel_uncore_= box *box, return; } =20 + if (intel_generic_uncore_assign_hw_event(event, box)) + return; + hwc->config_base =3D uncore_event_ctl(box, hwc->idx); hwc->event_base =3D uncore_perf_ctr(box, hwc->idx); } diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index ece761c9f17a..076ec1efe9cc 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -499,19 +499,31 @@ static const struct attribute_group generic_uncore_fo= rmat_group =3D { .attrs =3D generic_uncore_formats_attr, }; =20 +static u64 intel_generic_uncore_box_ctl(struct intel_uncore_box *box) +{ + struct intel_uncore_discovery_unit *unit; + + unit =3D intel_uncore_find_discovery_unit(box->pmu->type->boxes, + -1, box->pmu->pmu_idx); + if (WARN_ON_ONCE(!unit)) + return 0; + + return unit->addr; +} + void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) { - wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); + wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); } =20 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) { - wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); + wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); } =20 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box) { - wrmsrl(uncore_msr_box_ctl(box), 0); + wrmsrl(intel_generic_uncore_box_ctl(box), 0); } =20 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box = *box, @@ -539,6 +551,31 @@ static struct intel_uncore_ops generic_uncore_msr_ops = =3D { .read_counter =3D uncore_msr_read_counter, }; =20 +bool intel_generic_uncore_assign_hw_event(struct perf_event *event, + struct intel_uncore_box *box) +{ + struct hw_perf_event *hwc =3D &event->hw; + u64 box_ctl; + + if (!box->pmu->type->boxes) + return false; + + if (box->pci_dev || box->io_addr) { + hwc->config_base =3D uncore_pci_event_ctl(box, hwc->idx); + hwc->event_base =3D uncore_pci_perf_ctr(box, hwc->idx); + return true; + } + + box_ctl =3D intel_generic_uncore_box_ctl(box); + if (!box_ctl) + return false; + + hwc->config_base =3D box_ctl + box->pmu->type->event_ctl + hwc->idx; + hwc->event_base =3D box_ctl + box->pmu->type->perf_ctr + hwc->idx; + + return true; +} + void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; @@ -697,10 +734,12 @@ static bool uncore_update_uncore_type(enum uncore_acc= ess_type type_id, switch (type_id) { case UNCORE_ACCESS_MSR: uncore->ops =3D &generic_uncore_msr_ops; - uncore->perf_ctr =3D (unsigned int)type->box_ctrl + type->ctr_offset; - uncore->event_ctl =3D (unsigned int)type->box_ctrl + type->ctl_offset; + uncore->perf_ctr =3D (unsigned int)type->ctr_offset; + uncore->event_ctl =3D (unsigned int)type->ctl_offset; uncore->box_ctl =3D (unsigned int)type->box_ctrl; uncore->msr_offsets =3D type->box_offset; + uncore->boxes =3D &type->units; + uncore->num_boxes =3D type->num_units; break; case UNCORE_ACCESS_PCI: uncore->ops =3D &generic_uncore_pci_ops; diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 96265cf1fc86..4a7a7c819d6f 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -169,3 +169,5 @@ intel_uncore_generic_init_uncores(enum uncore_access_ty= pe type_id, int num_extra =20 int intel_uncore_find_discovery_unit_id(struct rb_root *units, int die, unsigned int pmu_idx); +bool intel_generic_uncore_assign_hw_event(struct perf_event *event, + struct intel_uncore_box *box); diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 74b8b21e8990..8b1cabff7ee3 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5933,10 +5933,11 @@ static int spr_cha_hw_config(struct intel_uncore_bo= x *box, struct perf_event *ev struct hw_perf_event_extra *reg1 =3D &event->hw.extra_reg; bool tie_en =3D !!(event->hw.config & SPR_CHA_PMON_CTL_TID_EN); struct intel_uncore_type *type =3D box->pmu->type; + int id =3D intel_uncore_find_discovery_unit_id(type->boxes, -1, box->pmu-= >pmu_idx); =20 if (tie_en) { reg1->reg =3D SPR_C0_MSR_PMON_BOX_FILTER0 + - HSWEP_CBO_MSR_OFFSET * type->box_ids[box->pmu->pmu_idx]; + HSWEP_CBO_MSR_OFFSET * id; reg1->config =3D event->attr.config1 & SPR_CHA_PMON_BOX_FILTER_TID; reg1->idx =3D 0; } @@ -6460,18 +6461,21 @@ uncore_find_type_by_id(struct intel_uncore_type **t= ypes, int type_id) static int uncore_type_max_boxes(struct intel_uncore_type **types, int type_id) { + struct intel_uncore_discovery_unit *unit; struct intel_uncore_type *type; - int i, max =3D 0; + struct rb_node *node; + int max =3D 0; =20 type =3D uncore_find_type_by_id(types, type_id); if (!type) return 0; =20 - for (i =3D 0; i < type->num_boxes; i++) { - if (type->box_ids[i] > max) - max =3D type->box_ids[i]; - } + for (node =3D rb_first(type->boxes); node; node =3D rb_next(node)) { + unit =3D rb_entry(node, struct intel_uncore_discovery_unit, node); =20 + if (unit->id > max) + max =3D unit->id; + } return max + 1; } =20 --=20 2.35.1