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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240610-xtheadvector-v2-5-97a48613ad64@rivosinc.com> References: <20240610-xtheadvector-v2-0-97a48613ad64@rivosinc.com> In-Reply-To: <20240610-xtheadvector-v2-0-97a48613ad64@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718060203; l=4477; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=JhqG4ZdS5QKzlPRzZcQfxAwTqc9C8rDVsHlpi4B1vOI=; b=oqpa4Eli9MHtw6c16Ousxh0D7rEs825z8yDABx/PRHTn3AlKGPjpbVc+L+JAxd3GB8VHSTo90 Rk75YiFR8pxBfawfOTvMriD8bmviIfjb2IiMl7RiVpecdLwPnRINAh9 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.vendor | 13 ++++++++++ arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/kernel/cpufeature.c | 48 +++++++++++++++++++++++++++++++++= ++++ arch/riscv/kernel/vector.c | 12 +++++++++- 4 files changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 9897442bd44f..b096548fe0ff 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -26,6 +26,19 @@ config RISCV_ISA_VENDOR_EXT_THEAD extensions. Without this option enabled, T-Head vendor extensions will not be detected at boot and their presence not reported to userspace. =20 + If you don't know what to do here, say Y. + +config RISCV_ISA_XTHEADVECTOR + bool "xtheadvector extension support" + depends on RISCV_ISA_VENDOR_EXT_THEAD + depends on RISCV_ISA_V + depends on FPU + default y + help + Say N here if you want to disable all xtheadvector related procedures + in the kernel. This will disable vector for any T-Head board that + contains xtheadvector rather than the standard vector. + If you don't know what to do here, say Y. endmenu =20 diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index b029ca72cebc..e0a3164c7a06 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 +extern u32 thead_vlenb_of; + void riscv_user_isa_enable(void); =20 #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) {= \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 2107c59575dd..077be4ab1f9a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __rea= d_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 +u32 thead_vlenb_of; + /** * riscv_isa_extension_base() - Get base extension word * @@ -625,6 +627,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu) } } =20 +static int has_thead_homogeneous_vlenb(void) +{ + int cpu; + u32 prev_vlenb =3D 0; + u32 vlenb; + + /* Ignore thead,vlenb property if xtheavector is not enabled in the kerne= l */ + if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return 0; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node; + + cpu_node =3D of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + return -ENOENT; + } + + if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { + of_node_put(cpu_node); + + if (prev_vlenb) + return -ENOENT; + continue; + } + + if (prev_vlenb && vlenb !=3D prev_vlenb) { + of_node_put(cpu_node); + return -ENOENT; + } + + prev_vlenb =3D vlenb; + of_node_put(cpu_node); + } + + thead_vlenb_of =3D vlenb; + return 0; +} + static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) { unsigned int cpu; @@ -689,6 +731,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); } =20 + if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) && + has_thead_homogeneous_vlenb() < 0) { + pr_warn("Unsupported heterogeneous vlenb detected, vector extension disa= bled.\n"); + elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; + } + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) return -ENOENT; =20 diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 6727d1d3b8f2..3ba2f2432483 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) { unsigned long this_vsize; =20 - /* There are 32 vector registers with vlenb length. */ + /* + * There are 32 vector registers with vlenb length. + * + * If the thead,vlenb property was provided by the firmware, use that + * instead of probing the CSRs. + */ + if (thead_vlenb_of) { + this_vsize =3D thead_vlenb_of * 32; + return 0; + } + riscv_v_enable(); this_vsize =3D csr_read(CSR_VLENB) * 32; riscv_v_disable(); --=20 2.44.0