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[83.30.46.83]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ebd5a63bf2sm6679841fa.33.2024.06.09.11.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 11:21:29 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: interconnect: Add Qualcomm MSM8976 DT bindings Date: Sun, 9 Jun 2024 20:20:54 +0200 Message-Id: <20240609182112.13032-2-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240609182112.13032-1-a39.skl@gmail.com> References: <20240609182112.13032-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for Qualcomm MSM8976 Network-On-Chip interconnect devices. Signed-off-by: Adam Skladowski --- .../bindings/interconnect/qcom,msm8976.yaml | 107 ++++++++++++++++++ .../dt-bindings/interconnect/qcom,msm8976.h | 97 ++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm= 8976.yaml create mode 100644 include/dt-bindings/interconnect/qcom,msm8976.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8976.ya= ml b/Documentation/devicetree/bindings/interconnect/qcom,msm8976.yaml new file mode 100644 index 000000000000..bc9d08443e7c --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8976.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8976.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8976 Network-On-Chip interconnect + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm MSM8976 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,msm8976-bimc + - qcom,msm8976-pcnoc + - qcom,msm8976-snoc + + reg: + maxItems: 1 + + clock-names: + minItems: 1 + maxItems: 2 + + clocks: + minItems: 1 + maxItems: 2 + +patternProperties: + '^interconnect-[a-z0-9\-]+$': + type: object + $ref: qcom,rpm-common.yaml# + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + allOf: + - $ref: qcom,rpm-common.yaml# + + properties: + compatible: + const: qcom,msm8976-snoc-mm + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,msm8976-snoc + + then: + properties: + clocks: + items: + - description: IPA clock from RPMCC + clock-names: + const: ipa + + required: + - clocks + - clock-names + +examples: + - | + #include + #include + + bimc: interconnect@400000 { + compatible =3D "qcom,msm8976-bimc"; + reg =3D <0x00400000 0x62000>; + #interconnect-cells =3D <2>; + }; + + pcnoc: interconnect@500000 { + compatible =3D "qcom,msm8976-pcnoc"; + reg =3D <0x00500000 0x14000>; + #interconnect-cells =3D <2>; + }; + + snoc: interconnect@580000 { + compatible =3D "qcom,msm8976-snoc"; + reg =3D <0x00580000 0x1a000>; + clocks =3D <&rpmcc RPM_SMD_IPA_CLK>; + clock-names =3D "ipa"; + #interconnect-cells =3D <2>; + + snoc_mm: interconnect-snoc { + compatible =3D "qcom,msm8976-snoc-mm"; + #interconnect-cells =3D <2>; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,msm8976.h b/include/dt-b= indings/interconnect/qcom,msm8976.h new file mode 100644 index 000000000000..4ea90f22320e --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8976.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm MSM8976 interconnect IDs + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H + +/* BIMC fabric */ +#define MAS_APPS_PROC 0 +#define MAS_SMMNOC_BIMC 1 +#define MAS_SNOC_BIMC 2 +#define MAS_TCU_0 3 +#define SLV_EBI 4 +#define SLV_BIMC_SNOC 5 + +/* PCNOC fabric */ +#define MAS_USB_HS2 0 +#define MAS_BLSP_1 1 +#define MAS_USB_HS1 2 +#define MAS_BLSP_2 3 +#define MAS_CRYPTO 4 +#define MAS_SDCC_1 5 +#define MAS_SDCC_2 6 +#define MAS_SDCC_3 7 +#define MAS_SNOC_PCNOC 8 +#define MAS_LPASS_AHB 9 +#define MAS_SPDM 10 +#define MAS_DEHR 11 +#define MAS_XM_USB_HS1 12 +#define PCNOC_M_0 13 +#define PCNOC_M_1 14 +#define PCNOC_INT_0 15 +#define PCNOC_INT_1 16 +#define PCNOC_INT_2 17 +#define PCNOC_S_1 18 +#define PCNOC_S_2 19 +#define PCNOC_S_3 20 +#define PCNOC_S_4 21 +#define PCNOC_S_8 22 +#define PCNOC_S_9 23 +#define SLV_TCSR 24 +#define SLV_TLMM 25 +#define SLV_CRYPTO_0_CFG 26 +#define SLV_MESSAGE_RAM 27 +#define SLV_PDM 28 +#define SLV_PRNG 29 +#define SLV_PMIC_ARB 30 +#define SLV_SNOC_CFG 31 +#define SLV_DCC_CFG 32 +#define SLV_CAMERA_SS_CFG 33 +#define SLV_DISP_SS_CFG 34 +#define SLV_VENUS_CFG 35 +#define SLV_SDCC_1 36 +#define SLV_BLSP_1 37 +#define SLV_USB_HS 38 +#define SLV_SDCC_3 39 +#define SLV_SDCC_2 40 +#define SLV_GPU_CFG 41 +#define SLV_USB_HS2 42 +#define SLV_BLSP_2 43 +#define SLV_PCNOC_SNOC 44 + +/* SNOC fabric */ +#define MAS_QDSS_BAM 0 +#define MAS_BIMC_SNOC 1 +#define MAS_PCNOC_SNOC 2 +#define MAS_QDSS_ETR 3 +#define MAS_LPASS_PROC 4 +#define MAS_IPA 5 +#define QDSS_INT 6 +#define SNOC_INT_0 7 +#define SNOC_INT_1 8 +#define SNOC_INT_2 9 +#define SLV_KPSS_AHB 10 +#define SLV_SNOC_BIMC 11 +#define SLV_IMEM 12 +#define SLV_SNOC_PCNOC 13 +#define SLV_QDSS_STM 14 +#define SLV_CATS_0 15 +#define SLV_CATS_1 16 +#define SLV_LPASS 17 + +/* SNOC-MM fabric */ +#define MAS_JPEG 0 +#define MAS_OXILI 1 +#define MAS_MDP0 2 +#define MAS_MDP1 3 +#define MAS_VENUS_0 4 +#define MAS_VENUS_1 5 +#define MAS_VFE_0 6 +#define MAS_VFE_1 7 +#define MAS_CPP 8 +#define MM_INT_0 9 +#define SLV_SMMNOC_BIMC 10 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8976_H */ --=20 2.45.1 From nobody Thu Feb 12 17:27:58 2026 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBF4C4E1DD; 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[83.30.46.83]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ebd5a63bf2sm6679841fa.33.2024.06.09.11.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 11:21:33 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] interconnect: qcom: Add MSM8976 interconnect provider driver Date: Sun, 9 Jun 2024 20:20:55 +0200 Message-Id: <20240609182112.13032-3-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240609182112.13032-1-a39.skl@gmail.com> References: <20240609182112.13032-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver for interconnect busses found in MSM8976 based platforms. The topology consists of four NoCs that are partially controlled by a RPM processor. Signed-off-by: Adam Skladowski --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/msm8976.c | 1443 +++++++++++++++++++++++++++ 3 files changed, 1454 insertions(+) create mode 100644 drivers/interconnect/qcom/msm8976.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 1446a839184e..a0e9c09954ed 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -44,6 +44,15 @@ config INTERCONNECT_QCOM_MSM8974 This is a driver for the Qualcomm Network-on-Chip on msm8974-based platforms. =20 +config INTERCONNECT_QCOM_MSM8976 + tristate "Qualcomm MSM8976 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8976-based + platforms. + config INTERCONNECT_QCOM_MSM8996 tristate "Qualcomm MSM8996 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 2ea3113d0a4d..21ce45438258 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -8,6 +8,7 @@ qnoc-msm8909-objs :=3D msm8909.o qnoc-msm8916-objs :=3D msm8916.o qnoc-msm8939-objs :=3D msm8939.o qnoc-msm8974-objs :=3D msm8974.o +qnoc-msm8976-objs :=3D msm8976.o qnoc-msm8996-objs :=3D msm8996.o icc-osm-l3-objs :=3D osm-l3.o qnoc-qcm2290-objs :=3D qcm2290.o @@ -42,6 +43,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909= .o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) +=3D qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) +=3D qnoc-msm8939.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) +=3D qnoc-msm8974.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) +=3D qnoc-msm8976.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) +=3D qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) +=3D icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) +=3D qnoc-qcm2290.o diff --git a/drivers/interconnect/qcom/msm8976.c b/drivers/interconnect/qco= m/msm8976.c new file mode 100644 index 000000000000..b6cefdf0fecb --- /dev/null +++ b/drivers/interconnect/qcom/msm8976.c @@ -0,0 +1,1443 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on data from msm8976-bus.dtsi in Qualcomm's msm-3.10 release: + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + + +#include +#include +#include +#include +#include +#include + + +#include + +#include "icc-rpm.h" + +static const char * const snoc_intf_clocks[] =3D { + "ipa", /* mas_ipa */ +}; + +enum { + QNOC_MASTER_AMPSS_M0 =3D 1, + QNOC_MNOC_BIMC_MAS, + QNOC_SNOC_BIMC_MAS, + QNOC_MASTER_TCU_0, + QNOC_MASTER_USB_HS2, + QNOC_MASTER_BLSP_1, + QNOC_MASTER_USB_HS, + QNOC_MASTER_BLSP_2, + QNOC_MASTER_CRYPTO_CORE0, + QNOC_MASTER_SDCC_1, + QNOC_MASTER_SDCC_2, + QNOC_MASTER_SDCC_3, + QNOC_SNOC_PNOC_MAS, + QNOC_MASTER_LPASS_AHB, + QNOC_MASTER_SPDM, + QNOC_MASTER_DEHR, + QNOC_MASTER_XM_USB_HS1, + QNOC_MASTER_QDSS_BAM, + QNOC_BIMC_SNOC_MAS, + QNOC_MASTER_JPEG, + QNOC_MASTER_GRAPHICS_3D, + QNOC_MASTER_MDP_PORT0, + QNOC_MASTER_MDP_PORT1, + QNOC_PNOC_SNOC_MAS, + QNOC_MASTER_VIDEO_P0, + QNOC_MASTER_VIDEO_P1, + QNOC_MASTER_VFE0, + QNOC_MASTER_VFE1, + QNOC_MASTER_CPP, + QNOC_MASTER_QDSS_ETR, + QNOC_MASTER_LPASS_PROC, + QNOC_MASTER_IPA, + QNOC_PNOC_M_0, + QNOC_PNOC_M_1, + QNOC_PNOC_INT_0, + QNOC_PNOC_INT_1, + QNOC_PNOC_INT_2, + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_3, + QNOC_PNOC_SLV_4, + QNOC_PNOC_SLV_8, + QNOC_PNOC_SLV_9, + QNOC_SNOC_MM_INT_0, + QNOC_SNOC_QDSS_INT, + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_INT_2, + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_TCSR, + QNOC_SLAVE_TLMM, + QNOC_SLAVE_CRYPTO_0_CFG, + QNOC_SLAVE_MESSAGE_RAM, + QNOC_SLAVE_PDM, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_PMIC_ARB, + QNOC_SLAVE_SNOC_CFG, + QNOC_SLAVE_DCC_CFG, + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG, + QNOC_SLAVE_SDCC_1, + QNOC_SLAVE_BLSP_1, + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_SDCC_3, + QNOC_SLAVE_SDCC_2, + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_USB_HS2, + QNOC_SLAVE_BLSP_2, + QNOC_PNOC_SNOC_SLV, + QNOC_SLAVE_APPSS, + QNOC_MNOC_BIMC_SLV, + QNOC_SNOC_BIMC_SLV, + QNOC_SLAVE_SYSTEM_IMEM, + QNOC_SNOC_PNOC_SLV, + QNOC_SLAVE_QDSS_STM, + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_OCMEM_64, + QNOC_SLAVE_LPASS, +}; + +static const u16 mas_apps_proc_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_apps_proc =3D { + .name =3D "mas_apps_proc", + .id =3D QNOC_MASTER_AMPSS_M0, + .buswidth =3D 16, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_apps_proc_links), + .links =3D mas_apps_proc_links, +}; + +static const u16 mas_smmnoc_bimc_links[] =3D { + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_smmnoc_bimc =3D { + .name =3D "mas_smmnoc_bimc", + .id =3D QNOC_MNOC_BIMC_MAS, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D 135, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 2, + .num_links =3D ARRAY_SIZE(mas_smmnoc_bimc_links), + .links =3D mas_smmnoc_bimc_links, +}; + +static const u16 mas_snoc_bimc_links[] =3D { + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_snoc_bimc =3D { + .name =3D "mas_snoc_bimc", + .id =3D QNOC_SNOC_BIMC_MAS, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D 3, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 3, + .num_links =3D ARRAY_SIZE(mas_snoc_bimc_links), + .links =3D mas_snoc_bimc_links, +}; + +static const u16 mas_tcu_0_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_tcu_0 =3D { + .name =3D "mas_tcu_0", + .id =3D QNOC_MASTER_TCU_0, + .buswidth =3D 16, + .mas_rpm_id =3D 102, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 2, + .qos.qos_port =3D 4, + .num_links =3D ARRAY_SIZE(mas_tcu_0_links), + .links =3D mas_tcu_0_links, +}; + +static const u16 mas_usb_hs2_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_usb_hs2 =3D { + .name =3D "mas_usb_hs2", + .id =3D QNOC_MASTER_USB_HS2, + .buswidth =3D 4, + .mas_rpm_id =3D 57, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb_hs2_links), + .links =3D mas_usb_hs2_links, +}; + +static const u16 mas_blsp_1_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_blsp_1 =3D { + .name =3D "mas_blsp_1", + .id =3D QNOC_MASTER_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D 41, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_1_links), + .links =3D mas_blsp_1_links, +}; + +static const u16 mas_usb_hs1_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_usb_hs1 =3D { + .name =3D "mas_usb_hs1", + .id =3D QNOC_MASTER_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D 42, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb_hs1_links), + .links =3D mas_usb_hs1_links, +}; + +static const u16 mas_blsp_2_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_blsp_2 =3D { + .name =3D "mas_blsp_2", + .id =3D QNOC_MASTER_BLSP_2, + .buswidth =3D 4, + .mas_rpm_id =3D 39, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_2_links), + .links =3D mas_blsp_2_links, +}; + +static const u16 mas_crypto_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_crypto =3D { + .name =3D "mas_crypto", + .id =3D QNOC_MASTER_CRYPTO_CORE0, + .buswidth =3D 8, + .mas_rpm_id =3D 23, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_crypto_links), + .links =3D mas_crypto_links, +}; + +static const u16 mas_sdcc_1_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_1 =3D { + .name =3D "mas_sdcc_1", + .id =3D QNOC_MASTER_SDCC_1, + .buswidth =3D 8, + .mas_rpm_id =3D 33, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_sdcc_1_links), + .links =3D mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_2_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_2 =3D { + .name =3D "mas_sdcc_2", + .id =3D QNOC_MASTER_SDCC_2, + .buswidth =3D 8, + .mas_rpm_id =3D 35, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_sdcc_2_links), + .links =3D mas_sdcc_2_links, +}; + +static const u16 mas_sdcc_3_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_3 =3D { + .name =3D "mas_sdcc_3", + .id =3D QNOC_MASTER_SDCC_3, + .buswidth =3D 8, + .mas_rpm_id =3D 34, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 10, + .num_links =3D ARRAY_SIZE(mas_sdcc_3_links), + .links =3D mas_sdcc_3_links, +}; + +static const u16 mas_snoc_pcnoc_links[] =3D { + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node mas_snoc_pcnoc =3D { + .name =3D "mas_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 77, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_snoc_pcnoc_links), + .links =3D mas_snoc_pcnoc_links, +}; + +static const u16 mas_lpass_ahb_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node mas_lpass_ahb =3D { + .name =3D "mas_lpass_ahb", + .id =3D QNOC_MASTER_LPASS_AHB, + .buswidth =3D 8, + .mas_rpm_id =3D 18, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 12, + .num_links =3D ARRAY_SIZE(mas_lpass_ahb_links), + .links =3D mas_lpass_ahb_links, +}; + +static const u16 mas_spdm_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_spdm =3D { + .name =3D "mas_spdm", + .id =3D QNOC_MASTER_SPDM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_spdm_links), + .links =3D mas_spdm_links, +}; + +static const u16 mas_dehr_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_dehr =3D { + .name =3D "mas_dehr", + .id =3D QNOC_MASTER_DEHR, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_dehr_links), + .links =3D mas_dehr_links, +}; + +static const u16 mas_xm_usb_hs1_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_xm_usb_hs1 =3D { + .name =3D "mas_xm_usb_hs1", + .id =3D QNOC_MASTER_XM_USB_HS1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_xm_usb_hs1_links), + .links =3D mas_xm_usb_hs1_links, +}; + +static const u16 mas_qdss_bam_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_bam =3D { + .name =3D "mas_qdss_bam", + .id =3D QNOC_MASTER_QDSS_BAM, + .buswidth =3D 4, + .mas_rpm_id =3D 19, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 11, + .num_links =3D ARRAY_SIZE(mas_qdss_bam_links), + .links =3D mas_qdss_bam_links, +}; + +static const u16 mas_bimc_snoc_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node mas_bimc_snoc =3D { + .name =3D "mas_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 21, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_bimc_snoc_links), + .links =3D mas_bimc_snoc_links, +}; + +static const u16 mas_jpeg_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_jpeg =3D { + .name =3D "mas_jpeg", + .id =3D QNOC_MASTER_JPEG, + .buswidth =3D 16, + .mas_rpm_id =3D 7, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(mas_jpeg_links), + .links =3D mas_jpeg_links, +}; + +static const u16 mas_oxili_links[] =3D { + QNOC_MNOC_BIMC_SLV, + QNOC_SNOC_MM_INT_0 +}; + +static struct qcom_icc_node mas_oxili =3D { + .name =3D "mas_oxili", + .id =3D QNOC_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D 6, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 16, /* [16, 17] */ + .num_links =3D ARRAY_SIZE(mas_oxili_links), + .links =3D mas_oxili_links, +}; + +static const u16 mas_mdp0_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_mdp0 =3D { + .name =3D "mas_mdp0", + .id =3D QNOC_MASTER_MDP_PORT0, + .buswidth =3D 16, + .mas_rpm_id =3D 8, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_mdp0_links), + .links =3D mas_mdp0_links, +}; + +static const u16 mas_mdp1_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_mdp1 =3D { + .name =3D "mas_mdp1", + .id =3D QNOC_MASTER_MDP_PORT1, + .buswidth =3D 16, + .mas_rpm_id =3D 61, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 13, + .num_links =3D ARRAY_SIZE(mas_mdp1_links), + .links =3D mas_mdp1_links, +}; + +static const u16 mas_pcnoc_snoc_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node mas_pcnoc_snoc =3D { + .name =3D "mas_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 29, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(mas_pcnoc_snoc_links), + .links =3D mas_pcnoc_snoc_links, +}; + +static const u16 mas_venus_0_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_venus_0 =3D { + .name =3D "mas_venus_0", + .id =3D QNOC_MASTER_VIDEO_P0, + .buswidth =3D 16, + .mas_rpm_id =3D 9, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_venus_0_links), + .links =3D mas_venus_0_links, +}; + +static const u16 mas_venus_1_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_venus_1 =3D { + .name =3D "mas_venus_1", + .id =3D QNOC_MASTER_VIDEO_P1, + .buswidth =3D 16, + .mas_rpm_id =3D 10, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 14, + .num_links =3D ARRAY_SIZE(mas_venus_1_links), + .links =3D mas_venus_1_links, +}; + +static const u16 mas_vfe_0_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_vfe_0 =3D { + .name =3D "mas_vfe_0", + .id =3D QNOC_MASTER_VFE0, + .buswidth =3D 16, + .mas_rpm_id =3D 11, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_vfe_0_links), + .links =3D mas_vfe_0_links, +}; + +static const u16 mas_vfe_1_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_vfe_1 =3D { + .name =3D "mas_vfe_1", + .id =3D QNOC_MASTER_VFE1, + .buswidth =3D 16, + .mas_rpm_id =3D 133, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 15, + .num_links =3D ARRAY_SIZE(mas_vfe_1_links), + .links =3D mas_vfe_1_links, +}; + +static const u16 mas_cpp_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_cpp =3D { + .name =3D "mas_cpp", + .id =3D QNOC_MASTER_CPP, + .buswidth =3D 16, + .mas_rpm_id =3D 115, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 12, + .num_links =3D ARRAY_SIZE(mas_cpp_links), + .links =3D mas_cpp_links, +}; + +static const u16 mas_qdss_etr_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_etr =3D { + .name =3D "mas_qdss_etr", + .id =3D QNOC_MASTER_QDSS_ETR, + .buswidth =3D 8, + .mas_rpm_id =3D 31, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 10, + .num_links =3D ARRAY_SIZE(mas_qdss_etr_links), + .links =3D mas_qdss_etr_links, +}; + +static const u16 mas_lpass_proc_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_lpass_proc =3D { + .name =3D "mas_lpass_proc", + .id =3D QNOC_MASTER_LPASS_PROC, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 19, + .num_links =3D ARRAY_SIZE(mas_lpass_proc_links), + .links =3D mas_lpass_proc_links, +}; + +static const u16 mas_ipa_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node mas_ipa =3D { + .name =3D "mas_ipa", + .id =3D QNOC_MASTER_IPA, + .buswidth =3D 8, + .mas_rpm_id =3D 59, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 18, + .num_links =3D ARRAY_SIZE(mas_ipa_links), + .links =3D mas_ipa_links, +}; + +static const u16 pcnoc_m_0_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_m_0 =3D { + .name =3D "pcnoc_m_0", + .id =3D QNOC_PNOC_M_0, + .buswidth =3D 4, + .mas_rpm_id =3D 87, + .slv_rpm_id =3D 116, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(pcnoc_m_0_links), + .links =3D pcnoc_m_0_links, +}; + +static const u16 pcnoc_m_1_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_m_1 =3D { + .name =3D "pcnoc_m_1", + .id =3D QNOC_PNOC_M_1, + .buswidth =3D 4, + .mas_rpm_id =3D 88, + .slv_rpm_id =3D 117, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(pcnoc_m_1_links), + .links =3D pcnoc_m_1_links, +}; + +static const u16 pcnoc_int_0_links[] =3D { + QNOC_PNOC_SNOC_SLV, + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node pcnoc_int_0 =3D { + .name =3D "pcnoc_int_0", + .id =3D QNOC_PNOC_INT_0, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(pcnoc_int_0_links), + .links =3D pcnoc_int_0_links, +}; + +static const u16 pcnoc_int_1_links[] =3D { + QNOC_PNOC_SNOC_SLV, + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node pcnoc_int_1 =3D { + .name =3D "pcnoc_int_1", + .id =3D QNOC_PNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D 86, + .slv_rpm_id =3D 115, + .num_links =3D ARRAY_SIZE(pcnoc_int_1_links), + .links =3D pcnoc_int_1_links, +}; + +static const u16 pcnoc_int_2_links[] =3D { + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_4, + QNOC_PNOC_SLV_8, + QNOC_PNOC_SLV_9, + QNOC_PNOC_SLV_3 +}; + +static struct qcom_icc_node pcnoc_int_2 =3D { + .name =3D "pcnoc_int_2", + .id =3D QNOC_PNOC_INT_2, + .buswidth =3D 8, + .mas_rpm_id =3D 124, + .slv_rpm_id =3D 184, + .num_links =3D ARRAY_SIZE(pcnoc_int_2_links), + .links =3D pcnoc_int_2_links, +}; + +static const u16 pcnoc_s_1_links[] =3D { + QNOC_SLAVE_CRYPTO_0_CFG, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_PDM, + QNOC_SLAVE_MESSAGE_RAM +}; + +static struct qcom_icc_node pcnoc_s_1 =3D { + .name =3D "pcnoc_s_1", + .id =3D QNOC_PNOC_SLV_1, + .buswidth =3D 4, + .mas_rpm_id =3D 90, + .slv_rpm_id =3D 119, + .num_links =3D ARRAY_SIZE(pcnoc_s_1_links), + .links =3D pcnoc_s_1_links, +}; + +static const u16 pcnoc_s_2_links[] =3D { + QNOC_SLAVE_PMIC_ARB +}; + +static struct qcom_icc_node pcnoc_s_2 =3D { + .name =3D "pcnoc_s_2", + .id =3D QNOC_PNOC_SLV_2, + .buswidth =3D 4, + .mas_rpm_id =3D 91, + .slv_rpm_id =3D 120, + .num_links =3D ARRAY_SIZE(pcnoc_s_2_links), + .links =3D pcnoc_s_2_links, +}; + +static const u16 pcnoc_s_3_links[] =3D { + QNOC_SLAVE_SNOC_CFG, + QNOC_SLAVE_DCC_CFG +}; + +static struct qcom_icc_node pcnoc_s_3 =3D { + .name =3D "pcnoc_s_3", + .id =3D QNOC_PNOC_SLV_3, + .buswidth =3D 4, + .mas_rpm_id =3D 92, + .slv_rpm_id =3D 121, + .num_links =3D ARRAY_SIZE(pcnoc_s_3_links), + .links =3D pcnoc_s_3_links, +}; + +static const u16 pcnoc_s_4_links[] =3D { + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG +}; + +static struct qcom_icc_node pcnoc_s_4 =3D { + .name =3D "pcnoc_s_4", + .id =3D QNOC_PNOC_SLV_4, + .buswidth =3D 4, + .mas_rpm_id =3D 93, + .slv_rpm_id =3D 122, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(pcnoc_s_4_links), + .links =3D pcnoc_s_4_links, +}; + +static const u16 pcnoc_s_8_links[] =3D { + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_SDCC_3, + QNOC_SLAVE_BLSP_1, + QNOC_SLAVE_SDCC_1 +}; + +static struct qcom_icc_node pcnoc_s_8 =3D { + .name =3D "pcnoc_s_8", + .id =3D QNOC_PNOC_SLV_8, + .buswidth =3D 4, + .mas_rpm_id =3D 96, + .slv_rpm_id =3D 125, + .num_links =3D ARRAY_SIZE(pcnoc_s_8_links), + .links =3D pcnoc_s_8_links, +}; + +static const u16 pcnoc_s_9_links[] =3D { + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_USB_HS2, + QNOC_SLAVE_SDCC_2, + QNOC_SLAVE_BLSP_2 +}; + +static struct qcom_icc_node pcnoc_s_9 =3D { + .name =3D "pcnoc_s_9", + .id =3D QNOC_PNOC_SLV_9, + .buswidth =3D 4, + .mas_rpm_id =3D 97, + .slv_rpm_id =3D 126, + .num_links =3D ARRAY_SIZE(pcnoc_s_9_links), + .links =3D pcnoc_s_9_links, +}; + +static const u16 mm_int_0_links[] =3D { + QNOC_SNOC_INT_0 +}; + +static struct qcom_icc_node mm_int_0 =3D { + .name =3D "mm_int_0", + .id =3D QNOC_SNOC_MM_INT_0, + .buswidth =3D 16, + .mas_rpm_id =3D 79, + .slv_rpm_id =3D 108, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(mm_int_0_links), + .links =3D mm_int_0_links, +}; + +static const u16 qdss_int_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node qdss_int =3D { + .name =3D "qdss_int", + .id =3D QNOC_SNOC_QDSS_INT, + .buswidth =3D 8, + .mas_rpm_id =3D 98, + .slv_rpm_id =3D 128, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(qdss_int_links), + .links =3D qdss_int_links, +}; + +static const u16 snoc_int_0_links[] =3D { + QNOC_SLAVE_QDSS_STM, + QNOC_SLAVE_SYSTEM_IMEM, + QNOC_SNOC_PNOC_SLV +}; + +static struct qcom_icc_node snoc_int_0 =3D { + .name =3D "snoc_int_0", + .id =3D QNOC_SNOC_INT_0, + .buswidth =3D 8, + .mas_rpm_id =3D 99, + .slv_rpm_id =3D 130, + .num_links =3D ARRAY_SIZE(snoc_int_0_links), + .links =3D snoc_int_0_links, +}; + +static const u16 snoc_int_1_links[] =3D { + QNOC_SLAVE_LPASS, + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_OCMEM_64, + QNOC_SLAVE_APPSS +}; + +static struct qcom_icc_node snoc_int_1 =3D { + .name =3D "snoc_int_1", + .id =3D QNOC_SNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D 100, + .slv_rpm_id =3D 131, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(snoc_int_1_links), + .links =3D snoc_int_1_links, +}; + +static const u16 snoc_int_2_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_BIMC_SLV +}; + +static struct qcom_icc_node snoc_int_2 =3D { + .name =3D "snoc_int_2", + .id =3D QNOC_SNOC_INT_2, + .buswidth =3D 8, + .mas_rpm_id =3D 134, + .slv_rpm_id =3D 197, + .num_links =3D ARRAY_SIZE(snoc_int_2_links), + .links =3D snoc_int_2_links, +}; + +static struct qcom_icc_node slv_ebi =3D { + .name =3D "slv_ebi", + .id =3D QNOC_SLAVE_EBI_CH0, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 0, +}; + +static const u16 slv_bimc_snoc_links[] =3D { + QNOC_BIMC_SNOC_MAS +}; + +static struct qcom_icc_node slv_bimc_snoc =3D { + .name =3D "slv_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_SLV, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 2, + .num_links =3D ARRAY_SIZE(slv_bimc_snoc_links), + .links =3D slv_bimc_snoc_links, +}; + +static struct qcom_icc_node slv_tcsr =3D { + .name =3D "slv_tcsr", + .id =3D QNOC_SLAVE_TCSR, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 50, +}; + +static struct qcom_icc_node slv_tlmm =3D { + .name =3D "slv_tlmm", + .id =3D QNOC_SLAVE_TLMM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 51, +}; + +static struct qcom_icc_node slv_crypto_0_cfg =3D { + .name =3D "slv_crypto_0_cfg", + .id =3D QNOC_SLAVE_CRYPTO_0_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 52, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_message_ram =3D { + .name =3D "slv_message_ram", + .id =3D QNOC_SLAVE_MESSAGE_RAM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 55, +}; + +static struct qcom_icc_node slv_pdm =3D { + .name =3D "slv_pdm", + .id =3D QNOC_SLAVE_PDM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 41, +}; + +static struct qcom_icc_node slv_prng =3D { + .name =3D "slv_prng", + .id =3D QNOC_SLAVE_PRNG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 44, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_pmic_arb =3D { + .name =3D "slv_pmic_arb", + .id =3D QNOC_SLAVE_PMIC_ARB, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 59, +}; + +static struct qcom_icc_node slv_snoc_cfg =3D { + .name =3D "slv_snoc_cfg", + .id =3D QNOC_SLAVE_SNOC_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 70, +}; + +static struct qcom_icc_node slv_dcc_cfg =3D { + .name =3D "slv_dcc_cfg", + .id =3D QNOC_SLAVE_DCC_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 155, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_camera_ss_cfg =3D { + .name =3D "slv_camera_ss_cfg", + .id =3D QNOC_SLAVE_CAMERA_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 3, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_disp_ss_cfg =3D { + .name =3D "slv_disp_ss_cfg", + .id =3D QNOC_SLAVE_DISPLAY_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 4, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_venus_cfg =3D { + .name =3D "slv_venus_cfg", + .id =3D QNOC_SLAVE_VENUS_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 10, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_sdcc_1 =3D { + .name =3D "slv_sdcc_1", + .id =3D QNOC_SLAVE_SDCC_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 31, +}; + +static struct qcom_icc_node slv_blsp_1 =3D { + .name =3D "slv_blsp_1", + .id =3D QNOC_SLAVE_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 39, +}; + +static struct qcom_icc_node slv_usb_hs =3D { + .name =3D "slv_usb_hs", + .id =3D QNOC_SLAVE_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 40, +}; + +static struct qcom_icc_node slv_sdcc_3 =3D { + .name =3D "slv_sdcc_3", + .id =3D QNOC_SLAVE_SDCC_3, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 32, +}; + +static struct qcom_icc_node slv_sdcc_2 =3D { + .name =3D "slv_sdcc_2", + .id =3D QNOC_SLAVE_SDCC_2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 33, +}; + +static struct qcom_icc_node slv_gpu_cfg =3D { + .name =3D "slv_gpu_cfg", + .id =3D QNOC_SLAVE_GRAPHICS_3D_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 11, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_usb_hs2 =3D { + .name =3D "slv_usb_hs2", + .id =3D QNOC_SLAVE_USB_HS2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 79, +}; + +static struct qcom_icc_node slv_blsp_2 =3D { + .name =3D "slv_blsp_2", + .id =3D QNOC_SLAVE_BLSP_2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 37, +}; + +static const u16 slv_pcnoc_snoc_links[] =3D { + QNOC_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node slv_pcnoc_snoc =3D { + .name =3D "slv_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 45, + .num_links =3D ARRAY_SIZE(slv_pcnoc_snoc_links), + .links =3D slv_pcnoc_snoc_links, +}; + +static struct qcom_icc_node slv_kpss_ahb =3D { + .name =3D "slv_kpss_ahb", + .id =3D QNOC_SLAVE_APPSS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 20, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static const u16 slv_smmnoc_bimc_links[] =3D { + QNOC_MNOC_BIMC_MAS +}; + +static struct qcom_icc_node slv_smmnoc_bimc =3D { + .name =3D "slv_smmnoc_bimc", + .id =3D QNOC_MNOC_BIMC_SLV, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 198, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(slv_smmnoc_bimc_links), + .links =3D slv_smmnoc_bimc_links, +}; + +static const u16 slv_snoc_bimc_links[] =3D { + QNOC_SNOC_BIMC_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc =3D { + .name =3D "slv_snoc_bimc", + .id =3D QNOC_SNOC_BIMC_SLV, + .channels =3D 2, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 24, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_links), + .links =3D slv_snoc_bimc_links, +}; + +static struct qcom_icc_node slv_imem =3D { + .name =3D "slv_imem", + .id =3D QNOC_SLAVE_SYSTEM_IMEM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 26, +}; + +static const u16 slv_snoc_pcnoc_links[] =3D { + QNOC_SNOC_PNOC_MAS +}; + +static struct qcom_icc_node slv_snoc_pcnoc =3D { + .name =3D "slv_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 28, + .num_links =3D ARRAY_SIZE(slv_snoc_pcnoc_links), + .links =3D slv_snoc_pcnoc_links, +}; + +static struct qcom_icc_node slv_qdss_stm =3D { + .name =3D "slv_qdss_stm", + .id =3D QNOC_SLAVE_QDSS_STM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 30, +}; + +static struct qcom_icc_node slv_cats_0 =3D { + .name =3D "slv_cats_0", + .id =3D QNOC_SLAVE_CATS_128, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 106, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_cats_1 =3D { + .name =3D "slv_cats_1", + .id =3D QNOC_SLAVE_OCMEM_64, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 107, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_lpass =3D { + .name =3D "slv_lpass", + .id =3D QNOC_SLAVE_LPASS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 21, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node * const msm8976_bimc_nodes[] =3D { + [MAS_APPS_PROC] =3D &mas_apps_proc, + [MAS_SMMNOC_BIMC] =3D &mas_smmnoc_bimc, + [MAS_SNOC_BIMC] =3D &mas_snoc_bimc, + [MAS_TCU_0] =3D &mas_tcu_0, + [SLV_EBI] =3D &slv_ebi, + [SLV_BIMC_SNOC] =3D &slv_bimc_snoc, +}; + +static const struct regmap_config msm8976_bimc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x62000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8976_bimc =3D { + .type =3D QCOM_ICC_BIMC, + .nodes =3D msm8976_bimc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_bimc_nodes), + .bus_clk_desc =3D &bimc_clk, + .regmap_cfg =3D &msm8976_bimc_regmap_config, + .qos_offset =3D 0x8000, + .ab_coeff =3D 154, +}; + +static struct qcom_icc_node * const msm8976_pcnoc_nodes[] =3D { + [MAS_USB_HS2] =3D &mas_usb_hs2, + [MAS_BLSP_1] =3D &mas_blsp_1, + [MAS_USB_HS1] =3D &mas_usb_hs1, + [MAS_BLSP_2] =3D &mas_blsp_2, + [MAS_CRYPTO] =3D &mas_crypto, + [MAS_SDCC_1] =3D &mas_sdcc_1, + [MAS_SDCC_2] =3D &mas_sdcc_2, + [MAS_SDCC_3] =3D &mas_sdcc_3, + [MAS_SNOC_PCNOC] =3D &mas_snoc_pcnoc, + [MAS_LPASS_AHB] =3D &mas_lpass_ahb, + [MAS_SPDM] =3D &mas_spdm, + [MAS_DEHR] =3D &mas_dehr, + [MAS_XM_USB_HS1] =3D &mas_xm_usb_hs1, + [PCNOC_M_0] =3D &pcnoc_m_0, + [PCNOC_M_1] =3D &pcnoc_m_1, + [PCNOC_INT_0] =3D &pcnoc_int_0, + [PCNOC_INT_1] =3D &pcnoc_int_1, + [PCNOC_INT_2] =3D &pcnoc_int_2, + [PCNOC_S_1] =3D &pcnoc_s_1, + [PCNOC_S_2] =3D &pcnoc_s_2, + [PCNOC_S_3] =3D &pcnoc_s_3, + [PCNOC_S_4] =3D &pcnoc_s_4, + [PCNOC_S_8] =3D &pcnoc_s_8, + [PCNOC_S_9] =3D &pcnoc_s_9, + [SLV_TCSR] =3D &slv_tcsr, + [SLV_TLMM] =3D &slv_tlmm, + [SLV_CRYPTO_0_CFG] =3D &slv_crypto_0_cfg, + [SLV_MESSAGE_RAM] =3D &slv_message_ram, + [SLV_PDM] =3D &slv_pdm, + [SLV_PRNG] =3D &slv_prng, + [SLV_PMIC_ARB] =3D &slv_pmic_arb, + [SLV_SNOC_CFG] =3D &slv_snoc_cfg, + [SLV_DCC_CFG] =3D &slv_dcc_cfg, + [SLV_CAMERA_SS_CFG] =3D &slv_camera_ss_cfg, + [SLV_DISP_SS_CFG] =3D &slv_disp_ss_cfg, + [SLV_VENUS_CFG] =3D &slv_venus_cfg, + [SLV_SDCC_1] =3D &slv_sdcc_1, + [SLV_BLSP_1] =3D &slv_blsp_1, + [SLV_USB_HS] =3D &slv_usb_hs, + [SLV_SDCC_3] =3D &slv_sdcc_3, + [SLV_SDCC_2] =3D &slv_sdcc_2, + [SLV_GPU_CFG] =3D &slv_gpu_cfg, + [SLV_USB_HS2] =3D &slv_usb_hs2, + [SLV_BLSP_2] =3D &slv_blsp_2, + [SLV_PCNOC_SNOC] =3D &slv_pcnoc_snoc, +}; + +static const struct regmap_config msm8976_pcnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8976_pcnoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8976_pcnoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_pcnoc_nodes), + .bus_clk_desc =3D &bus_0_clk, + .qos_offset =3D 0x7000, + .keep_alive =3D true, + .regmap_cfg =3D &msm8976_pcnoc_regmap_config, +}; + +static struct qcom_icc_node * const msm8976_snoc_nodes[] =3D { + [MAS_QDSS_BAM] =3D &mas_qdss_bam, + [MAS_BIMC_SNOC] =3D &mas_bimc_snoc, + [MAS_PCNOC_SNOC] =3D &mas_pcnoc_snoc, + [MAS_QDSS_ETR] =3D &mas_qdss_etr, + [MAS_LPASS_PROC] =3D &mas_lpass_proc, + [MAS_IPA] =3D &mas_ipa, + [QDSS_INT] =3D &qdss_int, + [SNOC_INT_0] =3D &snoc_int_0, + [SNOC_INT_1] =3D &snoc_int_1, + [SNOC_INT_2] =3D &snoc_int_2, + [SLV_KPSS_AHB] =3D &slv_kpss_ahb, + [SLV_SNOC_BIMC] =3D &slv_snoc_bimc, + [SLV_IMEM] =3D &slv_imem, + [SLV_SNOC_PCNOC] =3D &slv_snoc_pcnoc, + [SLV_QDSS_STM] =3D &slv_qdss_stm, + [SLV_CATS_0] =3D &slv_cats_0, + [SLV_CATS_1] =3D &slv_cats_1, + [SLV_LPASS] =3D &slv_lpass, +}; + +static const struct regmap_config msm8976_snoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1A000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8976_snoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8976_snoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_snoc_nodes), + .bus_clk_desc =3D &bus_1_clk, + .intf_clocks =3D snoc_intf_clocks, + .num_intf_clocks =3D ARRAY_SIZE(snoc_intf_clocks), + .regmap_cfg =3D &msm8976_snoc_regmap_config, + .qos_offset =3D 0x7000, +}; + +static struct qcom_icc_node * const msm8976_snoc_mm_nodes[] =3D { + [MAS_JPEG] =3D &mas_jpeg, + [MAS_OXILI] =3D &mas_oxili, + [MAS_MDP0] =3D &mas_mdp0, + [MAS_MDP1] =3D &mas_mdp1, + [MAS_VENUS_0] =3D &mas_venus_0, + [MAS_VENUS_1] =3D &mas_venus_1, + [MAS_VFE_0] =3D &mas_vfe_0, + [MAS_VFE_1] =3D &mas_vfe_1, + [MAS_CPP] =3D &mas_cpp, + [MM_INT_0] =3D &mm_int_0, + [SLV_SMMNOC_BIMC] =3D &slv_smmnoc_bimc, +}; + +static const struct qcom_icc_desc msm8976_snoc_mm =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8976_snoc_mm_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_snoc_mm_nodes), + .bus_clk_desc =3D &bus_2_clk, + .regmap_cfg =3D &msm8976_snoc_regmap_config, + .qos_offset =3D 0x7000, + .ab_coeff =3D 154, +}; + +static const struct of_device_id msm8976_noc_of_match[] =3D { + { .compatible =3D "qcom,msm8976-bimc", .data =3D &msm8976_bimc }, + { .compatible =3D "qcom,msm8976-pcnoc", .data =3D &msm8976_pcnoc }, + { .compatible =3D "qcom,msm8976-snoc", .data =3D &msm8976_snoc }, + { .compatible =3D "qcom,msm8976-snoc-mm", .data =3D &msm8976_snoc_mm }, + { } +}; +MODULE_DEVICE_TABLE(of, msm8976_noc_of_match); + +static struct platform_driver msm8976_noc_driver =3D { + .probe =3D qnoc_probe, + .remove_new =3D qnoc_remove, + .driver =3D { + .name =3D "qnoc-msm8976", + .of_match_table =3D msm8976_noc_of_match, + .sync_state =3D icc_sync_state, + }, +}; +module_platform_driver(msm8976_noc_driver); + +MODULE_DESCRIPTION("Qualcomm MSM8976 NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.45.1 From nobody Thu Feb 12 17:27:58 2026 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76EED50291; 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[83.30.46.83]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ebd5a63bf2sm6679841fa.33.2024.06.09.11.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 11:21:36 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] dt-bindings: interconnect: Add Qualcomm MSM8937 DT bindings Date: Sun, 9 Jun 2024 20:20:56 +0200 Message-Id: <20240609182112.13032-4-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240609182112.13032-1-a39.skl@gmail.com> References: <20240609182112.13032-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for Qualcomm MSM8937 Network-On-Chip interconnect devices. Signed-off-by: Adam Skladowski --- .../bindings/interconnect/qcom,msm8937.yaml | 81 ++++++++++++++++ .../dt-bindings/interconnect/qcom,msm8937.h | 93 +++++++++++++++++++ 2 files changed, 174 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm= 8937.yaml create mode 100644 include/dt-bindings/interconnect/qcom,msm8937.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8937.ya= ml b/Documentation/devicetree/bindings/interconnect/qcom,msm8937.yaml new file mode 100644 index 000000000000..39a1ca441bb2 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8937.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8937.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8937 Network-On-Chip interconnect + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm MSM8937 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +allOf: + - $ref: qcom,rpm-common.yaml# + +properties: + compatible: + enum: + - qcom,msm8937-bimc + - qcom,msm8937-pcnoc + - qcom,msm8937-snoc + + reg: + maxItems: 1 + +patternProperties: + '^interconnect-[a-z0-9\-]+$': + type: object + $ref: qcom,rpm-common.yaml# + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + allOf: + - $ref: qcom,rpm-common.yaml# + + properties: + compatible: + const: qcom,msm8937-snoc-mm + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bimc: interconnect@400000 { + compatible =3D "qcom,msm8937-bimc"; + reg =3D <0x00400000 0x5a000>; + #interconnect-cells =3D <2>; + }; + + pcnoc: interconnect@500000 { + compatible =3D "qcom,msm8937-pcnoc"; + reg =3D <0x00500000 0x13080>; + #interconnect-cells =3D <2>; + }; + + snoc: interconnect@580000 { + compatible =3D "qcom,msm8937-bimc"; + reg =3D <0x00580000 0x16080>; + #interconnect-cells =3D <2>; + + snoc_mm: interconnect-snoc { + compatible =3D "qcom,msm8937-snoc-mm"; + #interconnect-cells =3D <2>; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,msm8937.h b/include/dt-b= indings/interconnect/qcom,msm8937.h new file mode 100644 index 000000000000..98b8a4637aab --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8937.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm MSM8937 interconnect IDs + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H + +/* BIMC fabric */ +#define MAS_APPS_PROC 0 +#define MAS_OXILI 1 +#define MAS_SNOC_BIMC_0 2 +#define MAS_SNOC_BIMC_2 3 +#define MAS_SNOC_BIMC_1 4 +#define MAS_TCU_0 5 +#define SLV_EBI 6 +#define SLV_BIMC_SNOC 7 + +/* PCNOC fabric */ +#define MAS_SPDM 0 +#define MAS_BLSP_1 1 +#define MAS_BLSP_2 2 +#define MAS_USB_HS1 3 +#define MAS_XI_USB_HS1 4 +#define MAS_CRYPTO 5 +#define MAS_SDCC_1 6 +#define MAS_SDCC_2 7 +#define MAS_SNOC_PCNOC 8 +#define PCNOC_M_0 9 +#define PCNOC_M_1 10 +#define PCNOC_INT_0 11 +#define PCNOC_INT_1 12 +#define PCNOC_INT_2 13 +#define PCNOC_INT_3 14 +#define PCNOC_S_0 15 +#define PCNOC_S_1 16 +#define PCNOC_S_2 17 +#define PCNOC_S_3 18 +#define PCNOC_S_4 19 +#define PCNOC_S_6 20 +#define PCNOC_S_7 21 +#define PCNOC_S_8 22 +#define SLV_SDCC_2 23 +#define SLV_SPDM 24 +#define SLV_PDM 25 +#define SLV_PRNG 26 +#define SLV_TCSR 27 +#define SLV_SNOC_CFG 28 +#define SLV_MESSAGE_RAM 29 +#define SLV_CAMERA_SS_CFG 30 +#define SLV_DISP_SS_CFG 31 +#define SLV_VENUS_CFG 32 +#define SLV_GPU_CFG 33 +#define SLV_TLMM 34 +#define SLV_BLSP_1 35 +#define SLV_BLSP_2 36 +#define SLV_PMIC_ARB 37 +#define SLV_SDCC_1 38 +#define SLV_CRYPTO_0_CFG 39 +#define SLV_USB_HS 40 +#define SLV_TCU 41 +#define SLV_PCNOC_SNOC 42 + +/* SNOC fabric */ +#define MAS_QDSS_BAM 0 +#define MAS_BIMC_SNOC 1 +#define MAS_PCNOC_SNOC 2 +#define MAS_QDSS_ETR 3 +#define QDSS_INT 4 +#define SNOC_INT_0 5 +#define SNOC_INT_1 6 +#define SNOC_INT_2 7 +#define SLV_KPSS_AHB 8 +#define SLV_WCSS 9 +#define SLV_SNOC_BIMC_1 10 +#define SLV_IMEM 11 +#define SLV_SNOC_PCNOC 12 +#define SLV_QDSS_STM 13 +#define SLV_CATS_1 14 +#define SLV_LPASS 15 + +/* SNOC-MM fabric */ +#define MAS_JPEG 0 +#define MAS_MDP 1 +#define MAS_VENUS 2 +#define MAS_VFE0 3 +#define MAS_VFE1 4 +#define MAS_CPP 5 +#define SLV_SNOC_BIMC_0 6 +#define SLV_SNOC_BIMC_2 7 +#define SLV_CATS_0 8 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8937_H */ --=20 2.45.1 From nobody Thu Feb 12 17:27:58 2026 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E589F55887; 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[83.30.46.83]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ebd5a63bf2sm6679841fa.33.2024.06.09.11.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 11:21:40 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] interconnect: qcom: Add MSM8937 interconnect provider driver Date: Sun, 9 Jun 2024 20:20:57 +0200 Message-Id: <20240609182112.13032-5-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240609182112.13032-1-a39.skl@gmail.com> References: <20240609182112.13032-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver for interconnect busses found in MSM8937 based platforms. The topology consists of four NoCs that are partially controlled by a RPM processor. Signed-off-by: Adam Skladowski --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/msm8937.c | 1374 +++++++++++++++++++++++++++ 3 files changed, 1385 insertions(+) create mode 100644 drivers/interconnect/qcom/msm8937.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index a0e9c09954ed..c3c534e7dad6 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -26,6 +26,15 @@ config INTERCONNECT_QCOM_MSM8916 This is a driver for the Qualcomm Network-on-Chip on msm8916-based platforms. =20 +config INTERCONNECT_QCOM_MSM8937 + tristate "Qualcomm MSM8937 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8937-based + platforms. + config INTERCONNECT_QCOM_MSM8939 tristate "Qualcomm MSM8939 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 21ce45438258..a27dcb474df5 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -6,6 +6,7 @@ interconnect_qcom-y :=3D icc-common.o icc-bcm-voter-objs :=3D bcm-voter.o qnoc-msm8909-objs :=3D msm8909.o qnoc-msm8916-objs :=3D msm8916.o +qnoc-msm8937-objs :=3D msm8937.o qnoc-msm8939-objs :=3D msm8939.o qnoc-msm8974-objs :=3D msm8974.o qnoc-msm8976-objs :=3D msm8976.o @@ -41,6 +42,7 @@ icc-smd-rpm-objs :=3D smd-rpm.o icc-rpm.o icc-rpm-clock= s.o obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) +=3D icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) +=3D qnoc-msm8916.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8937) +=3D qnoc-msm8937.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) +=3D qnoc-msm8939.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) +=3D qnoc-msm8974.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) +=3D qnoc-msm8976.o diff --git a/drivers/interconnect/qcom/msm8937.c b/drivers/interconnect/qco= m/msm8937.c new file mode 100644 index 000000000000..470175c1c38b --- /dev/null +++ b/drivers/interconnect/qcom/msm8937.c @@ -0,0 +1,1374 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on data from msm8937-bus.dtsi in Qualcomm's msm-3.18 release: + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + + +#include +#include +#include +#include +#include +#include + + +#include + +#include "icc-rpm.h" + +enum { + QNOC_MASTER_AMPSS_M0 =3D 1, + QNOC_MASTER_GRAPHICS_3D, + QNOC_SNOC_BIMC_0_MAS, + QNOC_SNOC_BIMC_2_MAS, + QNOC_SNOC_BIMC_1_MAS, + QNOC_MASTER_TCU_0, + QNOC_MASTER_SPDM, + QNOC_MASTER_BLSP_1, + QNOC_MASTER_BLSP_2, + QNOC_MASTER_USB_HS, + QNOC_MASTER_XM_USB_HS1, + QNOC_MASTER_CRYPTO_CORE0, + QNOC_MASTER_SDCC_1, + QNOC_MASTER_SDCC_2, + QNOC_SNOC_PNOC_MAS, + QNOC_MASTER_QDSS_BAM, + QNOC_BIMC_SNOC_MAS, + QNOC_MASTER_JPEG, + QNOC_MASTER_MDP_PORT0, + QNOC_PNOC_SNOC_MAS, + QNOC_MASTER_VIDEO_P0, + QNOC_MASTER_VFE, + QNOC_MASTER_VFE1, + QNOC_MASTER_CPP, + QNOC_MASTER_QDSS_ETR, + QNOC_PNOC_M_0, + QNOC_PNOC_M_1, + QNOC_PNOC_INT_0, + QNOC_PNOC_INT_1, + QNOC_PNOC_INT_2, + QNOC_PNOC_INT_3, + QNOC_PNOC_SLV_0, + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_3, + QNOC_PNOC_SLV_4, + QNOC_PNOC_SLV_6, + QNOC_PNOC_SLV_7, + QNOC_PNOC_SLV_8, + QNOC_SNOC_QDSS_INT, + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_INT_2, + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_SDCC_2, + QNOC_SLAVE_SPDM_WRAPPER, + QNOC_SLAVE_PDM, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_TCSR, + QNOC_SLAVE_SNOC_CFG, + QNOC_SLAVE_MESSAGE_RAM, + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG, + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_TLMM, + QNOC_SLAVE_BLSP_1, + QNOC_SLAVE_BLSP_2, + QNOC_SLAVE_PMIC_ARB, + QNOC_SLAVE_SDCC_1, + QNOC_SLAVE_CRYPTO_0_CFG, + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_TCU, + QNOC_PNOC_SNOC_SLV, + QNOC_SLAVE_APPSS, + QNOC_SLAVE_WCSS, + QNOC_SNOC_BIMC_0_SLV, + QNOC_SNOC_BIMC_1_SLV, + QNOC_SNOC_BIMC_2_SLV, + QNOC_SLAVE_OCIMEM, + QNOC_SNOC_PNOC_SLV, + QNOC_SLAVE_QDSS_STM, + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_OCMEM_64, + QNOC_SLAVE_LPASS, +}; + +static const u16 mas_apps_proc_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_apps_proc =3D { + .name =3D "mas_apps_proc", + .id =3D QNOC_MASTER_AMPSS_M0, + .buswidth =3D 8, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_apps_proc_links), + .links =3D mas_apps_proc_links, +}; + +static const u16 mas_oxili_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_oxili =3D { + .name =3D "mas_oxili", + .id =3D QNOC_MASTER_GRAPHICS_3D, + .buswidth =3D 8, + .mas_rpm_id =3D 6, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 2, + .num_links =3D ARRAY_SIZE(mas_oxili_links), + .links =3D mas_oxili_links, +}; + +static const u16 mas_snoc_bimc_0_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_snoc_bimc_0 =3D { + .name =3D "mas_snoc_bimc_0", + .id =3D QNOC_SNOC_BIMC_0_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 3, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 3, + .num_links =3D ARRAY_SIZE(mas_snoc_bimc_0_links), + .links =3D mas_snoc_bimc_0_links, +}; + +static const u16 mas_snoc_bimc_2_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_snoc_bimc_2 =3D { + .name =3D "mas_snoc_bimc_2", + .id =3D QNOC_SNOC_BIMC_2_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 108, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 4, + .num_links =3D ARRAY_SIZE(mas_snoc_bimc_2_links), + .links =3D mas_snoc_bimc_2_links, +}; + +static const u16 mas_snoc_bimc_1_links[] =3D { + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_snoc_bimc_1 =3D { + .name =3D "mas_snoc_bimc_1", + .id =3D QNOC_SNOC_BIMC_1_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 76, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(mas_snoc_bimc_1_links), + .links =3D mas_snoc_bimc_1_links, +}; + +static const u16 mas_tcu_0_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_tcu_0 =3D { + .name =3D "mas_tcu_0", + .id =3D QNOC_MASTER_TCU_0, + .buswidth =3D 8, + .mas_rpm_id =3D 102, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 2, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(mas_tcu_0_links), + .links =3D mas_tcu_0_links, +}; + +static const u16 mas_spdm_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_spdm =3D { + .name =3D "mas_spdm", + .id =3D QNOC_MASTER_SPDM, + .buswidth =3D 4, + .mas_rpm_id =3D 50, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(mas_spdm_links), + .links =3D mas_spdm_links, +}; + +static const u16 mas_blsp_1_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_blsp_1 =3D { + .name =3D "mas_blsp_1", + .id =3D QNOC_MASTER_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D 41, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_1_links), + .links =3D mas_blsp_1_links, +}; + +static const u16 mas_blsp_2_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_blsp_2 =3D { + .name =3D "mas_blsp_2", + .id =3D QNOC_MASTER_BLSP_2, + .buswidth =3D 4, + .mas_rpm_id =3D 39, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_2_links), + .links =3D mas_blsp_2_links, +}; + +static const u16 mas_usb_hs1_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_usb_hs1 =3D { + .name =3D "mas_usb_hs1", + .id =3D QNOC_MASTER_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D 42, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 12, + .num_links =3D ARRAY_SIZE(mas_usb_hs1_links), + .links =3D mas_usb_hs1_links, +}; + +static const u16 mas_xi_usb_hs1_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_xi_usb_hs1 =3D { + .name =3D "mas_xi_usb_hs1", + .id =3D QNOC_MASTER_XM_USB_HS1, + .buswidth =3D 8, + .mas_rpm_id =3D 138, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 11, + .num_links =3D ARRAY_SIZE(mas_xi_usb_hs1_links), + .links =3D mas_xi_usb_hs1_links, +}; + +static const u16 mas_crypto_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_crypto =3D { + .name =3D "mas_crypto", + .id =3D QNOC_MASTER_CRYPTO_CORE0, + .buswidth =3D 8, + .mas_rpm_id =3D 23, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_crypto_links), + .links =3D mas_crypto_links, +}; + +static const u16 mas_sdcc_1_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_sdcc_1 =3D { + .name =3D "mas_sdcc_1", + .id =3D QNOC_MASTER_SDCC_1, + .buswidth =3D 8, + .mas_rpm_id =3D 33, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_sdcc_1_links), + .links =3D mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_2_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_sdcc_2 =3D { + .name =3D "mas_sdcc_2", + .id =3D QNOC_MASTER_SDCC_2, + .buswidth =3D 8, + .mas_rpm_id =3D 35, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_sdcc_2_links), + .links =3D mas_sdcc_2_links, +}; + +static const u16 mas_snoc_pcnoc_links[] =3D { + QNOC_PNOC_SLV_7, + QNOC_PNOC_INT_2, + QNOC_PNOC_INT_3 +}; + +static struct qcom_icc_node mas_snoc_pcnoc =3D { + .name =3D "mas_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 77, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_snoc_pcnoc_links), + .links =3D mas_snoc_pcnoc_links, +}; + +static const u16 mas_qdss_bam_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_bam =3D { + .name =3D "mas_qdss_bam", + .id =3D QNOC_MASTER_QDSS_BAM, + .buswidth =3D 4, + .mas_rpm_id =3D 19, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 11, + .num_links =3D ARRAY_SIZE(mas_qdss_bam_links), + .links =3D mas_qdss_bam_links, +}; + +static const u16 mas_bimc_snoc_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node mas_bimc_snoc =3D { + .name =3D "mas_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 21, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_bimc_snoc_links), + .links =3D mas_bimc_snoc_links, +}; + +static const u16 mas_jpeg_links[] =3D { + QNOC_SNOC_BIMC_2_SLV +}; + +static struct qcom_icc_node mas_jpeg =3D { + .name =3D "mas_jpeg", + .id =3D QNOC_MASTER_JPEG, + .buswidth =3D 16, + .mas_rpm_id =3D 7, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(mas_jpeg_links), + .links =3D mas_jpeg_links, +}; + +static const u16 mas_mdp_links[] =3D { + QNOC_SNOC_BIMC_0_SLV +}; + +static struct qcom_icc_node mas_mdp =3D { + .name =3D "mas_mdp", + .id =3D QNOC_MASTER_MDP_PORT0, + .buswidth =3D 16, + .mas_rpm_id =3D 8, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_mdp_links), + .links =3D mas_mdp_links, +}; + +static const u16 mas_pcnoc_snoc_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_BIMC_1_SLV +}; + +static struct qcom_icc_node mas_pcnoc_snoc =3D { + .name =3D "mas_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 29, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(mas_pcnoc_snoc_links), + .links =3D mas_pcnoc_snoc_links, +}; + +static const u16 mas_venus_links[] =3D { + QNOC_SNOC_BIMC_2_SLV +}; + +static struct qcom_icc_node mas_venus =3D { + .name =3D "mas_venus", + .id =3D QNOC_MASTER_VIDEO_P0, + .buswidth =3D 16, + .mas_rpm_id =3D 9, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_venus_links), + .links =3D mas_venus_links, +}; + +static const u16 mas_vfe0_links[] =3D { + QNOC_SNOC_BIMC_0_SLV +}; + +static struct qcom_icc_node mas_vfe0 =3D { + .name =3D "mas_vfe0", + .id =3D QNOC_MASTER_VFE, + .buswidth =3D 16, + .mas_rpm_id =3D 11, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_vfe0_links), + .links =3D mas_vfe0_links, +}; + +static const u16 mas_vfe1_links[] =3D { + QNOC_SNOC_BIMC_0_SLV +}; + +static struct qcom_icc_node mas_vfe1 =3D { + .name =3D "mas_vfe1", + .id =3D QNOC_MASTER_VFE1, + .buswidth =3D 16, + .mas_rpm_id =3D 133, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 13, + .num_links =3D ARRAY_SIZE(mas_vfe1_links), + .links =3D mas_vfe1_links, +}; + +static const u16 mas_cpp_links[] =3D { + QNOC_SNOC_BIMC_2_SLV +}; + +static struct qcom_icc_node mas_cpp =3D { + .name =3D "mas_cpp", + .id =3D QNOC_MASTER_CPP, + .buswidth =3D 16, + .mas_rpm_id =3D 115, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 12, + .num_links =3D ARRAY_SIZE(mas_cpp_links), + .links =3D mas_cpp_links, +}; + +static const u16 mas_qdss_etr_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_etr =3D { + .name =3D "mas_qdss_etr", + .id =3D QNOC_MASTER_QDSS_ETR, + .buswidth =3D 8, + .mas_rpm_id =3D 31, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 10, + .num_links =3D ARRAY_SIZE(mas_qdss_etr_links), + .links =3D mas_qdss_etr_links, +}; + +static const u16 pcnoc_m_0_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node pcnoc_m_0 =3D { + .name =3D "pcnoc_m_0", + .id =3D QNOC_PNOC_M_0, + .buswidth =3D 4, + .mas_rpm_id =3D 87, + .slv_rpm_id =3D 116, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(pcnoc_m_0_links), + .links =3D pcnoc_m_0_links, +}; + +static const u16 pcnoc_m_1_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node pcnoc_m_1 =3D { + .name =3D "pcnoc_m_1", + .id =3D QNOC_PNOC_M_1, + .buswidth =3D 4, + .mas_rpm_id =3D 88, + .slv_rpm_id =3D 117, + .num_links =3D ARRAY_SIZE(pcnoc_m_1_links), + .links =3D pcnoc_m_1_links, +}; + +static const u16 pcnoc_int_0_links[] =3D { + QNOC_PNOC_SNOC_SLV, + QNOC_PNOC_SLV_7, + QNOC_PNOC_INT_3, + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node pcnoc_int_0 =3D { + .name =3D "pcnoc_int_0", + .id =3D QNOC_PNOC_INT_0, + .buswidth =3D 8, + .mas_rpm_id =3D 85, + .slv_rpm_id =3D 114, + .num_links =3D ARRAY_SIZE(pcnoc_int_0_links), + .links =3D pcnoc_int_0_links, +}; + +static const u16 pcnoc_int_1_links[] =3D { + QNOC_PNOC_SNOC_SLV, + QNOC_PNOC_SLV_7, + QNOC_PNOC_INT_3, + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node pcnoc_int_1 =3D { + .name =3D "pcnoc_int_1", + .id =3D QNOC_PNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(pcnoc_int_1_links), + .links =3D pcnoc_int_1_links, +}; + +static const u16 pcnoc_int_2_links[] =3D { + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_3, + QNOC_PNOC_SLV_6, + QNOC_PNOC_SLV_8 +}; + +static struct qcom_icc_node pcnoc_int_2 =3D { + .name =3D "pcnoc_int_2", + .id =3D QNOC_PNOC_INT_2, + .buswidth =3D 8, + .mas_rpm_id =3D 124, + .slv_rpm_id =3D 184, + .num_links =3D ARRAY_SIZE(pcnoc_int_2_links), + .links =3D pcnoc_int_2_links, +}; + +static const u16 pcnoc_int_3_links[] =3D { + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_0, + QNOC_PNOC_SLV_4, + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_TCU +}; + +static struct qcom_icc_node pcnoc_int_3 =3D { + .name =3D "pcnoc_int_3", + .id =3D QNOC_PNOC_INT_3, + .buswidth =3D 8, + .mas_rpm_id =3D 125, + .slv_rpm_id =3D 185, + .num_links =3D ARRAY_SIZE(pcnoc_int_3_links), + .links =3D pcnoc_int_3_links, +}; + +static const u16 pcnoc_s_0_links[] =3D { + QNOC_SLAVE_SPDM_WRAPPER, + QNOC_SLAVE_PDM, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_SDCC_2 +}; + +static struct qcom_icc_node pcnoc_s_0 =3D { + .name =3D "pcnoc_s_0", + .id =3D QNOC_PNOC_SLV_0, + .buswidth =3D 4, + .mas_rpm_id =3D 89, + .slv_rpm_id =3D 118, + .num_links =3D ARRAY_SIZE(pcnoc_s_0_links), + .links =3D pcnoc_s_0_links, +}; + +static const u16 pcnoc_s_1_links[] =3D { + QNOC_SLAVE_TCSR +}; + +static struct qcom_icc_node pcnoc_s_1 =3D { + .name =3D "pcnoc_s_1", + .id =3D QNOC_PNOC_SLV_1, + .buswidth =3D 4, + .mas_rpm_id =3D 90, + .slv_rpm_id =3D 119, + .num_links =3D ARRAY_SIZE(pcnoc_s_1_links), + .links =3D pcnoc_s_1_links, +}; + +static const u16 pcnoc_s_2_links[] =3D { + QNOC_SLAVE_SNOC_CFG +}; + +static struct qcom_icc_node pcnoc_s_2 =3D { + .name =3D "pcnoc_s_2", + .id =3D QNOC_PNOC_SLV_2, + .buswidth =3D 4, + .mas_rpm_id =3D 91, + .slv_rpm_id =3D 120, + .num_links =3D ARRAY_SIZE(pcnoc_s_2_links), + .links =3D pcnoc_s_2_links, +}; + +static const u16 pcnoc_s_3_links[] =3D { + QNOC_SLAVE_MESSAGE_RAM +}; + +static struct qcom_icc_node pcnoc_s_3 =3D { + .name =3D "pcnoc_s_3", + .id =3D QNOC_PNOC_SLV_3, + .buswidth =3D 4, + .mas_rpm_id =3D 92, + .slv_rpm_id =3D 121, + .num_links =3D ARRAY_SIZE(pcnoc_s_3_links), + .links =3D pcnoc_s_3_links, +}; + +static const u16 pcnoc_s_4_links[] =3D { + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG +}; + +static struct qcom_icc_node pcnoc_s_4 =3D { + .name =3D "pcnoc_s_4", + .id =3D QNOC_PNOC_SLV_4, + .buswidth =3D 4, + .mas_rpm_id =3D 93, + .slv_rpm_id =3D 122, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(pcnoc_s_4_links), + .links =3D pcnoc_s_4_links, +}; + +static const u16 pcnoc_s_6_links[] =3D { + QNOC_SLAVE_TLMM, + QNOC_SLAVE_BLSP_1, + QNOC_SLAVE_BLSP_2 +}; + +static struct qcom_icc_node pcnoc_s_6 =3D { + .name =3D "pcnoc_s_6", + .id =3D QNOC_PNOC_SLV_6, + .buswidth =3D 4, + .mas_rpm_id =3D 94, + .slv_rpm_id =3D 123, + .num_links =3D ARRAY_SIZE(pcnoc_s_6_links), + .links =3D pcnoc_s_6_links, +}; + +static const u16 pcnoc_s_7_links[] =3D { + QNOC_SLAVE_SDCC_1, + QNOC_SLAVE_PMIC_ARB +}; + +static struct qcom_icc_node pcnoc_s_7 =3D { + .name =3D "pcnoc_s_7", + .id =3D QNOC_PNOC_SLV_7, + .buswidth =3D 4, + .mas_rpm_id =3D 95, + .slv_rpm_id =3D 124, + .num_links =3D ARRAY_SIZE(pcnoc_s_7_links), + .links =3D pcnoc_s_7_links, +}; + +static const u16 pcnoc_s_8_links[] =3D { + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_CRYPTO_0_CFG +}; + +static struct qcom_icc_node pcnoc_s_8 =3D { + .name =3D "pcnoc_s_8", + .id =3D QNOC_PNOC_SLV_8, + .buswidth =3D 4, + .mas_rpm_id =3D 96, + .slv_rpm_id =3D 125, + .num_links =3D ARRAY_SIZE(pcnoc_s_8_links), + .links =3D pcnoc_s_8_links, +}; + +static const u16 qdss_int_links[] =3D { + QNOC_SNOC_INT_1, + QNOC_SNOC_BIMC_1_SLV +}; + +static struct qcom_icc_node qdss_int =3D { + .name =3D "qdss_int", + .id =3D QNOC_SNOC_QDSS_INT, + .buswidth =3D 8, + .mas_rpm_id =3D 98, + .slv_rpm_id =3D 128, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(qdss_int_links), + .links =3D qdss_int_links, +}; + +static const u16 snoc_int_0_links[] =3D { + QNOC_SLAVE_LPASS, + QNOC_SLAVE_WCSS, + QNOC_SLAVE_APPSS +}; + +static struct qcom_icc_node snoc_int_0 =3D { + .name =3D "snoc_int_0", + .id =3D QNOC_SNOC_INT_0, + .buswidth =3D 8, + .mas_rpm_id =3D 99, + .slv_rpm_id =3D 130, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(snoc_int_0_links), + .links =3D snoc_int_0_links, +}; + +static const u16 snoc_int_1_links[] =3D { + QNOC_SLAVE_QDSS_STM, + QNOC_SLAVE_OCIMEM, + QNOC_SNOC_PNOC_SLV +}; + +static struct qcom_icc_node snoc_int_1 =3D { + .name =3D "snoc_int_1", + .id =3D QNOC_SNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D 100, + .slv_rpm_id =3D 131, + .num_links =3D ARRAY_SIZE(snoc_int_1_links), + .links =3D snoc_int_1_links, +}; + +static const u16 snoc_int_2_links[] =3D { + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_OCMEM_64 +}; + +static struct qcom_icc_node snoc_int_2 =3D { + .name =3D "snoc_int_2", + .id =3D QNOC_SNOC_INT_2, + .buswidth =3D 8, + .mas_rpm_id =3D 134, + .slv_rpm_id =3D 197, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(snoc_int_2_links), + .links =3D snoc_int_2_links, +}; + + +static struct qcom_icc_node slv_ebi =3D { + .name =3D "slv_ebi", + .id =3D QNOC_SLAVE_EBI_CH0, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 0, +}; + +static const u16 slv_bimc_snoc_links[] =3D { + QNOC_BIMC_SNOC_MAS +}; + +static struct qcom_icc_node slv_bimc_snoc =3D { + .name =3D "slv_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 2, + .num_links =3D ARRAY_SIZE(slv_bimc_snoc_links), + .links =3D slv_bimc_snoc_links, +}; + + +static struct qcom_icc_node slv_sdcc_2 =3D { + .name =3D "slv_sdcc_2", + .id =3D QNOC_SLAVE_SDCC_2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 33, +}; + + +static struct qcom_icc_node slv_spdm =3D { + .name =3D "slv_spdm", + .id =3D QNOC_SLAVE_SPDM_WRAPPER, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 60, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + + +static struct qcom_icc_node slv_pdm =3D { + .name =3D "slv_pdm", + .id =3D QNOC_SLAVE_PDM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 41, +}; + + +static struct qcom_icc_node slv_prng =3D { + .name =3D "slv_prng", + .id =3D QNOC_SLAVE_PRNG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 44, +}; + + +static struct qcom_icc_node slv_tcsr =3D { + .name =3D "slv_tcsr", + .id =3D QNOC_SLAVE_TCSR, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 50, +}; + + +static struct qcom_icc_node slv_snoc_cfg =3D { + .name =3D "slv_snoc_cfg", + .id =3D QNOC_SLAVE_SNOC_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 70, +}; + + +static struct qcom_icc_node slv_message_ram =3D { + .name =3D "slv_message_ram", + .id =3D QNOC_SLAVE_MESSAGE_RAM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 55, +}; + + +static struct qcom_icc_node slv_camera_ss_cfg =3D { + .name =3D "slv_camera_ss_cfg", + .id =3D QNOC_SLAVE_CAMERA_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 3, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + + +static struct qcom_icc_node slv_disp_ss_cfg =3D { + .name =3D "slv_disp_ss_cfg", + .id =3D QNOC_SLAVE_DISPLAY_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 4, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + + +static struct qcom_icc_node slv_venus_cfg =3D { + .name =3D "slv_venus_cfg", + .id =3D QNOC_SLAVE_VENUS_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 10, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + + +static struct qcom_icc_node slv_gpu_cfg =3D { + .name =3D "slv_gpu_cfg", + .id =3D QNOC_SLAVE_GRAPHICS_3D_CFG, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 11, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + + +static struct qcom_icc_node slv_tlmm =3D { + .name =3D "slv_tlmm", + .id =3D QNOC_SLAVE_TLMM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 51, +}; + + +static struct qcom_icc_node slv_blsp_1 =3D { + .name =3D "slv_blsp_1", + .id =3D QNOC_SLAVE_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 39, +}; + + +static struct qcom_icc_node slv_blsp_2 =3D { + .name =3D "slv_blsp_2", + .id =3D QNOC_SLAVE_BLSP_2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 37, +}; + + +static struct qcom_icc_node slv_pmic_arb =3D { + .name =3D "slv_pmic_arb", + .id =3D QNOC_SLAVE_PMIC_ARB, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 59, +}; + + +static struct qcom_icc_node slv_sdcc_1 =3D { + .name =3D "slv_sdcc_1", + .id =3D QNOC_SLAVE_SDCC_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 31, +}; + + +static struct qcom_icc_node slv_crypto_0_cfg =3D { + .name =3D "slv_crypto_0_cfg", + .id =3D QNOC_SLAVE_CRYPTO_0_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 52, +}; + + +static struct qcom_icc_node slv_usb_hs =3D { + .name =3D "slv_usb_hs", + .id =3D QNOC_SLAVE_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 40, +}; + + +static struct qcom_icc_node slv_tcu =3D { + .name =3D "slv_tcu", + .id =3D QNOC_SLAVE_TCU, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 133, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static const u16 slv_pcnoc_snoc_links[] =3D { + QNOC_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node slv_pcnoc_snoc =3D { + .name =3D "slv_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 45, + .num_links =3D ARRAY_SIZE(slv_pcnoc_snoc_links), + .links =3D slv_pcnoc_snoc_links, +}; + + +static struct qcom_icc_node slv_kpss_ahb =3D { + .name =3D "slv_kpss_ahb", + .id =3D QNOC_SLAVE_APPSS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 20, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + + +static struct qcom_icc_node slv_wcss =3D { + .name =3D "slv_wcss", + .id =3D QNOC_SLAVE_WCSS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 23, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static const u16 slv_snoc_bimc_0_links[] =3D { + QNOC_SNOC_BIMC_0_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc_0 =3D { + .name =3D "slv_snoc_bimc_0", + .id =3D QNOC_SNOC_BIMC_0_SLV, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 24, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_0_links), + .links =3D slv_snoc_bimc_0_links, +}; + +static const u16 slv_snoc_bimc_1_links[] =3D { + QNOC_SNOC_BIMC_1_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc_1 =3D { + .name =3D "slv_snoc_bimc_1", + .id =3D QNOC_SNOC_BIMC_1_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 104, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_1_links), + .links =3D slv_snoc_bimc_1_links, +}; + +static const u16 slv_snoc_bimc_2_links[] =3D { + QNOC_SNOC_BIMC_2_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc_2 =3D { + .name =3D "slv_snoc_bimc_2", + .id =3D QNOC_SNOC_BIMC_2_SLV, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 137, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_2_links), + .links =3D slv_snoc_bimc_2_links, +}; + +static struct qcom_icc_node slv_imem =3D { + .name =3D "slv_imem", + .id =3D QNOC_SLAVE_OCIMEM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 26, +}; + +static const u16 slv_snoc_pcnoc_links[] =3D { + QNOC_SNOC_PNOC_MAS +}; + +static struct qcom_icc_node slv_snoc_pcnoc =3D { + .name =3D "slv_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 28, + .num_links =3D ARRAY_SIZE(slv_snoc_pcnoc_links), + .links =3D slv_snoc_pcnoc_links, +}; + +static struct qcom_icc_node slv_qdss_stm =3D { + .name =3D "slv_qdss_stm", + .id =3D QNOC_SLAVE_QDSS_STM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 30, +}; + +static struct qcom_icc_node slv_cats_0 =3D { + .name =3D "slv_cats_0", + .id =3D QNOC_SLAVE_CATS_128, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 106, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_cats_1 =3D { + .name =3D "slv_cats_1", + .id =3D QNOC_SLAVE_OCMEM_64, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 107, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_lpass =3D { + .name =3D "slv_lpass", + .id =3D QNOC_SLAVE_LPASS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 21, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node *msm8937_bimc_nodes[] =3D { + [MAS_APPS_PROC] =3D &mas_apps_proc, + [MAS_OXILI] =3D &mas_oxili, + [MAS_SNOC_BIMC_0] =3D &mas_snoc_bimc_0, + [MAS_SNOC_BIMC_2] =3D &mas_snoc_bimc_2, + [MAS_SNOC_BIMC_1] =3D &mas_snoc_bimc_1, + [MAS_TCU_0] =3D &mas_tcu_0, + [SLV_EBI] =3D &slv_ebi, + [SLV_BIMC_SNOC] =3D &slv_bimc_snoc, +}; + +static const struct regmap_config msm8937_bimc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5A000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8937_bimc =3D { + .type =3D QCOM_ICC_BIMC, + .nodes =3D msm8937_bimc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8937_bimc_nodes), + .bus_clk_desc =3D &bimc_clk, + .regmap_cfg =3D &msm8937_bimc_regmap_config, + .qos_offset =3D 0x8000, + .ab_coeff =3D 154, +}; + +static struct qcom_icc_node *msm8937_pcnoc_nodes[] =3D { + [MAS_SPDM] =3D &mas_spdm, + [MAS_BLSP_1] =3D &mas_blsp_1, + [MAS_BLSP_2] =3D &mas_blsp_2, + [MAS_USB_HS1] =3D &mas_usb_hs1, + [MAS_XI_USB_HS1] =3D &mas_xi_usb_hs1, + [MAS_CRYPTO] =3D &mas_crypto, + [MAS_SDCC_1] =3D &mas_sdcc_1, + [MAS_SDCC_2] =3D &mas_sdcc_2, + [MAS_SNOC_PCNOC] =3D &mas_snoc_pcnoc, + [PCNOC_M_0] =3D &pcnoc_m_0, + [PCNOC_M_1] =3D &pcnoc_m_1, + [PCNOC_INT_0] =3D &pcnoc_int_0, + [PCNOC_INT_1] =3D &pcnoc_int_1, + [PCNOC_INT_2] =3D &pcnoc_int_2, + [PCNOC_INT_3] =3D &pcnoc_int_3, + [PCNOC_S_0] =3D &pcnoc_s_0, + [PCNOC_S_1] =3D &pcnoc_s_1, + [PCNOC_S_2] =3D &pcnoc_s_2, + [PCNOC_S_3] =3D &pcnoc_s_3, + [PCNOC_S_4] =3D &pcnoc_s_4, + [PCNOC_S_6] =3D &pcnoc_s_6, + [PCNOC_S_7] =3D &pcnoc_s_7, + [PCNOC_S_8] =3D &pcnoc_s_8, + [SLV_SDCC_2] =3D &slv_sdcc_2, + [SLV_SPDM] =3D &slv_spdm, + [SLV_PDM] =3D &slv_pdm, + [SLV_PRNG] =3D &slv_prng, + [SLV_TCSR] =3D &slv_tcsr, + [SLV_SNOC_CFG] =3D &slv_snoc_cfg, + [SLV_MESSAGE_RAM] =3D &slv_message_ram, + [SLV_CAMERA_SS_CFG] =3D &slv_camera_ss_cfg, + [SLV_DISP_SS_CFG] =3D &slv_disp_ss_cfg, + [SLV_VENUS_CFG] =3D &slv_venus_cfg, + [SLV_GPU_CFG] =3D &slv_gpu_cfg, + [SLV_TLMM] =3D &slv_tlmm, + [SLV_BLSP_1] =3D &slv_blsp_1, + [SLV_BLSP_2] =3D &slv_blsp_2, + [SLV_PMIC_ARB] =3D &slv_pmic_arb, + [SLV_SDCC_1] =3D &slv_sdcc_1, + [SLV_CRYPTO_0_CFG] =3D &slv_crypto_0_cfg, + [SLV_USB_HS] =3D &slv_usb_hs, + [SLV_TCU] =3D &slv_tcu, + [SLV_PCNOC_SNOC] =3D &slv_pcnoc_snoc, +}; + +static const struct regmap_config msm8937_pcnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x13080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8937_pcnoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8937_pcnoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8937_pcnoc_nodes), + .bus_clk_desc =3D &bus_0_clk, + .qos_offset =3D 0x7000, + .keep_alive =3D true, + .regmap_cfg =3D &msm8937_pcnoc_regmap_config, +}; + +static struct qcom_icc_node *msm8937_snoc_nodes[] =3D { + [MAS_QDSS_BAM] =3D &mas_qdss_bam, + [MAS_BIMC_SNOC] =3D &mas_bimc_snoc, + [MAS_PCNOC_SNOC] =3D &mas_pcnoc_snoc, + [MAS_QDSS_ETR] =3D &mas_qdss_etr, + [QDSS_INT] =3D &qdss_int, + [SNOC_INT_0] =3D &snoc_int_0, + [SNOC_INT_1] =3D &snoc_int_1, + [SNOC_INT_2] =3D &snoc_int_2, + [SLV_KPSS_AHB] =3D &slv_kpss_ahb, + [SLV_WCSS] =3D &slv_wcss, + [SLV_SNOC_BIMC_1] =3D &slv_snoc_bimc_1, + [SLV_IMEM] =3D &slv_imem, + [SLV_SNOC_PCNOC] =3D &slv_snoc_pcnoc, + [SLV_QDSS_STM] =3D &slv_qdss_stm, + [SLV_CATS_1] =3D &slv_cats_1, + [SLV_LPASS] =3D &slv_lpass, +}; + +static const struct regmap_config msm8937_snoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8937_snoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8937_snoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8937_snoc_nodes), + .bus_clk_desc =3D &bus_1_clk, + .regmap_cfg =3D &msm8937_snoc_regmap_config, + .qos_offset =3D 0x7000, +}; + +static struct qcom_icc_node *msm8937_snoc_mm_nodes[] =3D { + [MAS_JPEG] =3D &mas_jpeg, + [MAS_MDP] =3D &mas_mdp, + [MAS_VENUS] =3D &mas_venus, + [MAS_VFE0] =3D &mas_vfe0, + [MAS_VFE1] =3D &mas_vfe1, + [MAS_CPP] =3D &mas_cpp, + [SLV_SNOC_BIMC_0] =3D &slv_snoc_bimc_0, + [SLV_SNOC_BIMC_2] =3D &slv_snoc_bimc_2, + [SLV_CATS_0] =3D &slv_cats_0, +}; + +static const struct qcom_icc_desc msm8937_snoc_mm =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8937_snoc_mm_nodes, + .num_nodes =3D ARRAY_SIZE(msm8937_snoc_mm_nodes), + .bus_clk_desc =3D &bus_2_clk, + .regmap_cfg =3D &msm8937_snoc_regmap_config, + .qos_offset =3D 0x7000, + .ab_coeff =3D 154, +}; + +static const struct of_device_id msm8937_noc_of_match[] =3D { + { .compatible =3D "qcom,msm8937-bimc", .data =3D &msm8937_bimc }, + { .compatible =3D "qcom,msm8937-pcnoc", .data =3D &msm8937_pcnoc }, + { .compatible =3D "qcom,msm8937-snoc", .data =3D &msm8937_snoc }, + { .compatible =3D "qcom,msm8937-snoc-mm", .data =3D &msm8937_snoc_mm }, + { } +}; +MODULE_DEVICE_TABLE(of, msm8937_noc_of_match); + +static struct platform_driver msm8937_noc_driver =3D { + .probe =3D qnoc_probe, + .remove_new =3D qnoc_remove, + .driver =3D { + .name =3D "qnoc-msm8937", + .of_match_table =3D msm8937_noc_of_match, + .sync_state =3D icc_sync_state, + }, +}; +module_platform_driver(msm8937_noc_driver); + +MODULE_DESCRIPTION("Qualcomm MSM8937 NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.45.1 From nobody Thu Feb 12 17:27:58 2026 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3719755C29; 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[83.30.46.83]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ebd5a63bf2sm6679841fa.33.2024.06.09.11.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 11:21:43 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] interconnect: qcom: qcs404: Introduce AP-owned nodes Date: Sun, 9 Jun 2024 20:20:58 +0200 Message-Id: <20240609182112.13032-6-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240609182112.13032-1-a39.skl@gmail.com> References: <20240609182112.13032-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When driver was first sent it seems ap_owned nodes were not available, bring them now. Signed-off-by: Adam Skladowski --- drivers/interconnect/qcom/qcs404.c | 85 ++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom= /qcs404.c index 11b49a89c03d..91b2ccc56a33 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -101,6 +101,11 @@ static struct qcom_icc_node mas_apps_proc =3D { .buswidth =3D 8, .mas_rpm_id =3D 0, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, .num_links =3D ARRAY_SIZE(mas_apps_proc_links), .links =3D mas_apps_proc_links, }; @@ -116,6 +121,11 @@ static struct qcom_icc_node mas_oxili =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 2, .num_links =3D ARRAY_SIZE(mas_oxili_links), .links =3D mas_oxili_links, }; @@ -131,6 +141,11 @@ static struct qcom_icc_node mas_mdp =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 1, + .qos.qos_port =3D 4, .num_links =3D ARRAY_SIZE(mas_mdp_links), .links =3D mas_mdp_links, }; @@ -145,6 +160,10 @@ static struct qcom_icc_node mas_snoc_bimc_1 =3D { .buswidth =3D 8, .mas_rpm_id =3D 76, .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, .num_links =3D ARRAY_SIZE(mas_snoc_bimc_1_links), .links =3D mas_snoc_bimc_1_links, }; @@ -160,6 +179,11 @@ static struct qcom_icc_node mas_tcu_0 =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 2, + .qos.qos_port =3D 6, .num_links =3D ARRAY_SIZE(mas_tcu_0_links), .links =3D mas_tcu_0_links, }; @@ -174,6 +198,8 @@ static struct qcom_icc_node mas_spdm =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, .num_links =3D ARRAY_SIZE(mas_spdm_links), .links =3D mas_spdm_links, }; @@ -231,6 +257,11 @@ static struct qcom_icc_node mas_crypto =3D { .buswidth =3D 8, .mas_rpm_id =3D 23, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 0, .num_links =3D ARRAY_SIZE(mas_crypto_links), .links =3D mas_crypto_links, }; @@ -287,6 +318,11 @@ static struct qcom_icc_node mas_qpic =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 14, .num_links =3D ARRAY_SIZE(mas_qpic_links), .links =3D mas_qpic_links, }; @@ -301,6 +337,11 @@ static struct qcom_icc_node mas_qdss_bam =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 1, .num_links =3D ARRAY_SIZE(mas_qdss_bam_links), .links =3D mas_qdss_bam_links, }; @@ -348,6 +389,11 @@ static struct qcom_icc_node mas_qdss_etr =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 0, .num_links =3D ARRAY_SIZE(mas_qdss_etr_links), .links =3D mas_qdss_etr_links, }; @@ -363,6 +409,11 @@ static struct qcom_icc_node mas_emac =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 17, .num_links =3D ARRAY_SIZE(mas_emac_links), .links =3D mas_emac_links, }; @@ -378,6 +429,11 @@ static struct qcom_icc_node mas_pcie =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 8, .num_links =3D ARRAY_SIZE(mas_pcie_links), .links =3D mas_pcie_links, }; @@ -393,6 +449,11 @@ static struct qcom_icc_node mas_usb3 =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 16, .num_links =3D ARRAY_SIZE(mas_usb3_links), .links =3D mas_usb3_links, }; @@ -491,6 +552,8 @@ static struct qcom_icc_node pcnoc_s_2 =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, .num_links =3D ARRAY_SIZE(pcnoc_s_2_links), .links =3D pcnoc_s_2_links, }; @@ -626,6 +689,8 @@ static struct qcom_icc_node qdss_int =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, .num_links =3D ARRAY_SIZE(qdss_int_links), .links =3D qdss_int_links, }; @@ -704,6 +769,8 @@ static struct qcom_icc_node slv_spdm =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_pdm =3D { @@ -752,6 +819,8 @@ static struct qcom_icc_node slv_disp_ss_cfg =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_gpu_cfg =3D { @@ -760,6 +829,8 @@ static struct qcom_icc_node slv_gpu_cfg =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_blsp_1 =3D { @@ -784,6 +855,8 @@ static struct qcom_icc_node slv_pcie =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_ethernet =3D { @@ -792,6 +865,8 @@ static struct qcom_icc_node slv_ethernet =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_blsp_2 =3D { @@ -816,6 +891,8 @@ static struct qcom_icc_node slv_tcu =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_pmic_arb =3D { @@ -894,6 +971,8 @@ static struct qcom_icc_node slv_kpss_ahb =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_wcss =3D { @@ -954,6 +1033,8 @@ static struct qcom_icc_node slv_cats_0 =3D { .buswidth =3D 16, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_cats_1 =3D { @@ -962,6 +1043,8 @@ static struct qcom_icc_node slv_cats_1 =3D { .buswidth =3D 8, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node slv_lpass =3D { @@ -970,6 +1053,8 @@ static struct qcom_icc_node slv_lpass =3D { .buswidth =3D 4, .mas_rpm_id =3D -1, .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, }; =20 static struct qcom_icc_node * const qcs404_bimc_nodes[] =3D { --=20 2.45.1 From nobody Thu Feb 12 17:27:58 2026 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C4A25C8FC; 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[83.30.46.83]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ebd5a63bf2sm6679841fa.33.2024.06.09.11.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 11:21:47 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] interconnect: qcom: qcs404: Add regmaps and more bus descriptions Date: Sun, 9 Jun 2024 20:20:59 +0200 Message-Id: <20240609182112.13032-7-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240609182112.13032-1-a39.skl@gmail.com> References: <20240609182112.13032-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently we are lacking descriptions of regmaps and buses, provide them. Signed-off-by: Adam Skladowski --- drivers/interconnect/qcom/qcs404.c | 41 +++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom= /qcs404.c index 91b2ccc56a33..f9b508a56588 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -1067,10 +1067,22 @@ static struct qcom_icc_node * const qcs404_bimc_nod= es[] =3D { [SLAVE_BIMC_SNOC] =3D &slv_bimc_snoc, }; =20 +static const struct regmap_config qcs404_bimc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x80000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs404_bimc =3D { - .bus_clk_desc =3D &bimc_clk, + .type =3D QCOM_ICC_BIMC, .nodes =3D qcs404_bimc_nodes, .num_nodes =3D ARRAY_SIZE(qcs404_bimc_nodes), + .bus_clk_desc =3D &bimc_clk, + .regmap_cfg =3D &qcs404_bimc_regmap_config, + .qos_offset =3D 0x8000, + .ab_coeff =3D 153, }; =20 static struct qcom_icc_node * const qcs404_pcnoc_nodes[] =3D { @@ -1122,10 +1134,22 @@ static struct qcom_icc_node * const qcs404_pcnoc_no= des[] =3D { [SLAVE_PCNOC_SNOC] =3D &slv_pcnoc_snoc, }; =20 +static const struct regmap_config qcs404_pcnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x15080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs404_pcnoc =3D { - .bus_clk_desc =3D &bus_0_clk, + .type =3D QCOM_ICC_NOC, .nodes =3D qcs404_pcnoc_nodes, .num_nodes =3D ARRAY_SIZE(qcs404_pcnoc_nodes), + .bus_clk_desc =3D &bus_0_clk, + .qos_offset =3D 0x7000, + .keep_alive =3D true, + .regmap_cfg =3D &qcs404_pcnoc_regmap_config, }; =20 static struct qcom_icc_node * const qcs404_snoc_nodes[] =3D { @@ -1151,10 +1175,21 @@ static struct qcom_icc_node * const qcs404_snoc_nod= es[] =3D { [SLAVE_LPASS] =3D &slv_lpass, }; =20 +static const struct regmap_config qcs404_snoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x23080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs404_snoc =3D { - .bus_clk_desc =3D &bus_1_clk, + .type =3D QCOM_ICC_NOC, .nodes =3D qcs404_snoc_nodes, .num_nodes =3D ARRAY_SIZE(qcs404_snoc_nodes), + .bus_clk_desc =3D &bus_1_clk, + .qos_offset =3D 0x11000, + .regmap_cfg =3D &qcs404_snoc_regmap_config, }; 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[83.30.46.83]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ebd5a63bf2sm6679841fa.33.2024.06.09.11.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 11:21:50 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] dt-bindings: interconnect: qcom: msm8939: Fix example Date: Sun, 9 Jun 2024 20:21:00 +0200 Message-Id: <20240609182112.13032-8-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240609182112.13032-1-a39.skl@gmail.com> References: <20240609182112.13032-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For now example list snoc_mm as children of bimc which is obviously not valid, change example and include rest of nocs in it. Fixes: 462baaf4c628 ("dt-bindings: interconnect: qcom: Fix and separate out= MSM8939") Signed-off-by: Adam Skladowski --- .../bindings/interconnect/qcom,msm8939.yaml | 22 ++++++++++++------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8939.ya= ml b/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml index fd15ab5014fb..a77e6aa2fbee 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml @@ -56,19 +56,25 @@ examples: - | #include =20 - snoc: interconnect@580000 { - compatible =3D "qcom,msm8939-snoc"; - reg =3D <0x00580000 0x14000>; - #interconnect-cells =3D <1>; - }; - bimc: interconnect@400000 { compatible =3D "qcom,msm8939-bimc"; reg =3D <0x00400000 0x62000>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; + }; + + pcnoc: interconnect@500000 { + compatible =3D "qcom,msm8939-pcnoc"; + reg =3D <0x00500000 0x11000>; + #interconnect-cells =3D <2>; + }; + + snoc: interconnect@580000 { + compatible =3D "qcom,msm8939-snoc"; + reg =3D <0x00580000 0x14080>; + #interconnect-cells =3D <2>; =20 snoc_mm: interconnect-snoc { compatible =3D "qcom,msm8939-snoc-mm"; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; }; }; --=20 2.45.1