From nobody Thu Feb 12 19:03:38 2026 Received: from mail-il1-f182.google.com (mail-il1-f182.google.com [209.85.166.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E882208B8; Sun, 9 Jun 2024 10:07:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717927663; cv=none; b=OeilEZe/ZJK4CdY1hS1Ivj2Ck5R3UQ2UZA6CrhcZhz08R2lKHg4S21Qcjv2kvRpMlMji5BBR6FcoWiJ2T4hkgDufIe+z0BviR57CHuRkVss2DlxBA1SYTFlSYRcq7zlwJBtBuSMqKOiCTZiByaWoL6LDd2wOKaCVzCLHgI2LFkU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717927663; c=relaxed/simple; bh=EOys2I62KZ1akQipaN9xi0V4ioOFDVDNkKMRki62SFc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gppB1FIwxFvdfAyrcUe9eRBdKRgEFkJmNLicYzSZ8CFuqM3nDGx/bQPbJaEGdStinCZYUyxIkPlRc+ct8eRCliHgztoY2M8zxQOYWJNRvNG9P1L1X2zjnoOzHpZvp7Nyha34QZwHrHmnWYQMGcEL4qbVJOCWo9n+6oBW8RNS1tY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IGfcpLlO; arc=none smtp.client-ip=209.85.166.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IGfcpLlO" Received: by mail-il1-f182.google.com with SMTP id e9e14a558f8ab-3737b47c0acso14404345ab.3; Sun, 09 Jun 2024 03:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717927661; x=1718532461; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nrGcPYJMJhishfsKRnQ7kYXDZI93Ds4JWA94AUqTVuU=; b=IGfcpLlOYORqrWAGT4ae7AdMjRttf33ZGZZy2/zPr7GunCP5MSidJAxO7990GCAErB 6fNqfdMrDSDcZwVCfmFQFdWJvMX3YosNpP+aHb/ho9SHd22EnBFKEoKwiveaJbBW+MRC R98EfR2tXPTUuYxGJADWXlOFNfnOfEaT/C+oplRnauWKGvwfYPLY66EvWLIINZJIepGf JYbxU5MS2QbqBHnlVej4CIuxO2i3hDKnpvrP3GXzAfYKdfETrwbXHyJWtbVlWVX7jQvs W458k6x3XXb+uvfpZgptFAkPfJJp2yjgtx7RXAJP9+ZS3dNxXZ9f2/YlSFJwUetWRWmq GbiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717927661; x=1718532461; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nrGcPYJMJhishfsKRnQ7kYXDZI93Ds4JWA94AUqTVuU=; b=TphEFqlEJrXkGjQgFl9MHyqo2+kk8bhqrz8QvYvSScx20hMa2G1f02MBABMXQlKwa8 msQL2FCZQw/CgVY0Bb1GKtdWvSwYYoOgtDYeKj820KSQFufhZ6QZGdsIVsIwd6pnFtLs euXnkEMGhvck9odDLRG9Ipz4XNHR4P585YO5lS8HfnpYrNOJPjE4UenHVQNfshu0XXcL +t8pzCdEH/uGzlcoKIXI0lF5pXMoR8pViauYDPtqJYbY4++qwg/V8yk8+4+pG8iDEkG+ VK9pkjVzsysRwxVfTr51iteTORI47/c09khZtvkmRI1EcpzzASw+jlvDkiASpbtkebHr NDxQ== X-Forwarded-Encrypted: i=1; AJvYcCUEqHgd/sRUpvgT5QIVylVse2NwFR7OgHJaOW8yGddGcJYGBN7kcJZxvVQFPoxsDpRzU9iidJ8zpDQ9wgoYgyLvXuitaUbf62pIFPkmmXTNvABcNwYI8NPOOb7Dn5+OMyPSF/4Wd+4CLQ== X-Gm-Message-State: AOJu0Yz7fXeS/Plai5zUQyLYmnXGkYqYVEwfZkyeAcRqayIy6ChscWk0 kyjhw47SH0jX3ClkwnlGONKeWWTcaRUfCozaZ1sJt8rpG1Kop29K X-Google-Smtp-Source: AGHT+IGhnopr1rEFpd+oheUq9TRm3b8JotiKAk1cnMv/x3wNf4V5aQMge/e1RjDVzYdr1u+tylWzLA== X-Received: by 2002:a05:6e02:1c8d:b0:374:593f:9158 with SMTP id e9e14a558f8ab-37580375a71mr70344885ab.20.1717927661378; Sun, 09 Jun 2024 03:07:41 -0700 (PDT) Received: from ga401ii.. ([2401:4900:1cc9:92b2:ce0f:ca96:5cb0:62e5]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-7041c78ac20sm2817534b3a.154.2024.06.09.03.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 03:07:40 -0700 (PDT) From: Kanak Shilledar To: Cc: kanakshilledar111@protonmail.com, Kanak Shilledar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v4 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema Date: Sun, 9 Jun 2024 15:37:07 +0530 Message-ID: <20240609100710.85055-2-kanakshilledar@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240609100710.85055-1-kanakshilledar@gmail.com> References: <20240609100710.85055-1-kanakshilledar@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the RISC-V Hart-Level Interrupt Controller (HLIC) to newer DT schema, Created DT schema based on the .txt file which had `compatible`, `#interrupt-cells` and `interrupt-controller` as required properties. Changes made with respect to original file: - Changed the example to just use interrupt-controller instead of using the whole cpu block - Changed the example compatible string. Reviewed-by: Conor Dooley Signed-off-by: Kanak Shilledar --- Changes in v4: - Change DCO email to @gmail.com Changes in v3: - Remove reference to `interrupt-controller` in `riscv/cpus.yaml`. Changes in v2: - Update the maintainers list. - Add reference to `interrupt-controller` in `riscv/cpus.yaml`. - Update compatible property with the reference in `cpus.yaml`. - Include description for '#interrupt-cells' property. - Change '#interrupt-cells' property to have `const: 1` as per the text binding. - Fixed the warning thrown by `/renesas/r9a07g043f01-smarc.dtb`. --- .../interrupt-controller/riscv,cpu-intc.txt | 52 ------------- .../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++ 2 files changed, 73 insertions(+), 52 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,cpu-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,cpu-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,c= pu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,= cpu-intc.txt deleted file mode 100644 index 265b223cd978..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc= .txt +++ /dev/null @@ -1,52 +0,0 @@ -RISC-V Hart-Level Interrupt Controller (HLIC) ---------------------------------------------- - -RISC-V cores include Control Status Registers (CSRs) which are local to ea= ch -CPU core (HART in RISC-V terminology) and can be read or written by softwa= re. -Some of these CSRs are used to control local interrupts connected to the c= ore. -Every interrupt is ultimately routed through a hart's HLIC before it -interrupts that hart. - -The RISC-V supervisor ISA manual specifies three interrupt sources that are -attached to every HLIC: software interrupts, the timer interrupt, and exte= rnal -interrupts. Software interrupts are used to send IPIs between cores. The -timer interrupt comes from an architecturally mandated real-time timer tha= t is -controlled via Supervisor Binary Interface (SBI) calls and CSR reads. Ext= ernal -interrupts connect all other device interrupts to the HLIC, which are rout= ed -via the platform-level interrupt controller (PLIC). - -All RISC-V systems that conform to the supervisor ISA specification are -required to have a HLIC with these three interrupt sources present. Since= the -interrupt map is defined by the ISA it's not listed in the HLIC's device t= ree -entry, though external interrupt controllers (like the PLIC, for example) = will -need to define how their interrupts map to the relevant HLICs. This means -a PLIC interrupt property will typically list the HLICs for all present HA= RTs -in the system. - -Required properties: -- compatible : "riscv,cpu-intc" -- #interrupt-cells : should be <1>. The interrupt sources are defined by = the - RISC-V supervisor ISA manual, with only the following three interrupts b= eing - defined for supervisor mode: - - Source 1 is the supervisor software interrupt, which can be sent by = an SBI - call and is reserved for use by software. - - Source 5 is the supervisor timer interrupt, which can be configured = by - SBI calls and implements a one-shot timer. - - Source 9 is the supervisor external interrupt, which chains to all o= ther - device interrupts. -- interrupt-controller : Identifies the node as an interrupt controller - -Furthermore, this interrupt-controller MUST be embedded inside the cpu -definition of the hart whose CSRs control these local interrupts. - -An example device tree entry for a HLIC is show below. - - cpu1: cpu@1 { - compatible =3D "riscv"; - ... - cpu1-intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; - interrupt-controller; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,c= pu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv= ,cpu-intc.yaml new file mode 100644 index 000000000000..83256cc0bd5c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc= .yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Hart-Level Interrupt Controller (HLIC) + +description: + RISC-V cores include Control Status Registers (CSRs) which are local to + each CPU core (HART in RISC-V terminology) and can be read or written by + software. Some of these CSRs are used to control local interrupts connec= ted + to the core. Every interrupt is ultimately routed through a hart's HLIC + before it interrupts that hart. + + The RISC-V supervisor ISA manual specifies three interrupt sources that = are + attached to every HLIC namely software interrupts, the timer interrupt, = and + external interrupts. Software interrupts are used to send IPIs between + cores. The timer interrupt comes from an architecturally mandated real- + time timer that is controlled via Supervisor Binary Interface (SBI) calls + and CSR reads. External interrupts connect all other device interrupts to + the HLIC, which are routed via the platform-level interrupt controller + (PLIC). + + All RISC-V systems that conform to the supervisor ISA specification are + required to have a HLIC with these three interrupt sources present. Sin= ce + the interrupt map is defined by the ISA it's not listed in the HLIC's de= vice + tree entry, though external interrupt controllers (like the PLIC, for + example) will need to define how their interrupts map to the relevant HL= ICs. + This means a PLIC interrupt property will typically list the HLICs for a= ll + present HARTs in the system. + +maintainers: + - Palmer Dabbelt + - Paul Walmsley + +properties: + compatible: + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: | + The interrupt sources are defined by the RISC-V supervisor ISA manua= l, + with only the following three interrupts being defined for + supervisor mode: + - Source 1 is the supervisor software interrupt, which can be sent= by + an SBI call and is reserved for use by software. + - Source 5 is the supervisor timer interrupt, which can be configu= red + by SBI calls and implements a one-shot timer. + - Source 9 is the supervisor external interrupt, which chains to a= ll + other device interrupts. + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + +additionalProperties: false + +examples: + - | + interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; --=20 2.45.2 From nobody Thu Feb 12 19:03:38 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C29B3208B8; Sun, 9 Jun 2024 10:07:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717927671; cv=none; b=fy6IIpNi29whcJWJmhO2qNnOc+ITT1Yl/OfzW4tyRh/k9slHeRLeFIVIwO74bb+06ZlakjOk9R9cel9IJptfv1tTjBf3y9toxlHmyFZRILCT++Xg/zTOFC0ElArLnZzxmyVZAiZPDkV7eBCNDBuW6uOvlav8ggWwoFHY46RbOfY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717927671; c=relaxed/simple; bh=fW4OnfxSC1huAXibwjVO49aWwP6kwWsg9vuNq1cMjKM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CdExNxX0IINNgTJOwu5scRRkWqQNtWwLSGVT1l5BGN40MBTcaSxoloEJBLWbki+h3GZXaPalcN4yT/xwNPurlHbORxB+5XtkjBdsd/3DagIKZkWuTnAUEKJ2rSLQyMlY+m+KSSBkdi6SYhF+Vq/c+F+PQq6C70VJHWeQSjNKdUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eyRiM9Qg; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eyRiM9Qg" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-702555eb23bso2760959b3a.1; Sun, 09 Jun 2024 03:07:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717927669; x=1718532469; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A8cWoOmqxKfRTYz+fqWWX+hQL/rBm7CI/FqFLj5thyk=; b=eyRiM9QgEKR26YuAmj3xzurUVNHs8Na2y8ifSanf0IOXHiq+oyKb22aQFUIxx6Pj16 GOZM01jjOzQKepQ4wbLNZwBg7dWvu8KtLJcSSQ9/OWhZWkcsG5cnbLgCU56ItjE5oF5q Rz4XGv9EMwaC4necoJP08Eh419g5SRE4Yn3aDBe3MbUOgnOe5qR1CfEhe3Ko4gq8jPTN Fx72gZM+nbO7Q6znZSaJw06tJX9L09wuGuKeCPmIHz3luAjy290po8QzgQtc+gP3ghZz L6OGgDENjCFOHbGO4zINTAm/uU1h/Z9z8e3kya2wnahcCwrvTFnsT5NkK97+RorgKTXP cXjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717927669; x=1718532469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A8cWoOmqxKfRTYz+fqWWX+hQL/rBm7CI/FqFLj5thyk=; b=pe82yjEAQirhILVet0f755DyRkOTxz8SdbLmeAee/bqLmyCuoUk9nWzSgH7H10k41B s7U3q+vfEcRdYnIXXFB0cDRKCervgzG5PejIJUG95+9XAydk6/rbjR7fph76IYd3LDtq 2wrt2p5Fl+7C5hWCrFL4gdzzbvQGdmn1meytvvSC2fw7VOZUOtHpSMLcdzgJyTnXgEWu s0LVr28gT9ZjUtFHS0ybgJmghAKi1VxFag0rE2cqJsjSD3dbGPJDe/PpsOB4vbaq/TEg SMtyEWHcfmjrCrPzJgl7VmNvICl42AIX8Z6hZtgAaXRQVc9qwMtTdueo2/aQsjwkP6hz 7bBg== X-Forwarded-Encrypted: i=1; AJvYcCUoAQmwpl5FKEyg8EHk4wQnbDI2g+5OgzvrdT9cKLXHz3l/l1kshTUyhxdhseyH5Flun3NZam/MxoJVLotkqAw7N/CaWkqh+vBjgR7W+G59qFWpaDM0+H0+2ACzxeILAy8AjG1xLfK51w== X-Gm-Message-State: AOJu0Yxua7lgkitUvJTtQIHCsRl6Azf4OKo9NdMpUFgw5Mx/4Mw4bL9X usarjjZG2RbjUjVFFcm27kFP+0fBboAFX0e1fKe9y+iNkSwXR8Zn X-Google-Smtp-Source: AGHT+IGUOwdS4rXbpKPl2f/O6CYkYK6yfhL3sIsZMAuc7WIZ8+BQleh6SCurcGAE85uB/kTJeBCzGQ== X-Received: by 2002:a05:6a20:7487:b0:1af:fa18:76f7 with SMTP id adf61e73a8af0-1b2f9dc2e94mr7273875637.39.1717927668863; Sun, 09 Jun 2024 03:07:48 -0700 (PDT) Received: from ga401ii.. ([2401:4900:1cc9:92b2:ce0f:ca96:5cb0:62e5]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-7041c78ac20sm2817534b3a.154.2024.06.09.03.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 03:07:48 -0700 (PDT) From: Kanak Shilledar To: Cc: kanakshilledar111@protonmail.com, Kanak Shilledar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v4 2/2] dt-bindings: riscv: cpus: add ref to interrupt-controller Date: Sun, 9 Jun 2024 15:37:08 +0530 Message-ID: <20240609100710.85055-3-kanakshilledar@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240609100710.85055-1-kanakshilledar@gmail.com> References: <20240609100710.85055-1-kanakshilledar@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" removed the redundant properties for interrupt-controller and provide reference to the riscv,cpu-intc.yaml which defines the interrupt-controller. making the properties for riscv interrupt-controller at a central place. Reviewed-by: Conor Dooley Signed-off-by: Kanak Shilledar --- Changes in v4: - Change DCO email to @gmail.com Changes in v3: - No change. - Rolling out as RESEND. Changes in v2: - Fix warning of `type` is a required property during `make dt_bindings_check`. --- .../devicetree/bindings/riscv/cpus.yaml | 21 +------------------ 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..f1241e5e8753 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -102,26 +102,7 @@ properties: =20 interrupt-controller: type: object - additionalProperties: false - description: Describes the CPU's local interrupt controller - - properties: - '#interrupt-cells': - const: 1 - - compatible: - oneOf: - - items: - - const: andestech,cpu-intc - - const: riscv,cpu-intc - - const: riscv,cpu-intc - - interrupt-controller: true - - required: - - '#interrupt-cells' - - compatible - - interrupt-controller + $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# =20 cpu-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array --=20 2.45.2