From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3B07AD58 for ; Mon, 10 Jun 2024 04:45:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994739; cv=none; b=MvWFYWpQg9PIRe2wpUwoMfVBW0xnpl0nHwGQ2YQQW8Hm4C7dxwG+MvReNO4FZe1ldfIxWaOkSiiRaDSJrFT9owNnZsoxF1zz9g2xLj2+a8ImgR4PynHZFwdlij+fLTy9cOu475arUlSGyUfflidwAjuVw6QxoUqywJVfyo0UyWs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994739; c=relaxed/simple; bh=BFeF/rMqjmAL/T3qO395y21tghoeF4vuGyaBxCV02tk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A6SOYe2mizWuO73M5LjfmfWwBMhv59FUmdTmhSvpeIurGM5mS/Ov/7oRuJxH+6pJp/+k3xz0SGYqrVqHOLla+v8oQ1T3145qpEDCi0FhOjMNO/Lavly+QnIWcEHso9eVwu/0lR/JyQfV4yKGPFrKuqzs982p6J6Kg7qHxG9KtcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=yO2MlF9C; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="yO2MlF9C" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-6e54287a719so1467935a12.1 for ; Sun, 09 Jun 2024 21:45:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994737; x=1718599537; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0gP3BTCO/eMabIcPEHZlkkrT/LBtjjbwR/exXvwDsR0=; b=yO2MlF9CVgV55C8zLc2mcExV9W4UOBCDf45GzbcMIFmcn/LndIaWn7JKQ50Xu1cWPS H1RWv0z0xkqaEVkmf7zUViEIYseL+NM+9pEqyuLHuRCtndnGiC5UxGjqp8SxNxSPIsp6 ELPODX4pZ06no0YnFaagI4IfZ+TQSWgCNUxORbEHqrhocFIbWbFeBqetx4bojNIVyk5+ hOdgVF73DeGbmOo/aHTNoJMoBvbUfd37I+NyCXypBoWEPjz+AGF3d6b874taJOEuN5g0 iSZqT5sP1hWkSf2bH+/EwRun28QeOG5+gdKXa3ePtDNkQXyVbSGNgZOaXY+jXXAjvGkz cerA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994737; x=1718599537; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0gP3BTCO/eMabIcPEHZlkkrT/LBtjjbwR/exXvwDsR0=; b=qUJXuPEHA4GtyqDF5gCt4OcJobGc9hMkeTjMzrPfBAZuxhkEA0UkY17gfPfym7lYKg hbq1ap8MGJDDKClInVHG/BRz0mOb9n/meKARQFTqRIjbtUW2+iRc3jH5XTxA/yB/Dczo vsYE9umtkv6JyC3vMVa9AAkCql7+EDugJg/n1EBvzTxD/nY0z2HSpJt0oW3qBohmSu7z yCQ7fQcwm+8KjWy1ftZmQBrkK8+jkjWc35Im3gYpVr0ODaaDEahC/tY5Ec0JbyDDQOrW XTLdfwVS7oKGdtBYiBJ+VKI57dcfGkMzLBEhYQEVRKHPvNVeo0Bx53x6te6AtEClTi2U ZxAg== X-Forwarded-Encrypted: i=1; AJvYcCXyLvkOXSXjzUDTp6XMnYxriGSaqe+lZafuOaa8p6ostbG26QQ3f87+arCt7ff72z68YFbb2KITmotMMt7vPMmVO3B3YVNrASWMkRUR X-Gm-Message-State: AOJu0YxD0eb1XUFkPgXBpz3gNbXGoOZqgba+UVYsM2gHbjZMBcECeKqW S4R9nGGwL0CEpUK2uDiltg9ZV0xEUqI9MjXhmaJ4EjRpbSAREphx7cJls6Gnw9c= X-Google-Smtp-Source: AGHT+IFWDInJoRdiv7yy4abVtD7rjRBD+5cj0P5U/4ieBFQEcEQDeMGkcWS+bxqhxTSZ6IUNdGy+uA== X-Received: by 2002:a05:6300:8088:b0:1af:3715:80c8 with SMTP id adf61e73a8af0-1b2f9c72398mr7890004637.46.1717994737211; Sun, 09 Jun 2024 21:45:37 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:36 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:06 -0700 Subject: [PATCH 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-1-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=1767; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=BFeF/rMqjmAL/T3qO395y21tghoeF4vuGyaBxCV02tk=; b=IOAoxXefLtnxcb9/gkClYMSBjiej8R99FUDNxVj9T92yij8sj0PIqkxukBdOvfHybExsRN5MX 8IFqt96IbAOBrlmGCI5VVCTbG5L+9+BjW8yNnuO22FIABU2PMBnuOK/ X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9= 489361c61d335e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..99d2a9e8c52d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -477,6 +477,10 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + # vendor extensions, each extension sorted alphanumerically under = the + # vendor they belong to. Vendors are sorted alphanumerically as we= ll. + + # Andes - const: xandespmu description: The Andes Technology performance monitor extension for counter= overflow @@ -484,5 +488,11 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf =20 + # T-HEAD + - const: xtheadvector + description: + The T-HEAD specific 0.7.1 vector implementation as written in + https://github.com/T-head-Semi/thead-extension-spec/blob/95358= cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. + additionalProperties: true ... --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03E3E11723 for ; Mon, 10 Jun 2024 04:45:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994741; cv=none; b=FWJIfLt3DDiCeCwJKGuuL9n4SMJjLufvXtRODXiX4cDx0tWe4jvwLHy3oeoLu2NKCa7YzxdKKD3bPPfCaJjhvLMqcRM/wT+nJoQDjl/vkBC3KVGmyEHYQas4p0mcx0fyhb1sfMUDriq94g0eb3sEN1kKCrQG4XI1+IvATVPWG20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994741; c=relaxed/simple; bh=kilTkVt6+s7AVwl0Le2KXls/6mRYwW97PnRFwTEsmd0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZPVquxn8/sjSr8Gf2GoeM4UVn+vTHuL583ZWnrTLaj/DZchJalzKwyRNbeo2KrEcGS4TKQh0xF5x+Lz+Ct0tIRq7qH5ZonwMfRN6ZBKx8B0xwFNoJ9zrvou3iRu9dFj24H4y3bR6sRdZYxvykGB6ZAORs7wZ69kz8tWD4/SRz7k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=wxn5caCs; arc=none smtp.client-ip=209.85.210.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="wxn5caCs" Received: by mail-pf1-f171.google.com with SMTP id d2e1a72fcca58-7042ee09f04so1079874b3a.0 for ; Sun, 09 Jun 2024 21:45:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994739; x=1718599539; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PnsoWpv70BH6qIUNn0TaawjhriEvRFbQJi7Pz4BWmlk=; b=wxn5caCsXC0vV09n0dBHjR4UfkxtlzU/kGayio/R1su7uFEk/HX3Iu3Qx26RI62lCf vXfs00y18NrU/M8wfXB6eOxjBq6suSglVwJRxxVFGRC1S63D+j4MFAMJrxVeHwFeIAl1 ElsNb2FBpV4tkfnaGdB0ivSwvJ3eXzAPgrl0klFK/B9HQbm5lkSOOtq37i8NSTH6vZcQ U5XTsbnkLkAJBZ7HZMV95APaVouicb0mhmkrKnwCwk9jJ2ktirW28m0q6ZNVv1HJJP9m LMNU7oXVLTeeQEeAN49GbE8zbatX69Idg8uCPnIYs0nYaiXskqRq6//fxMHhIQRPD0qV JgRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994739; x=1718599539; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PnsoWpv70BH6qIUNn0TaawjhriEvRFbQJi7Pz4BWmlk=; b=brzVgLiXH5JNlGPXoYQL8GU6CbrifOIx7eJZIQuV8qD10KV6jx5T0P2Lt06ZPcKajE pk1P/5N6Jxl2DzTaYGeaHdStZPcJLGXdzBbu2ekkPFS4GS2kYXFtjWa4AggkV0o+HRPd 2VK56FKR3Gbda1vb1LyYIMMLYtxrHPY42CWISNAaTfJAfBuR2mXVYz5v47iqrson03Yl UNa/DX0O97YfoF/3TMV7dsQoPVsCpLol5IqmJgDT27sk/dqnhFn3McDI4BedEK0dnujj toHKskfEOcdqNVJuBoiBTx5VnypA3pk2TYngnMqzP7DnG52zq5IJUpMSwdoWbweRZWo5 Aihg== X-Forwarded-Encrypted: i=1; AJvYcCXgr7FOKNNv4q+ksS3xYvIlXM5ZRq98K/IBz+xSX4OI1LTQhNyu1gCscIUu7vpzaVcVQemSxdYRQvM3Jf3vaQwPryFhCTPINdrMttGc X-Gm-Message-State: AOJu0YxhdtRmvzo21WiUEaDDT3cc2ay2de8de5kEhqJCXvwQ40fI3Hgr yzboKFUC7saFeq2zICoXhqs5qDHw3rM7sKm1B+t/enGqJFLMeqcIaejMohqw9Fw= X-Google-Smtp-Source: AGHT+IGAB+vWm0sGCNa81cmJyCujrQf8On8Y+GxMGYRiKcexYZGA6hr44N3kBkh31p7uFMVCcWAQvA== X-Received: by 2002:a05:6a20:3c88:b0:1b6:4151:6158 with SMTP id adf61e73a8af0-1b641516226mr4498267637.47.1717994739324; Sun, 09 Jun 2024 21:45:39 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:38 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:07 -0700 Subject: [PATCH 02/13] dt-bindings: thead: add a vlen register length property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-2-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=1303; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=kilTkVt6+s7AVwl0Le2KXls/6mRYwW97PnRFwTEsmd0=; b=4RRz7xmpcb7CA1ZMWQZlS9J8l2HdlB2OzfAfqDm1wbd8Q0dPdolWk/sqmZ90bsZ3IlYTtYYew po+8/cap559D5Bi2X+IDlt6JHWqySfqydxCXpaM/iRpkxwpTP5F3ksW X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, reading the th.vlenb CSR may produce an illegal instruction trap, so this property is required on such systems. Signed-off-by: Charlie Jenkins --- Documentation/devicetree/bindings/riscv/thead.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documenta= tion/devicetree/bindings/riscv/thead.yaml index 301912dcd290..5e578df36ac5 100644 --- a/Documentation/devicetree/bindings/riscv/thead.yaml +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -28,6 +28,13 @@ properties: - const: sipeed,lichee-module-4a - const: thead,th1520 =20 +thead,vlenb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + VLEN/8, the vector register length in bytes. This property is required= in + systems where the vector register length is not identical on all harts= , or + the vlenb CSR is not available. + additionalProperties: true =20 ... --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A68817BAA for ; Mon, 10 Jun 2024 04:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994743; cv=none; b=NXihnOSzpyeXjzYCB2CoYIU7psxv9bIqYl/7Bx5ctMcx0+zbKIMQ1RGVJJ1y14G57KYkxNMS+yXvtHY3mTpIi/VNBXt0To0ROFy6fEBflCevaRtE58tdAD8Mz6j6cIYKZs6VCT8UIQanbk3PyHMLwkOcn1kOS63zeqOND9iClPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994743; c=relaxed/simple; bh=eg5f+2eUdPorsjTg1AXnvbZp1Gz8QKwXU/sn4bArQ/o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mFyg15RioV0drJKzFhnk3j1bDP295kVgvYi0V7GaBU+JN5ji6eFstL9jpzfvVk82sL6tuzneJATS5i5qVw1EtfDEkv9RWS895ww4E1RuJ80bZ3DbBFXY8ZTJUFfNkqDkuxvnxcM9B4O6c48Ec36Lb4XDoo+nuDSMrsdlmuDEtR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=mPWIPv5M; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="mPWIPv5M" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-7043102dcc1so990935b3a.2 for ; Sun, 09 Jun 2024 21:45:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994741; x=1718599541; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Xb9tww82u8GPwb/D9ZGp2c9YRfA1MZ53TtnEydxWwQE=; b=mPWIPv5MH8Ifz8Z8RiCAcsrujOg/6fzKNI/Af82cqBDnni5WNc06z1CVaTbTClKZjg G74uPW40vl4ZANDEibynMdnNg2PCCR2NlSSbT/LG2bsEyDesZwOaorsaf8bUON5dlXOQ 7nkEKkEopqXyM5FtUGHqfW/9cT0g/vUBMuOqWXYitAetPbo0y13MHP3i3HkkxPbtFVaZ 9ZMu/genyOkAq8lPe3g+wfMTs/MT2fpWIiZMyyUDKO2ASBLz9m/IkNRFv6J3Wfb6yGEE eOjOPFnN8mWQm/3BqxQ1JZQ4Yv9Qp9YVDo44sX4ARR3/clWosq7lXYoxjXt6dK8ntVs3 6NnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994741; x=1718599541; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xb9tww82u8GPwb/D9ZGp2c9YRfA1MZ53TtnEydxWwQE=; b=cFO3MIfuvvowtjU+96bVdFhMVQjcxChNQD/qCrdVtr/o6zwB0wJqjjPMrxiE2hkymx 3h5GueEA8k++CRYxeeHJrY/0iaKdqXDNG1JuPqKiWRqWKt8b4BQ/5iEdBwvrv+AGJx+S YlwWyzQoAKXw0tr/CNRgaK3wBFbj/4bh1iFc+HvyUbFL17/ClFvfg8gAPV+ra1jIP6kl fVp3sgX276nhlgzXEgSp1VFL8zl8U3kK4jOvTmY+DrVWZAAwC46xLAYDwwYCn1cb940d m4Te2MWZNtnkMVf80vSzhcTJr+OOlmY3FmdJCM/+/vkbyM5ui3IDBaRBviRN0wgHRGI6 Mgpw== X-Forwarded-Encrypted: i=1; AJvYcCVUOCh9y+Z0vbOqjeKxCjAZZuRG7GjjZgD4DnBykUrn7F8+fIxyHTbEzCBr1EvnadxVyP4xVIROq/yV75y/mJuKhTz8LZRWXEfDl+AQ X-Gm-Message-State: AOJu0YyGlsShRXSd/akNe4ELD4JCR45lVD1TWLGjiZFg4EPxtDpEBdfF CeVue99qhpM2rRQg1HqFjLH6PtJlv0D7G4NPY3bAi0RmH1YKVcL7GB5Rh2IrBKg= X-Google-Smtp-Source: AGHT+IHfXz/eqcApvPQDnA4xGEwd2uFPXgoMy/TBwiOmRs/TV62bMg4pq81xPe0jQyHMWsO+kgdruQ== X-Received: by 2002:a05:6a20:3d81:b0:1b7:77ef:b125 with SMTP id adf61e73a8af0-1b777efc43amr2187647637.21.1717994741443; Sun, 09 Jun 2024 21:45:41 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:40 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:08 -0700 Subject: [PATCH 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-3-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=904; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=eg5f+2eUdPorsjTg1AXnvbZp1Gz8QKwXU/sn4bArQ/o=; b=qMU9GEMHv/svOPJ5zghxy0bhqG/AbgzxOZ0AfXJrmBOvTNW3UuMX841ytI7NfGDiJh0BQgx9K BRhD0FN3VpWCnzzynK4/FI3j/f0VwYqtduoZBXh2eanJAoZrFHFaZvg X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boo= t/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..50c9f4ec8a7f 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,8 @@ cpu0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadvector"; + riscv,vlenb =3D <128>; #cooling-cells =3D <2>; =20 cpu0_intc: interrupt-controller { --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3195A1C694 for ; Mon, 10 Jun 2024 04:45:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994745; cv=none; b=dMY9QsvK7gEYRElgrOicqhCiSjtBBLnuXC0RyZ/UdZMkNAZpgpQTkiMJS3Wkwc7rEf22wqZ5qn7ahvzOantuOfXhf70R955OwpajVUzCkuLy0Yaro8KZwuQDZVQibko31oBNz//n7rwlx2ZcD/mbwgEoN5Ohms525UGH1X7+T3Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994745; c=relaxed/simple; bh=Be9GFskCPaOhLa/vnEPQwyxN6jle/+xWeXOMsnFs0uY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=svldQ4bSp/XM0MXqm5GnKJZQN99dcqw3BtcnZYkOPWNj150+kJacWEhRXFbbMCfhwxZo0eTcxi2VWaKmeHDtnIAYkazH/o/CAB9JdPuEUHYkj+eyuppQc9aB/CPkqhtrpe9UrgreWknqFn0Fl00JQ9Dl9mAehWvB0umS4WZeq1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=M+uPt7vf; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="M+uPt7vf" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1f6f1677b26so8866935ad.0 for ; Sun, 09 Jun 2024 21:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994743; x=1718599543; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bt/OPDG5ozolIGkzcJWAUq0hvCz2HvO0aGCtSKiuUJE=; b=M+uPt7vfqyVlGb1n2WPLgWSOadfeyu9e4XzbVgDvwJgCoE5q9gKvG8BPfNMo13/+s/ Eqp2lM0aqENduJMeIyxP7SVPQTP5Zj9m9WRp98pBSFTN/WkCcA3y8a/uh+XlizvcLsUM DWH06n46Mf1x9IxKqoonLDGFe70zm8VnAxcv8ahugKTfWF7MalNZLpSg0TcU5qBU6LUy GigUcPjAvpmVM7Bu+GsSVjeV4ly90lQZDpV+QWhh0dMeEIPKFxPidgmopP301EG/6qzF ifs4WZu97XXX1osp0UleBFY5ajdEEbXyfK2vuec8tfE9JhMegJ9rTSrokRQBqvdA+GGy SWUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994743; x=1718599543; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bt/OPDG5ozolIGkzcJWAUq0hvCz2HvO0aGCtSKiuUJE=; b=uRYzKFUr3d0xKfkBsTmx712t2q4U8QOlWUFw0q5zIQZd2aDQuNwWKmHTjT64Fu7KAY Qe3o6KxYrVTUQbQ1qRiw9R0YBfa2PgS4x0PpJTJMR0Y2z0q7pAUcFIf1wEc0ZFoQ6NS4 0iIazc9b5PTjT1m0MRj4Dkl/uzTs92SyfjK0A45O8w9AA8dBdnFvFXQgJMyNDZQSC3AX 86nfbMQTIYSyI4MprnvzMy4wZdA+jW+ZOmFa4TXMQuzHA1dp6U95txMJTOWDftjtyJs4 YdSAUNEV+TOyF1onxnrFxdIxOI91oaeTQwVuwWSlXqtFfwuz6sQu49X84nSmz9ZgvRMC OvhQ== X-Forwarded-Encrypted: i=1; AJvYcCVnewN2gsCKmzYZfibR4SL9jHs7tsjhDtD4hqquqiuh46NSkI9W67DRCPh7Eb/3viyHAt0airVMEhn9bHjUEnfUC2KP5V9+Ufmifvwo X-Gm-Message-State: AOJu0YzubE7RLhEYSk6c/T16d7t0nO0CbkiFaBwsIfGILfwsdX/kfC5D J+7FncsIXLKqWYoeAJVHK8VdjR4DlhKWZjDsaO2Fa7WoaKPer49g/t8Xgx7HiHw= X-Google-Smtp-Source: AGHT+IFH0fEFn05oJUO43atBFKX0JjFk1xBhIihjWq6hCe7/KgueMlD/SusqXY/llSlmf2+T6tnShA== X-Received: by 2002:a17:903:2444:b0:1f2:fe12:b7be with SMTP id d9443c01a7336-1f6b8f1c342mr174009835ad.32.1717994743536; Sun, 09 Jun 2024 21:45:43 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:42 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:09 -0700 Subject: [PATCH 04/13] riscv: Add thead and xtheadvector as a vendor extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-4-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=4997; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=Be9GFskCPaOhLa/vnEPQwyxN6jle/+xWeXOMsnFs0uY=; b=mbzwm8EukXWWDz6wv6ztY1IDvgb2VXzMgEVGb5A9fHOy+U+h4tTF63h034I5z0jaG+9yErwwt vq3iXh7htG3D40mNmInAP0Pl5djxcFil2xteOUkUvuMiAvjABAek3yM X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.vendor | 13 +++++++++++++ arch/riscv/include/asm/vendor_extensions/thead.h | 16 ++++++++++++++++ arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/thead.c | 18 ++++++++++++++++++ 6 files changed, 59 insertions(+) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 6f1cdd32ed29..9897442bd44f 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -16,4 +16,17 @@ config RISCV_ISA_VENDOR_EXT_ANDES If you don't know what to do here, say Y. endmenu =20 +menu "T-Head" +config RISCV_ISA_VENDOR_EXT_THEAD + bool "T-Head vendor extension support" + select RISCV_ISA_VENDOR_EXT + default y + help + Say N here to disable detection of and support for all T-Head vendor + extensions. Without this option enabled, T-Head vendor extensions will + not be detected at boot and their presence not reported to userspace. + + If you don't know what to do here, say Y. +endmenu + endmenu diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/= include/asm/vendor_extensions/thead.h new file mode 100644 index 000000000000..48421d1553ad --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H + +#include + +#include + +/* + * Extension keys must be strictly less than RISCV_ISA_VENDOR_EXT_MAX. + */ +#define RISCV_ISA_VENDOR_EXT_XTHEADVECTOR 0 + +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_the= ad; + +#endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f2c24820700b..2107c59575dd 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #define NUM_ALPHA_EXTS ('z' - 'a' + 1) =20 diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vend= or_extensions.c index b6c1e7b5d34b..662ba64a8f93 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -6,6 +6,7 @@ #include #include #include +#include =20 #include #include @@ -14,6 +15,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_e= xt_list[] =3D { #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES &riscv_isa_vendor_ext_list_andes, #endif +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + &riscv_isa_vendor_ext_list_thead, +#endif }; =20 const size_t riscv_isa_vendor_ext_list_size =3D ARRAY_SIZE(riscv_isa_vendo= r_ext_list); @@ -41,6 +45,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, uns= igned long vendor, unsig cpu_bmap =3D &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu]; break; #endif + #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + case THEAD_VENDOR_ID: + bmap =3D &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap; + cpu_bmap =3D &riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu]; + break; + #endif default: return false; } diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index 6a61aed944f1..353522cb3bf0 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o diff --git a/arch/riscv/kernel/vendor_extensions/thead.c b/arch/riscv/kerne= l/vendor_extensions/thead.c new file mode 100644 index 000000000000..0934a2086473 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +/* All T-Head vendor extensions supported in Linux */ +const struct riscv_isa_ext_data riscv_isa_vendor_ext_thead[] =3D { + __RISCV_ISA_EXT_DATA(xtheadvector, RISCV_ISA_VENDOR_EXT_XTHEADVECTOR), +}; + +struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead =3D { + .ext_data_count =3D ARRAY_SIZE(riscv_isa_vendor_ext_thead), + .ext_data =3D riscv_isa_vendor_ext_thead, +}; --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 494231CAB1 for ; Mon, 10 Jun 2024 04:45:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994747; cv=none; b=X0pKPaZYiltAfcLv15F+YaY6RMZbl8n44wmmlJhFRAideE0jtedOZZdqHQBRV3MRYuGlO4uTjDDi7k/D0Co47P5G9hQXjI52oIACRI+PTedn8uedsJ5CE3Sw4OHhpSalk+D5C0E4DtP16/bVl6YwWFzaot/zUFcGRnM/hDA1QAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994747; c=relaxed/simple; bh=4N9WDp7GVC3puitkjGgcI/jJcnDMobkD3Avh+NXutPg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eI9MsFnPSNmc32mK3Dt+kWtCQK5Jos8jP4Hn0oe5SD0fZF+ECd0xP6n6Lvari0/3jctOaCJ8nJsyoRxmcuG4yN20vCXxIqd3ywURWAUaLuNHP/qOfpEtM2DuE9WXlG3SDDwNSghxfZ8Tf+wI5Imm0iMJFI45pQ5JL/hkQ0KwNGs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=TM9WCAxf; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="TM9WCAxf" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-1f70509b811so5671145ad.1 for ; Sun, 09 Jun 2024 21:45:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994745; x=1718599545; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=u6wty7/5ckkbIMYQrfSGTFo0XViwtxD1A330OlnyF00=; b=TM9WCAxfF3ohl01G5f1tSimYewxZVyhAzXr0wgadDovzYAmUOoP6RMhT250+liHDAG MNAQHzZ+jqVzKDo3ndqtSWl4UMghFFKZhSS9WLvTBRooUZPfDjnzpyGHuxTur399p0RB EnLfNY/NK2L6Bsce14MFXcC2mctmpl3AZO9kKnNwyGax9hdfA6Zc12eqe+vq2XTj+rmU H7IqZAiTsi/tdSPUWY1Itn3+GnM/x7/Kh0FGa3w/7kt2X4pMFsivIupMoSAPMCsapSOe Uf48jpAFJl+OAiK9m/xxM3zz3Pju51RFo/TefVPFFE9iv359wkquc+aqkFIT1EZtRaZW +ngg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994745; x=1718599545; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u6wty7/5ckkbIMYQrfSGTFo0XViwtxD1A330OlnyF00=; b=vbRHTTCL8zd7iYUBV5rBzkIhG0opqvZsSEAhyNTsdJSBNy53CNN8MNoAsoXadvrpOn cP6GJezXPk4sc6xgkDihi02uZg3CUol+LhAdi7moYiC4LrWRklNKvdyZYp5/X9c1MEZR ExTCDD/q7LC5AeChMz3Yj0cKK8tAyUnxMqmYGy6D2FGVpkcM8z4yqzqgNzBwV7cMTamY CVz/XPsO4ZzQcgvfcVDU3hXGLZpDhvkmcEKAf+CA+UtdGZykRS1i4PP5jeTDmE54TphW TybNhkAFOt8II+bQDTvG335lr1PR5lNocRfK2XMKh6cXDZDoTqdKAFdQ4WHlVHFK8Shv Fl3A== X-Forwarded-Encrypted: i=1; AJvYcCVK/fnnRza4W5j8XqP5mzHwHXs9+olH827+Q2y4JUEjlPjEqgBeUg49pmjbh25mypj8Zkcg3kInIUFJNWDSzTRVgxubVLtXqAVssNP1 X-Gm-Message-State: AOJu0YyxNmlVhxsZJqcToPHENzwnQWzpx+ftoxCzAqOKFycZnjwLg+Um VzVu4F2HfkUF5ytFyCmGsMbZey6jMG2h+/eVm3qXTvFE5LpG2LZV3DWeH64HxOc= X-Google-Smtp-Source: AGHT+IFf+1OJg1xK1MiXf0vBcz9BVHeA14Ul2s1z6qYt10MeOW0nvzzXkW/P4XRzr1D4aiRO1tRUzg== X-Received: by 2002:a17:902:e88d:b0:1f4:a3a1:a7e5 with SMTP id d9443c01a7336-1f6d02bef11mr85103415ad.13.1717994745696; Sun, 09 Jun 2024 21:45:45 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:44 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:10 -0700 Subject: [PATCH 05/13] riscv: vector: Use vlenb from DT for thead Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-5-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=3511; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=4N9WDp7GVC3puitkjGgcI/jJcnDMobkD3Avh+NXutPg=; b=DC7NLCqeukgT5lOVe137EsewYJ9o72ymXSCD9kejmdpQ1Vf7p2mH/l6TTZY1v6PLdnnpuqWvY zXH1O/+aMGsDnv7PW52FjUayRa3BK2sWdLtfhwVrfOaa4GCD21J2jf2 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/kernel/cpufeature.c | 48 +++++++++++++++++++++++++++++++++= ++++ arch/riscv/kernel/vector.c | 12 +++++++++- 3 files changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index b029ca72cebc..e0a3164c7a06 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 +extern u32 thead_vlenb_of; + void riscv_user_isa_enable(void); =20 #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) {= \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 2107c59575dd..0c01f33f2348 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __rea= d_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 +u32 thead_vlenb_of; + /** * riscv_isa_extension_base() - Get base extension word * @@ -625,6 +627,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu) } } =20 +static int has_thead_homogeneous_vlenb(void) +{ + int cpu; + u32 prev_vlenb =3D 0; + u32 vlenb; + + /* Ignore vlenb if vector is not enabled in the kernel */ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return 0; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node; + + cpu_node =3D of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + return -ENOENT; + } + + if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { + of_node_put(cpu_node); + + if (prev_vlenb) + return -ENOENT; + continue; + } + + if (prev_vlenb && vlenb !=3D prev_vlenb) { + of_node_put(cpu_node); + return -ENOENT; + } + + prev_vlenb =3D vlenb; + of_node_put(cpu_node); + } + + thead_vlenb_of =3D vlenb; + return 0; +} + static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) { unsigned int cpu; @@ -689,6 +731,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); } =20 + if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) && + has_thead_homogeneous_vlenb() < 0) { + pr_warn("Unsupported heterogeneous vlenb detected, vector extension disa= bled.\n"); + elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; + } + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) return -ENOENT; =20 diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 6727d1d3b8f2..3ba2f2432483 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) { unsigned long this_vsize; =20 - /* There are 32 vector registers with vlenb length. */ + /* + * There are 32 vector registers with vlenb length. + * + * If the thead,vlenb property was provided by the firmware, use that + * instead of probing the CSRs. + */ + if (thead_vlenb_of) { + this_vsize =3D thead_vlenb_of * 32; + return 0; + } + riscv_v_enable(); this_vsize =3D csr_read(CSR_VLENB) * 32; riscv_v_disable(); --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70AFB225CE for ; Mon, 10 Jun 2024 04:45:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994749; cv=none; b=D0+qkIS9nujxIqANa/SDKsPS6VXK7tBG1vxBnWFu+ttLJ7wkDPYKDXYEwymM7ZxHDDSrxUhh82jurxSjxI39MZLuGnX2dydsRUjl2oaWV2IArBUkvD+lRSwWpActIE/5PongNbd4iwPcQnfCs6Y+ADM5motb0RGGRittVV2tBgc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994749; c=relaxed/simple; bh=SMA++MELxtndsmlf2ltstvee/EM+yG8MF8KTMj9Ilaw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o8hLMcyqS1rT2heaFz+ouyx5f8+XpdxROSnoq2/s5pNHArQWTqxDuc5HYX/WUIcJDnxWGGNrwlU/yy7EVAizyANA45wORI6BkLcRuMjnOdciqq5Ucwc6tvK+WY2waMRw7e0q+9+ANolOQAbTmY4iKuEDMiXw9N7FcC15zU5IoRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Koj25E+/; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Koj25E+/" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-1f4a5344ec7so29188365ad.1 for ; Sun, 09 Jun 2024 21:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994748; x=1718599548; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=P240Gh/m4dWtpIWWlN8DjDnG2wL4gQcnQEBhQHOtafc=; b=Koj25E+/B50VWoWy3AwSYsiTNVlsXeDom2u/4XTUcQFirUnYLEyNZyjImfQbftc5M3 5dCtO2gkWWEkSOWLBmRi073Dp3x3V7cWfVJxceRX4X8OUSayYpPTf/LGH8Aor2EhHZmB etsBnsfaQub92DfFPdJfsLXVoOYC5CU1oXF8l0PAuxs4JtqDqs2d5Kpcf0iiRaPFYPoK VWEJJnICFeVJUknP1jHZq+LYN6GdcDbKH4qsAfAsrltr//TlxJwxoR4f0CgpdAmBJZXZ JVOXcGQkyJhcCYVyIAx7c2hw5RLpAW4wvXrrOaQtVETebR6Pn9r4iyMPR7McAr27kdUP vEpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994748; x=1718599548; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P240Gh/m4dWtpIWWlN8DjDnG2wL4gQcnQEBhQHOtafc=; b=pnEllmTY1FbaXukjbHyywaSUrDhkY7AqSJmTeQX1XwCHTdrhCob8Ww6KXZ11ZS6vdt 64UMM1FDA6zi0p8VIA/V5oEpl2mmx50d2YabUCiQF0wQQ5QzcZm9zFZ1Pb19r4WwVYKr S/90Imihxyqt/f+U+ERr32SCuMfRcZVAPHXA+6Wj4QY+dABNRHm5WQ1AkcN1Qf2TBBFk s5aA2Cu1SDbeXfc1P9uWnF/PNLFcxpKo63nOlrgyEdBkucLmh6+nGX0r0tO1XyiqsLkt FdT+O8Bng7ypbUOqFD5ZUjLoEczXjUyk59h0n8KY9v17eww0MUbP1sM8mtMbfnDK8Kia zSrw== X-Forwarded-Encrypted: i=1; AJvYcCX7H+s0dF/xV5bzB2XS6AdkWogBYOTfnRn4W318r37qOniq9J2Cb+UO43aP1v/kBFavxOQ3PX4sAsFEH6RDFrqIS2FEMBHvZbT/KhNF X-Gm-Message-State: AOJu0Yx+GEkaodaRiMSccln+xpIM++3AabRvd3X/7+bjppzsf7HTvDDv J5fLG1/7dDKwal7tEEGJg00sgOkoLKIjuqRTWJrmTvOMqHT79CGkPKzgFsBn850= X-Google-Smtp-Source: AGHT+IHHYkPAFs7Wybfe87tVbgyhX6m7aNDjY0QvnrXxzXLixuWmYwWBPXRWWuSdJ8YBrBa1EGWvsA== X-Received: by 2002:a17:902:db11:b0:1f3:7da:b0f5 with SMTP id d9443c01a7336-1f6d019efbfmr128910115ad.22.1717994747846; Sun, 09 Jun 2024 21:45:47 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:47 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:11 -0700 Subject: [PATCH 06/13] RISC-V: define the elements of the VCSR vector CSR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-6-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=954; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=rl/YEju2Da4Y30TCSeGgcBJQ4jtog67tmUBEGN9KrFw=; b=P25QoGbkxEpsQPOS3fSEe2wHlcp/4ddwgnPBsbhgltAUD65AsllR2lgWJ6YD0KH6hvNU90zge uLCtEb1QxJACMtDDLFk1aJU3wAfZckqIcjUQQVTLYFFInUydCNoG4cP X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..18e178d83401 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -216,6 +216,11 @@ #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) =20 +/* VCSR flags */ +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* symbolic CSR names: */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89826101CA for ; Mon, 10 Jun 2024 04:45:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994751; cv=none; b=lqoCUDUC60aEJ5Wg41a49u5+Kze+uVUJwd2AgxKevZNnZPSDc8ffx1i5hMLeAdCX122USNwF4fecS0r6R3Rp6VZuu+amYDb+YWyt1hzVxkC1iPWQ8ED1LFojTIA9qzwvsqbCv45UAdaq5g5by6ymYtqF0mGWnYzrSHx/lwOqdOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994751; c=relaxed/simple; bh=YRbwjAEMooOC1Wqfne0YGBAOlvdWm2exzND7IqGSDDM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U4RYYaSPYMNnj5Clj8KPMXiKplauXHQChktrXLKrdo+toTy/VBdc99pGVVJu/f4p9YG06PNwRCA+ZPsHRXauY9x9OInYdoImGdzOE8/VvnTuttRNCKnvrO7VfOcZYNT1bU3hyMwoUjx8qz981Kln1PgvRZ7vvc8BrI8S9hVKB50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=CwyKWGpa; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="CwyKWGpa" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1f7028196f2so6326735ad.2 for ; Sun, 09 Jun 2024 21:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994750; x=1718599550; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7HBSOfNpcERRo+IfFfSUzbZmQ8OANKCSab29OA8NgQg=; b=CwyKWGpaCevBq3LY6tPDvBUN6kbs1o2VRTRwceAAm9mvNClJqwMtBmtWZz0txBVJUd qLtmK5PTEDH21Wvapy8rZY+drGlU55GApyVOaik+F6FNoLdEGzEGsEEEQ2i01WOxxjaf h11qh1D+q5BzAKeHpuVi+3aJqgIXxKXv4F5INwKUP1bOr04PdG1n9ivVXn54Le0SfyHI Mrm9V4JnivwIo7+wjobPSRa/V9RaPi3w2UM1Bj89P1+8mu6TdvglKYTifomalRIcexIv ASAIg8QZdXIhqFngYcBo9uEXWs4uRz9jL3iG5h5Fm4yLU65sZhFYdClhOyGzHNXAnazV s5kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994750; x=1718599550; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7HBSOfNpcERRo+IfFfSUzbZmQ8OANKCSab29OA8NgQg=; b=XmWOgxHXkdpiby1q5VBUy7ASAaQWBo51LH5rAmUD0SoRzSCycBPurLVPw02S0xvrYN U9haDYG3sb7Og3WRQFsUvIj5CH5Z8hHCWD92GxP9jprrvt9z+2USpLXB8wh34cPqH6CU nUpIoYdZ0lpAVBHLBkomWUGqsGW4OSxse+HCGYklc7g6K+guB1/qKYbkX0bkJh3MuATw P3/KjIG1z8ht3vEToW5XHAF+hHCqKfahk5NGNSC/pWvfwsTykcH0EtanWCatvOTw0bLX O9M6m7WfK32TcVxvj1K3yBYy9NRXZKHlVGA1IAc6+UZU0GlFaZvHo2fizdAmfH9zd431 /D0w== X-Forwarded-Encrypted: i=1; AJvYcCVfjNcDQHNc1OzXiyoImtp9YPdYZNkWh3cPQFKZ4tTSjxDw4+u6l1lX7hFfxtnQJFhUsO/ROiqWsR7QAMLm/x+L+QXeDgPVc4Y2yDen X-Gm-Message-State: AOJu0Yz3VQsWrXXhq1RfL57oudroKc0oJwNKsz3GrtokgTBNjtXMft1b 5Erp55IccbtkvYMaO7CaMziiC4G9+PFs3sN3ya+XhwDoliCTMETPlWd82RTrcVU= X-Google-Smtp-Source: AGHT+IFokGlovp2IkNoCK67wcj7YPJ3AH98Sp2QxsCqsaBawuDAm3x3I7E9iE5QWcbZgk110G1+MgQ== X-Received: by 2002:a17:902:d4c3:b0:1f6:326b:cde0 with SMTP id d9443c01a7336-1f6d02f98ebmr107670705ad.31.1717994749999; Sun, 09 Jun 2024 21:45:49 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:49 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:12 -0700 Subject: [PATCH 07/13] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-7-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=706; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=YRbwjAEMooOC1Wqfne0YGBAOlvdWm2exzND7IqGSDDM=; b=99wn/niA0cQScW2RZHdAYs/G3d+6fucqbAlEziDCOsNFlslIJ1kTJdSJRonbVlLwckEyjZYSv oLpqsYahmVoCslt9Y6Si3QOPyFQR5kdwcQuHfdy3fJPz51XrWIzyAzd X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 18e178d83401..9086639a3dde 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -220,6 +220,8 @@ #define VCSR_VXRM_MASK 3 #define VCSR_VXRM_SHIFT 1 #define VCSR_VXSAT_MASK 1 +#define VCSR_VXSAT 0x9 +#define VCSR_VXRM 0xa =20 /* symbolic CSR names: */ #define CSR_CYCLE 0xc00 --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A78D63D57A for ; Mon, 10 Jun 2024 04:45:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994754; cv=none; b=SG17nFzgM5XIcbXiFSqptn//72q0bPhtFN/HyDH2B+1BRS0DYfWi2Nm2NrCrDV14JxmGq3wkVpmy89XuKBLNvscz27xDjdgGeJzyrIh7UI+YWNilUFNO1W8lGGc54y4jbWjlNoPP9Anp8qxFfqY2DlGYYmygK32wluRARkIpYlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994754; c=relaxed/simple; bh=fwxPC9e5acCJKXfvxD0QuLfngnuG8uQUjT/zUUS4iJ0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fmyPqxHqPLnWmwvfwNE8OQ3LztEvkPsLsxRz6cSKei9rYoIfrkDvWAxFONIWZ1vv1T2CxY1R6pt9ByGLFBXpmA+oD26flTmJFmfz/3kxQWrLA53iC9MzNznIqUQ+Liui/naDRKRwvf0Yfo/c7Q5NBEVusNpkjTNCyjKac5zDpMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=GbOhPy11; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="GbOhPy11" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1f61f775738so33489895ad.2 for ; Sun, 09 Jun 2024 21:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994752; x=1718599552; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XLBLJWgoI5ONq0p19OcZNiSMS9NNG1Jn9M7ZhOPyPpg=; b=GbOhPy11pStnMkVHjlgMummwUIfAQCvtYyeOOO58Jujx6+fh/xbpjWAYEw3fOnfUCl FtHYHNmU5OMDc7+L67OfL0P51mUylm2x4zJ0hHrtsg/9P39RzJhZ6ZOphXgGCiFbUaua IccJDhpZNi7E7LonJ4GDIEWLVizgDUE/HG/etsH4M5L0YW/uuxgirHMNlOmc9wKZs2YF yz/cZXgvvPs981uDCacbnxMSgGMEwiC2+6QtE1Wj3/OZOufTt/WBLwqlcsuKws/o2riO B5cHcTsaEM3vjPG5DU33mKwmFdGoHlu57li5JROHlCUDjbAuaNgsExP8SwPSNaqm1vfv 9vYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994752; x=1718599552; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XLBLJWgoI5ONq0p19OcZNiSMS9NNG1Jn9M7ZhOPyPpg=; b=L+5tQkSliS4A8cZ37vFI+ZrhHKltJPxKQgHJAbEpuUx/4ooZrzqM75w4U5iv19JFJP eda+POMtSdD7NPQEcBgYA9s/TGzZfkVDFITXZet+gzZOwmSSOjArMyQ2sazU+Pu/a7d5 BVIPZEj+/csBC7i0kXxrRZM+2BXd/HBb/rgFC8DgyrGK5GfxKHY9eZiO9bsFlSV+Ts3f mXL4FeoqKf9/wh6Gx/0+7zZe/VN+4PZGtqLXCVSDjdjop8Y/1GJ3NU32xxlLZOH2b2E5 kgDuIYer+W4NAnKVhk3L3h/Zmls7DMWEwpgHJRi66EFSIeu9o9e/XxMeWKv9a2xafdxA BMnA== X-Forwarded-Encrypted: i=1; AJvYcCU81oFF3dEm23BcVFCdbeNPLCRyOYeqW61cEXGbFM/d1XJdpKGOxpABYiUo1iQeyPmgyj3EJAuUDYJ8+z1P+GK80RU1yHuwZrhVUV+R X-Gm-Message-State: AOJu0YyJPPib/0tda1sinIhWf6OO1GkMgFfLvVdEpOAhho4aM3TDrnnj pY/jSyfR+qSbcYyYfy1UHQJS58rYXCtP0vEqOKvkIKQVgEUmyRlyMkWNtZbfLb8= X-Google-Smtp-Source: AGHT+IGhzNw67XowR+pxZXHezAitcTACLUYAiHb9cEpJzp2JsugT0jDK2XmWOKiIDx7qVYVsfrIJPA== X-Received: by 2002:a17:902:ccce:b0:1f4:9ce1:6e78 with SMTP id d9443c01a7336-1f6d02dda70mr108577415ad.19.1717994752097; Sun, 09 Jun 2024 21:45:52 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:51 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:13 -0700 Subject: [PATCH 08/13] riscv: Add xtheadvector instruction definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-8-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=1908; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=fwxPC9e5acCJKXfvxD0QuLfngnuG8uQUjT/zUUS4iJ0=; b=M+PUFY/NkfsExTsLVk8k8J14gBVKv6BFH2DHRNNQUnGVcMQ3tAUdofnki8To6aiLBdBSyd3l8 CwcONHmOkfXAJxo09mBCTw8CQBL707I5DEdUsNXqUeM68eA2H8/JeMP X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/vendor_extensions/thead.h | 26 ++++++++++++++++++++= ++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/= include/asm/vendor_extensions/thead.h index 48421d1553ad..27a253a20ab8 100644 --- a/arch/riscv/include/asm/vendor_extensions/thead.h +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -13,4 +13,30 @@ =20 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_the= ad; =20 +/* Extension specific helpers */ + +/* + * Vector 0.7.1 as used for example on T-Head Xuantie cores, uses an older + * encoding for vsetvli (ta, ma vs. d1), so provide an instruction for + * vsetvli t4, x0, e8, m8, d1 + */ +#define THEAD_VSETVLI_T4X0E8M8D1 ".long 0x00307ed7\n\t" +#define THEAD_VSETVLI_X0X0E8M8D1 ".long 0x00307057\n\t" + +/* + * While in theory, the vector-0.7.1 vsb.v and vlb.v result in the same + * encoding as the standard vse8.v and vle8.v, compilers seem to optimize + * the call resulting in a different encoding and then using a value for + * the "mop" field that is not part of vector-0.7.1 + * So encode specific variants for vstate_save and _restore. + */ +#define THEAD_VSB_V_V0T0 ".long 0x02028027\n\t" +#define THEAD_VSB_V_V8T0 ".long 0x02028427\n\t" +#define THEAD_VSB_V_V16T0 ".long 0x02028827\n\t" +#define THEAD_VSB_V_V24T0 ".long 0x02028c27\n\t" +#define THEAD_VLB_V_V0T0 ".long 0x012028007\n\t" +#define THEAD_VLB_V_V8T0 ".long 0x012028407\n\t" +#define THEAD_VLB_V_V16T0 ".long 0x012028807\n\t" +#define THEAD_VLB_V_V24T0 ".long 0x012028c07\n\t" + #endif --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2BC646BA0 for ; Mon, 10 Jun 2024 04:45:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994758; cv=none; b=t1N85EZy2JD3qXLuowBISZeMPm86a71/yahJAG9ZwEVIkAlNZGwteihbglmonLx9SibmhYMmi6yTeAkRzm1tFL5JrwJnqLN4OSE+Rwv0b1kIfsjL+dTaWEc4lBAHSX30b6EBuLLD/ZQjxZkZQa8sbiDXxfYnzyo113DQF+OvWuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994758; c=relaxed/simple; bh=Rs6W5kpbN29wRGdS7454FIXtNDO48Dzr6vkHau1WoC0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q4zyMzLuHhcSfUbeN9/yA8Oo+OXgYeHnG5fB7rTF0pV98uz9BYf9RzdfLqUshEYGlBs77pXmGwynLCOPd+L9Q2Eg5uEc5aCeBgSY+AijM4xbN68XnmFOtzT/O8VSJ+ryPNbQtgVrYpogZR/KyUAlDP39it7i3BURO3LHw9rygHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=km6sk4+V; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="km6sk4+V" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1f68834bfdfso29473495ad.3 for ; Sun, 09 Jun 2024 21:45:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994754; x=1718599554; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sKFKFqVc2ACxsO/4Dhld68bqZFrBrQIqygi0cCwkwA4=; b=km6sk4+V1eQS4Zdrd4848ebtpwH9ZLGGwkHEpNFrT7cEd7I3pa7UyZ2oBIEePDEl1g 5h99b6JwOn2LoSJXuxQU1s49l5kG84+ZK2g53pJ1cD/2bPPVEQvBWpFh0hCANkS+lAcL 3jWT91BJ/Ra7iQywZAXNW9NpaZTswraYCJ2+ZvKvJ15tUL3P6Ay/yhTzx1XeBAFJcGAO EoCL3ldyYIMcUVg8xkQiuoGLFPD01AwAp3VrEdRwC674Rl/jI+AjRbuoSQLxksdm2sxc dsMSQxnP2xikURNbjNLyAU3IYsuwkwlVfD42WFP3mv33tID8HBh4Ue/Q6pFJOq105aUb a6yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994754; x=1718599554; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sKFKFqVc2ACxsO/4Dhld68bqZFrBrQIqygi0cCwkwA4=; b=pOKCRubVWVd8Wx49dqWeKUYmbY1VLtP/1MLnXioUzA7dXI+4Ks1QHDXs04Gj63Ktxj 5PrS8k9x6te8MjOimTMr6vy6iQPSoIRN8dRHwPO6bXHd14yhoBjWHI6FArijhEe5juNr NNnC+VbewuLFeOD9V7eTCLNMK6aztlhLP7lFn7J8jLpSo/8CXMTcBT/IYD0F7cS0nzOl V+/2aOot9lD0cd9mMW7fBJ9G7lnYlx+Zlsz5DwuSRdtagH+0GEkfdFdizp5EYpShhEKI PfzFLdewu/NHH4AoeiOCjrWV4plEUtSZAQE97aC5+ZhkF6aWwkjrzq8jQfma8oDY7kld KNPA== X-Forwarded-Encrypted: i=1; AJvYcCWguXLuuErjXpALPokCQi+Fk3rFe/A4pLXjF2/BQYKIAb1XTVZP4FC4MkFMFRUNd0KZ+0aq/GS3xUT0M9HR6lrwaHt9+SuXkzHkgcPo X-Gm-Message-State: AOJu0Yz6uML17k5Qgx6NQ7chVUPVRL57uuC5J4fmajTdDcsev788+rPC t0oNC7sMmP/J0EIuev54+KBKI6+gSPXYMba8OdmTlMheAulxNgFrS9TdrGk4ELY= X-Google-Smtp-Source: AGHT+IFcFxYsNWpgCjMtyhD/72rc+oawDwaWTx9Tc8K0//cb/Hqbjc4lkZgqfJ2PTkAJqntApww/kg== X-Received: by 2002:a17:903:41cc:b0:1f7:19b7:98c6 with SMTP id d9443c01a7336-1f719b79c3bmr8798085ad.12.1717994754137; Sun, 09 Jun 2024 21:45:54 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:53 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:14 -0700 Subject: [PATCH 09/13] riscv: vector: Support xtheadvector save/restore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-9-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=19990; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=Rs6W5kpbN29wRGdS7454FIXtNDO48Dzr6vkHau1WoC0=; b=m43BN20l0YZoq+If1w71zkoktkYtz+D5rrGnyYgi+M8h7p6beCT5eFzoXmwVCog4X8FEwzcdC fSC18QG9zzjAR5jCXmaw6tgh0Cd9L0UHKj1lrI8jgwelc1/orCQdtge X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.vendor | 13 ++ arch/riscv/include/asm/csr.h | 6 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 249 ++++++++++++++++++++++++++---= ---- arch/riscv/kernel/cpufeature.c | 2 +- arch/riscv/kernel/kernel_mode_vector.c | 8 +- arch/riscv/kernel/process.c | 4 +- arch/riscv/kernel/signal.c | 6 +- arch/riscv/kernel/vector.c | 13 +- 9 files changed, 235 insertions(+), 68 deletions(-) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 9897442bd44f..5371d5567d90 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -26,6 +26,19 @@ config RISCV_ISA_VENDOR_EXT_THEAD extensions. Without this option enabled, T-Head vendor extensions will not be detected at boot and their presence not reported to userspace. =20 + If you don't know what to do here, say Y. + +config RISCV_ISA_XTHEADVECTOR + bool "xtheadvector extension support" + depends on RISCV_ISA_VENDOR_EXT_THEAD + depends on RISCV_ISA_V + depends on FPU + default y + help + Say N here if you want to disable all xtheadvector related procedure + in the kernel. This will disable vector for any T-Head board that + contains xtheadvector rather than the standard vector. + If you don't know what to do here, say Y. endmenu =20 diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 9086639a3dde..407d4a5687f5 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -30,6 +30,12 @@ #define SR_VS_CLEAN _AC(0x00000400, UL) #define SR_VS_DIRTY _AC(0x00000600, UL) =20 +#define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */ +#define SR_VS_OFF_THEAD _AC(0x00000000, UL) +#define SR_VS_INITIAL_THEAD _AC(0x00800000, UL) +#define SR_VS_CLEAN_THEAD _AC(0x01000000, UL) +#define SR_VS_DIRTY_THEAD _AC(0x01800000, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7594df37cc9f..f9cbebe372b8 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -99,7 +99,7 @@ do { \ __set_prev_cpu(__prev->thread); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ - if (has_vector()) \ + if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index 731dcd0ed4de..6294dcaabc6a 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -18,6 +18,27 @@ #include #include #include +#include +#include +#include + +#define __riscv_v_vstate_or(_val, TYPE) ({ \ + typeof(_val) _res =3D _val; \ + if (has_xtheadvector()) \ + _res =3D (_res & ~SR_VS_THEAD) | SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D (_res & ~SR_VS) | SR_VS_##TYPE; \ + _res; \ +}) + +#define __riscv_v_vstate_check(_val, TYPE) ({ \ + bool _res; \ + if (has_xtheadvector()) \ + _res =3D ((_val) & SR_VS_THEAD) =3D=3D SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D ((_val) & SR_VS) =3D=3D SR_VS_##TYPE; \ + _res; \ +}) =20 extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -40,39 +61,62 @@ static __always_inline bool has_vector(void) return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); } =20 +static __always_inline bool has_xtheadvector_no_alternatives(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTO= R); + else + return false; +} + +static __always_inline bool has_xtheadvector(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_has_vendor_extension_unlikely(THEAD_VENDOR_ID, + RISCV_ISA_VENDOR_EXT_XTHEADVECTOR); + else + return false; +} + static inline void __riscv_v_vstate_clean(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_CLEAN; + regs->status =3D __riscv_v_vstate_or(regs->status, CLEAN); } =20 static inline void __riscv_v_vstate_dirty(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_DIRTY; + regs->status =3D __riscv_v_vstate_or(regs->status, DIRTY); } =20 static inline void riscv_v_vstate_off(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_OFF; + regs->status =3D __riscv_v_vstate_or(regs->status, OFF); } =20 static inline void riscv_v_vstate_on(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_INITIAL; + regs->status =3D __riscv_v_vstate_or(regs->status, INITIAL); } =20 static inline bool riscv_v_vstate_query(struct pt_regs *regs) { - return (regs->status & SR_VS) !=3D 0; + return !__riscv_v_vstate_check(regs->status, OFF); } =20 static __always_inline void riscv_v_enable(void) { - csr_set(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_set(CSR_SSTATUS, SR_VS_THEAD); + else + csr_set(CSR_SSTATUS, SR_VS); } =20 static __always_inline void riscv_v_disable(void) { - csr_clear(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_clear(CSR_SSTATUS, SR_VS_THEAD); + else + csr_clear(CSR_SSTATUS, SR_VS); } =20 static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *= dest) @@ -81,10 +125,49 @@ static __always_inline void __vstate_csr_save(struct _= _riscv_v_ext_state *dest) "csrr %0, " __stringify(CSR_VSTART) "\n\t" "csrr %1, " __stringify(CSR_VTYPE) "\n\t" "csrr %2, " __stringify(CSR_VL) "\n\t" - "csrr %3, " __stringify(CSR_VCSR) "\n\t" - "csrr %4, " __stringify(CSR_VLENB) "\n\t" : "=3Dr" (dest->vstart), "=3Dr" (dest->vtype), "=3Dr" (dest->vl), - "=3Dr" (dest->vcsr), "=3Dr" (dest->vlenb) : :); + "=3Dr" (dest->vcsr) : :); + + if (has_xtheadvector()) { + u32 tmp_vcsr; + bool restore_fpu =3D false; + unsigned long status =3D csr_read(CSR_SSTATUS); + + /* + * CSR_VCSR is defined as + * [2:1] - vxrm[1:0] + * [0] - vxsat + * The earlier vector spec implemented by T-Head uses separate + * registers for the same bit-elements, so just combine those + * into the existing output field. + * + * Additionally T-Head cores need FS to be enabled when accessing + * the VXRM and VXSAT CSRs, otherwise ending in illegal instructions. + * Though the cores do not implement the VXRM and VXSAT fields in the + * FCSR CSR that vector-0.7.1 specifies. + */ + if ((status & SR_FS) =3D=3D SR_FS_OFF) { + csr_set(CSR_SSTATUS, (status & ~SR_FS) | SR_FS_CLEAN); + restore_fpu =3D true; + } + + asm volatile ( + "csrr %[tmp_vcsr], " __stringify(VCSR_VXRM) "\n\t" + "slliw %[vcsr], %[tmp_vcsr], " __stringify(VCSR_VXRM_SHIFT) "\n\t" + "csrr %[tmp_vcsr], " __stringify(VCSR_VXSAT) "\n\t" + "or %[vcsr], %[vcsr], %[tmp_vcsr]\n\t" + : [vcsr] "=3Dr" (dest->vcsr), [tmp_vcsr] "=3D&r" (tmp_vcsr)); + + dest->vlenb =3D riscv_v_vsize / 32; + + if (restore_fpu) + csr_set(CSR_SSTATUS, status); + } else { + asm volatile ( + "csrr %[vcsr], " __stringify(CSR_VCSR) "\n\t" + "csrr %[vlenb], " __stringify(CSR_VLENB) "\n\t" + : [vcsr] "=3Dr" (dest->vcsr), [vlenb] "=3Dr" (dest->vlenb)); + } } =20 static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_stat= e *src) @@ -95,9 +178,37 @@ static __always_inline void __vstate_csr_restore(struct= __riscv_v_ext_state *src "vsetvl x0, %2, %1\n\t" ".option pop\n\t" "csrw " __stringify(CSR_VSTART) ", %0\n\t" - "csrw " __stringify(CSR_VCSR) ", %3\n\t" - : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl), - "r" (src->vcsr) :); + : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl)); + + if (has_xtheadvector()) { + u32 tmp_vcsr; + bool restore_fpu =3D false; + unsigned long status =3D csr_read(CSR_SSTATUS); + + /* + * Similar to __vstate_csr_save above, restore values for the + * separate VXRM and VXSAT CSRs from the vcsr variable. + */ + if ((status & SR_FS) =3D=3D SR_FS_OFF) { + csr_set(CSR_SSTATUS, (status & ~SR_FS) | SR_FS_CLEAN); + restore_fpu =3D true; + } + + asm volatile ( + "srliw %[tmp_vcsr], %[vcsr], " __stringify(VCSR_VXRM_SHIFT) "\n\t" + "andi %[tmp_vcsr], %[tmp_vcsr], " __stringify(VCSR_VXRM_MASK) "\n\t" + "csrw " __stringify(VCSR_VXRM) ", %[tmp_vcsr]\n\t" + "andi %[tmp_vcsr], %[vcsr], " __stringify(VCSR_VXSAT_MASK) "\n\t" + "csrw " __stringify(VCSR_VXSAT) ", %[tmp_vcsr]\n\t" + : [tmp_vcsr] "=3D&r" (tmp_vcsr) : [vcsr] "r" (src->vcsr)); + + if (restore_fpu) + csr_set(CSR_SSTATUS, status); + } else { + asm volatile ( + "csrw " __stringify(CSR_VCSR) ", %[vcsr]\n\t" + : : [vcsr] "r" (src->vcsr)); + } } =20 static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_= to, @@ -107,19 +218,33 @@ static inline void __riscv_v_vstate_save(struct __ris= cv_v_ext_state *save_to, =20 riscv_v_enable(); __vstate_csr_save(save_to); - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vse8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vse8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } riscv_v_disable(); } =20 @@ -129,55 +254,77 @@ static inline void __riscv_v_vstate_restore(struct __= riscv_v_ext_state *restore_ unsigned long vl; =20 riscv_v_enable(); - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vle8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vle8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } __vstate_csr_restore(restore_from); riscv_v_disable(); } =20 static inline void __riscv_v_vstate_discard(void) { - unsigned long vl, vtype_inval =3D 1UL << (BITS_PER_LONG - 1); + unsigned long vtype_inval =3D 1UL << (BITS_PER_LONG - 1); =20 riscv_v_enable(); + if (has_xtheadvector()) + asm volatile (THEAD_VSETVLI_X0X0E8M8D1); + else + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e8, m8, ta, ma\n\t" + ".option pop\n\t"); + asm volatile ( ".option push\n\t" ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vmv.v.i v0, -1\n\t" "vmv.v.i v8, -1\n\t" "vmv.v.i v16, -1\n\t" "vmv.v.i v24, -1\n\t" - "vsetvl %0, x0, %1\n\t" + "vsetvl x0, x0, %0\n\t" ".option pop\n\t" - : "=3D&r" (vl) : "r" (vtype_inval) : "memory"); + : : "r" (vtype_inval)); + riscv_v_disable(); } =20 static inline void riscv_v_vstate_discard(struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_OFF) - return; - - __riscv_v_vstate_discard(); - __riscv_v_vstate_dirty(regs); + if (riscv_v_vstate_query(regs)) { + __riscv_v_vstate_discard(); + __riscv_v_vstate_dirty(regs); + } } =20 static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate, struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(regs->status, DIRTY)) { __riscv_v_vstate_save(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -186,7 +333,7 @@ static inline void riscv_v_vstate_save(struct __riscv_v= _ext_state *vstate, static inline void riscv_v_vstate_restore(struct __riscv_v_ext_state *vsta= te, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { __riscv_v_vstate_restore(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -195,7 +342,7 @@ static inline void riscv_v_vstate_restore(struct __risc= v_v_ext_state *vstate, static inline void riscv_v_vstate_set_restore(struct task_struct *task, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { set_tsk_thread_flag(task, TIF_RISCV_V_DEFER_RESTORE); riscv_v_vstate_on(regs); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0c01f33f2348..ed756b227b15 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -789,7 +789,7 @@ void __init riscv_fill_hwcap(void) elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; } =20 - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + if (elf_hwcap & COMPAT_HWCAP_ISA_V || has_xtheadvector_no_alternatives())= { riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/ker= nel_mode_vector.c index 6afe80c7f03a..99972a48e86b 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -143,7 +143,7 @@ static int riscv_v_start_kernel_context(bool *is_nested) =20 /* Transfer the ownership of V from user to kernel, then save */ riscv_v_start(RISCV_PREEMPT_V | RISCV_PREEMPT_V_DIRTY); - if ((task_pt_regs(current)->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(task_pt_regs(current)->status, DIRTY)) { uvstate =3D ¤t->thread.vstate; __riscv_v_vstate_save(uvstate, uvstate->datap); } @@ -160,7 +160,7 @@ asmlinkage void riscv_v_context_nesting_start(struct pt= _regs *regs) return; =20 depth =3D riscv_v_ctx_get_depth(); - if (depth =3D=3D 0 && (regs->status & SR_VS) =3D=3D SR_VS_DIRTY) + if (depth =3D=3D 0 && __riscv_v_vstate_check(regs->status, DIRTY)) riscv_preempt_v_set_dirty(); =20 riscv_v_ctx_depth_inc(); @@ -208,7 +208,7 @@ void kernel_vector_begin(void) { bool nested =3D false; =20 - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 BUG_ON(!may_use_simd()); @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin); */ void kernel_vector_end(void) { - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 riscv_v_disable(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e4bc61c4e58a..191023decd16 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -176,7 +176,7 @@ void flush_thread(void) void arch_release_task_struct(struct task_struct *tsk) { /* Free the vector context of datap. */ - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_free(tsk); } =20 @@ -222,7 +222,7 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) p->thread.s[0] =3D 0; } p->thread.riscv_v_flags =3D 0; - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_alloc(p); p->thread.ra =3D (unsigned long)ret_from_fork; p->thread.sp =3D (unsigned long)childregs; /* kernel sp */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 5a2edd7f027e..1d5e4b3ca9e1 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -189,7 +189,7 @@ static long restore_sigcontext(struct pt_regs *regs, =20 return 0; case RISCV_V_MAGIC: - if (!has_vector() || !riscv_v_vstate_query(regs) || + if (!(has_vector() || has_xtheadvector()) || !riscv_v_vstate_query(regs= ) || size !=3D riscv_v_sc_size) return -EINVAL; =20 @@ -211,7 +211,7 @@ static size_t get_rt_frame_size(bool cal_all) =20 frame_size =3D sizeof(*frame); =20 - if (has_vector()) { + if (has_vector() || has_xtheadvector()) { if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size +=3D riscv_v_sc_size; } @@ -284,7 +284,7 @@ static long setup_sigcontext(struct rt_sigframe __user = *frame, if (has_fpu()) err |=3D save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if (has_vector() && riscv_v_vstate_query(regs)) + if ((has_vector() || has_xtheadvector()) && riscv_v_vstate_query(regs)) err |=3D save_v_state(regs, (void __user **)&sc_ext_ptr); /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |=3D __put_user(0, &sc->sc_extdesc.reserved); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 3ba2f2432483..83126995f61a 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -63,7 +63,7 @@ int riscv_v_setup_vsize(void) =20 void __init riscv_v_setup_ctx_cache(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 riscv_v_user_cachep =3D kmem_cache_create_usercopy("riscv_vector_ctx", @@ -184,7 +184,8 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 insn =3D (u32)regs->badaddr; =20 /* Do not handle if V is not supported, or disabled */ - if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V)) + if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V) && + !(has_xtheadvector() && riscv_v_vstate_ctrl_user_allowed())) return false; =20 /* If V has been enabled then it is not the first-use trap */ @@ -223,7 +224,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 next =3D riscv_v_ctrl_get_next(tsk); @@ -245,7 +246,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) =20 long riscv_v_vstate_ctrl_get_current(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; @@ -256,7 +257,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) @@ -306,7 +307,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = =3D { =20 static int __init riscv_v_sysctl_init(void) { - if (has_vector()) + if (has_vector() || has_xtheadvector()) if (!register_sysctl("abi", riscv_v_default_vstate_table)) return -EINVAL; return 0; --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C93E4EB52 for ; Mon, 10 Jun 2024 04:45:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994758; cv=none; b=QhvXqPeMRR+cngUZnmXVHn3tZFCplhbOPLMDe4YG+1jDp7BU3y78glNKGESdA3X5s45SsILtu2wSST8zH0Yn4KhPiHMNusXxiQfQ71ZumCZZwQizj3eVcRnOGVh0J0QGjypWus0fbFY5wlLRDSC+Y+cc+3WNkBdJKKSEgfj4hhM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994758; c=relaxed/simple; bh=BUrC1FP1l+VlTkuyGPq1vdTGQN5JGzKyHjNsgNBeuVI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mn8jkkEcGmv5oB+1kjb0MsVC/QQjHYkbdLt+ssEJIBYJUD65QyliqdU8tfNVdmSpArucjPnS0HxPG+KQsBZGhE1eQpsUtOsRBEr3SbFH7bOXskHQO7BotNG5xRSO8hpokn2H7JyG64rlVCzkLOhjfghD3tiPxcYGUErWSWevwh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=QGaG5R99; arc=none smtp.client-ip=209.85.215.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="QGaG5R99" Received: by mail-pg1-f178.google.com with SMTP id 41be03b00d2f7-652fd0bb5e6so3500785a12.0 for ; Sun, 09 Jun 2024 21:45:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994756; x=1718599556; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ibOh5mhf2lDK2VgbBqycF5Y5tsRu24lzyWUxq1Ze1io=; b=QGaG5R99yMI7m2Sl4clDfmKMs/nzMlgqELbJM/HZj5lhydgdl6Eibj2sM8sa3vAtJq F0TLGVJ+z1uDuXynFWCly85jK2ONggBjWnWGmkAj8qEYTSbjKrcmNo2K2U+KrVq31hBu nZe4D4m6OmufFuauFIB5q6O+xymVGT+2sKX0AhE2JrKHqfxgm8Ou5rITNLhk4XIr5QDk SMuYpVdQMUXB8Woi5TZPD4KtE3IRLYSzYdBOUv6bHYODhyqd3EbJASrajCSiyC+zyLXE GNpLF/CfJPbuTwURsNIXeaRdL8jDsRFWpvVtLnTWnBGphZxBhCOgwhtAAp1/EIimrEDb OUpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994756; x=1718599556; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ibOh5mhf2lDK2VgbBqycF5Y5tsRu24lzyWUxq1Ze1io=; b=u/t1E6UFOfwPwnRkuYKz97WKilX8RJAREnQu0JmcKAOAc67J345FP5DzM6NbjBRt0g hfKlq9uz3iw14vcXq5aaO7S1trDGRmreVf9QLwUTYxc9kxly3AYZjIy7Hqa3jE2Y7nTU s5NgNv/xtPG9GOcfFYMx5b9JHjBd/Ts9IgUhbGGQ/6NHcVyRnqycwnDFB/hmB4ho4dZL u0TpahUfSHRUetJDYnkTWMyLO4SBflYAl1iqyc3YX18IxoUSOqoxN0tmOwJ5w3jifBx7 clcCzzG7XaU5lWvboZiR4K3zPW7TSyqi8FcuigSLTlgEfZjVULnSJJ2EsQLrtHNK+Ujx YrQA== X-Forwarded-Encrypted: i=1; AJvYcCW2OP8vtQe7kAdrpTSBmzPTQkxuiZHBghvtth1gs5PAj0AtOwwymbt03dJso2TZo6duVmTVbzMjADIST7uTdubY2PzeeBA5Rvqcjue7 X-Gm-Message-State: AOJu0Yw6kGNEFjDYV5ht4O1zw4knDZ5SY4g3IM/bb+SfGAgorfdb7y5R djfnjMA76eUQiQTlRf6jt6E3UIeMdmGIQ4AuoaLhePF43A3RN4GmxHa+NctnHQU= X-Google-Smtp-Source: AGHT+IFYiS0Xgre0TS1VgGGozSkukfN3TS+NLAwJh0YKAf0g0itcq8Gbu+ETiSnp/WBs/8H1UcS00Q== X-Received: by 2002:a05:6a20:5611:b0:1af:b1c0:c9eb with SMTP id adf61e73a8af0-1b2f9ca345fmr8199119637.45.1717994756262; Sun, 09 Jun 2024 21:45:56 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:55 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:15 -0700 Subject: [PATCH 10/13] riscv: hwprobe: Add thead vendor extension probing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-10-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=7283; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=BUrC1FP1l+VlTkuyGPq1vdTGQN5JGzKyHjNsgNBeuVI=; b=9AeRYOoE5uucxnbpp0YkhPhTVDvWr6CvfGZ+kz5AmCgv82yotrmqqFhtzoC0EgvJgeoS7t58m mMxcCighHXCCXInGmNZQ5y5q6VtbYphkZHQKzW9X8O1qezl58rlc6Ju X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit corresponding to a supported thead vendor extension of the cpumask set. Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program to determine all of the supported thead vendor extensions in one call. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- arch/riscv/include/asm/hwprobe.h | 4 +-- .../include/asm/vendor_extensions/thead_hwprobe.h | 18 +++++++++++ .../include/asm/vendor_extensions/vendor_hwprobe.h | 37 ++++++++++++++++++= ++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 +- arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ arch/riscv/kernel/sys_hwprobe.c | 5 +++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 19 +++++++++++ 8 files changed, 87 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 630507dff5ea..e68496b4f8de 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ =20 #ifndef _ASM_HWPROBE_H @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 6 +#define RISCV_HWPROBE_MAX_KEY 7 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arc= h/riscv/include/asm/vendor_extensions/thead_hwprobe.h new file mode 100644 index 000000000000..925fef39a2c0 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H + +#include + +#include + +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const stru= ct cpumask *cpus); +#else +static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pa= ir, const struct cpumask *cpus) +{ + pair->value =3D 0; +} +#endif + +#endif diff --git a/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h b/ar= ch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h new file mode 100644 index 000000000000..b6222e7b519e --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2024 Rivos, Inc + */ + +#ifndef _ASM_RISCV_SYS_HWPROBE_H +#define _ASM_RISCV_SYS_HWPROBE_H + +#include + +#define EXT_KEY(ext) \ + do { \ + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_#= #ext)) \ + pair->value |=3D RISCV_HWPROBE_VENDOR_EXT_##ext; \ + else \ + missing |=3D RISCV_HWPROBE_VENDOR_EXT_##ext; \ + } while (false) + +/* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + * + * _extension_checks is an arbitrary C block to set the values of pair->va= lue + * and missing. It should be filled with EXT_KEY expressions. + */ +#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_thead_bitmap, _ext= ension_checks) \ + do { \ + int cpu; \ + u64 missing; \ + for_each_cpu(cpu, (cpus)) { \ + struct riscv_isavendorinfo *isainfo =3D &(per_hart_thead_bitmap)[cpu]; \ + _extension_checks \ + } \ + (pair)->value &=3D ~missing; \ + } while (false) \ + +#endif /* _ASM_RISCV_SYS_HWPROBE_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index dda76a05420b..155a83dd1cdf 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ =20 #ifndef _UAPI_ASM_HWPROBE_H @@ -68,6 +68,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 7 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/includ= e/uapi/asm/vendor/thead.h new file mode 100644 index 000000000000..43790ebe5faf --- /dev/null +++ b/arch/riscv/include/uapi/asm/vendor/thead.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 969ef3d59dbe..e39fa70083d3 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -13,6 +13,7 @@ #include #include #include +#include #include =20 =20 @@ -217,6 +218,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, pair->value =3D riscv_cboz_block_size; break; =20 + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: + hwprobe_isa_vendor_ext_thead_0(pair, cpus); + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index 353522cb3bf0..866414c81a9f 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -2,3 +2,4 @@ =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead_hwprobe.o diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/ris= cv/kernel/vendor_extensions/thead_hwprobe.c new file mode 100644 index 000000000000..53f65942f7e8 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +#include +#include + +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const stru= ct cpumask *cpus) +{ + VENDOR_EXTENSION_SUPPORTED(pair, cpus, + riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { + EXT_KEY(XTHEADVECTOR); + }); +} --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E74AE125DE for ; Mon, 10 Jun 2024 04:45:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994761; cv=none; b=Gf+lVRz3MMR4hFsEdR437eb0J20DTld+L4TBONqO/lIKmqtVyp+DcaNLo9+QCpnOMeFtjU/gx9uq7xq2uuvM/DUKRrc7HrU3aOMSs6vGWnq7ydT+Al9qdFLo/zOwmt1qpdaQN1t/R5c8vTDiMhdjucn4MDXzLI/ATyO7sMeIt0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994761; c=relaxed/simple; bh=FGQxjkKFg6ikcL755lFMFBnsaceTJTK90HJM8u9R8ek=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XXnnqPLvqOia7c/Yg73oS9yv5vLs6BH0YiWObRNrtIOiJtBpLqkFhvEP/dpL9VnjWBKzf1+TbWlKMhf1vkxu/z+fKzUjl1PLgb5Nr0bATKVPM9HkgAJvXnAIoW/YgCas5lbB/o+PHMeUKOr6p0JHmfcyQm8RyRXw5yy11/Cm0Wg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=YRpstOBK; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="YRpstOBK" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1f6fabe9da3so9320775ad.0 for ; Sun, 09 Jun 2024 21:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994758; x=1718599558; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=r8BieCexzaDREgF6SB/4DhCje3SwtC4a6MLqQwsxjuQ=; b=YRpstOBKXymk5/TeGfpOOWM8pL1omzzI4J2gDfxCtEYUeuNNgFkwX3bk5MG5gdEzml friEdq3YXMe1z26wAwjfQnjFR8yF/nfI525zUl7a2VqOTULbPtHVd/zQ6lqzIhQ8oSJb uTRhtWZmz1QlMqkojw8aw2WifSmN/y9qa+gIc0LEcUHx73nG5h+yyqSpZiQ7rVyR29uv Cr2ZZFAgX/BMb6TZvmp1Cy2j+1cbJblFwG/1OAdHc9ucURBz/rVvM2JFlIA4biL4xoJ1 f1Rl9/lVqyDOcKu6uKsTb6m7qnGkhph6EPKqMXdH4dgCti5BMNL8QVMmuB/ql/moN+9y Vw7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994758; x=1718599558; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8BieCexzaDREgF6SB/4DhCje3SwtC4a6MLqQwsxjuQ=; b=vbfgo5DO7PYBt0u9QxkqVBT0sxo5nrKjyIxWGl8Ez4eQR6H8Qt6gdNFAZWv9q10XK2 L/Th6uirwRowIKtzig4hauxN9sVmcG67nkGyWFXxyorUxbQvYJF6aaERfneE5qIEGFfH taiAKYmi2W67kTjcxeJ/jkD9WYrNgLejp0w0xz+fsuRqTgZGef7eisOJfxvfdP0fEVKf ubIDGDInVvcl2pUMIrHuMbge+crsB7G3BC3PMGUxgaEeCLliMVV05nI201jD5okI8hw1 dGX0lclBo8kpuTaoLjA+KZAQZG6HgKE+dQXzgKzoW75z8RSC1cvao5hwvPLDpPndE3YG r8oA== X-Forwarded-Encrypted: i=1; AJvYcCXcKZD+eieCI47Sgzgh6LgMa21SwKXGHMuL2SxGaFKiVRwlU68KMQs8pn5qYB/HDoPsrsuii3ZLMwGwfLSMkjm1+o7xHCDDZdSheOGq X-Gm-Message-State: AOJu0YxalXbO0MD2EO91Y3Rbo55oIyFfWrO5ow5vL6kJoFMMQsbK74lu 4p4BotVUWyXdqcH2Y3gxRy9f++y8zmCHIx74CRFupw8dk1mz6tJ835Sg3tEBJjA= X-Google-Smtp-Source: AGHT+IGT317oosIG3JNia7Pc2PgndKpOONadquoO+w7t4F+iRdDjWNQNIYmD2UUADman72ew5imj1g== X-Received: by 2002:a17:902:e842:b0:1f7:1d78:db3f with SMTP id d9443c01a7336-1f71d78e31emr1364105ad.33.1717994758342; Sun, 09 Jun 2024 21:45:58 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:57 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:16 -0700 Subject: [PATCH 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-11-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=1250; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=FGQxjkKFg6ikcL755lFMFBnsaceTJTK90HJM8u9R8ek=; b=hOHF9McI+o1cU1DAmF1IXm7ZMdeqVzGBgk601RJJNOjyOk+/Oadw40msR5BmovQCOoTuHmcBF zkRQyUhxJRGCbqJNpLJekD/85gONlVrdLOUv5QHabXYSTiHWZC2HUUA X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Document support for thead vendor extensions using the key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 204cd4433af5..9c0ef8c57228 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -214,3 +214,13 @@ The following keys are defined: =20 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes. + +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the + thead vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * T-HEAD + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector v= endor + extension is supported in the T-Head ISA extensions spec starting = from + commit a18c801634 ("Add T-Head VECTOR vendor extension. "). --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 560D65644E for ; Mon, 10 Jun 2024 04:46:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994765; cv=none; b=D19MppAjLtFdHjLq5Uk0JlNogyxIkm+tCcYlzOKDGNBDTe6HwXb4LL2hgKofu4r06iLP5JlKRXymXk+87tXvHBczLoWAaldsMReQwL320f3QO/D04wYar42bXZ30dhg+mwvezwaVYGsuIeaJRoRUwG7+SwnmS2/i/4NriGhn30w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994765; c=relaxed/simple; bh=jzH/9y8d7HpBSeuVnCS+9H12uNYWluVUbxgd6rp+TH4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VukIO4yY9QqnmNculldrDaOpDK+x7PgRdFqQboTeapYaqp62S4wtaA3d0ISUyhk9aD/5yXv8MIWH39N4bPj8ay/x/ItrGoqp4HPJs0Vdl6C5gnkKCaeArMhiukpZbGSHEMqSbw0My2cMjjG1qknDIx6dBhqrPMaozK7UCB9WnyI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=EfJQMaYN; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="EfJQMaYN" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-1f65a3abd01so37303275ad.3 for ; Sun, 09 Jun 2024 21:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994761; x=1718599561; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=whnKjWwZlEAm2Tk1WNNpUsvcMFmVvQvxiY5eIxqDPb4=; b=EfJQMaYNKKplh25CHa4ibaGzjNGDUNBTs2bDT6V7s3OkAtkb5PZB4K5yp5/KSnSib1 xLiSvtxNkCF5/gdJCMm9+gBwRY27zGtl75fVTnp/A2XAvqsV8N5CgFuCc6hRb5mSjngo EA6Swe+osnI4aK7ptcHuJjSSRDnIB8t+/68O6QyeK9u0WWCNkJxxkLNoEZimFET+7qb5 8/BttApONZK79kmJ33zzkoRR4IPUw5X7Bv5cFuFVvfkIVCzJ8BbYsHtUFOi9yU6xiqQt sh8gD3SQTMKeWhYBAgHIYu/HtHbLitwHUjT6Wvb17HSXhy0HCO4ZS10tdTcGoYtFTJcc jb8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994761; x=1718599561; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=whnKjWwZlEAm2Tk1WNNpUsvcMFmVvQvxiY5eIxqDPb4=; b=AayvoYk8NemMT3VOkYXKjnartzVjeTStvNIOACr1L91Xh3Yl/XGTfF/VbtJ9q8rf8L SdfHRGE/n9Z2Zf2bXxjuecVcVzPnmP11oVeJOsbML54BVpzxS2reEX+8EQ0Vf/d6IVm7 EwDcto9kGlIumuoWmcMVkIvGJS49p0VbBFZEZYZw0WUaQePqr9hRLjeg07ufdeQEf0Pl Wrv3AgNH/c8hj5/VnJZ5wiZDVMEsVGQSEFqxDPwUoAPCpJz2vRSBsVsALZARGyeY5lrj tNKo79DB2UZzqFsu2zX5PRnq7NPAFn7G2zZNa94yJxEn7CkYPwG2n0kyIKe/Z2zGPxN/ qFTA== X-Forwarded-Encrypted: i=1; AJvYcCUo22NZsjoL/iB7pTG62o2Dlva9JCoinUL2Q2NMiT/Afkgu2edxssFiX3YVi7rmwiq8S8pcA+ljLnQgTDgi9lNaP5N3lBs69gywoycU X-Gm-Message-State: AOJu0YwdcA0n4gdwuFYM54BtQudvC9zLcfShPRVnzYlrpsvgX0KFBlNl 5zRN93s9+yyJLMFR3TGP71QEQIJ0BnbiZ2BC4Y0AOByXHH8TyiczUSKLDPDEOJY= X-Google-Smtp-Source: AGHT+IHXDgqXqPv2yVrZ2sueCm5hOUQMHkklAN1loW4QV4kcYpMPyrD4WUnP4zk7Rpr0ZGz80w8hSw== X-Received: by 2002:a17:902:db11:b0:1f5:e635:21e1 with SMTP id d9443c01a7336-1f6d02beac3mr120264235ad.9.1717994760602; Sun, 09 Jun 2024 21:46:00 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:45:59 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:17 -0700 Subject: [PATCH 12/13] selftests: riscv: Fix vector tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-12-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=19626; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=jzH/9y8d7HpBSeuVnCS+9H12uNYWluVUbxgd6rp+TH4=; b=nytS8OwkqKQ7xdxQ5gdYfPkdvWb3IbQFP8AgZ+3yPn33zpHVQYYsuGWojlohKEdo/6VOd2+xX Re35FhKrEoYAAE90M9v63Ji2LnQUhlt3aCzPlc6MzuKQ7sIbI0nDFtg X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases is vector is reported and properly report the test case as skipped otherwise. The v_initval_nolibc test was previously not checking if vector was supported and used a function (malloc) which invalidates the state of the vector registers. Signed-off-by: Charlie Jenkins --- tools/testing/selftests/riscv/vector/.gitignore | 3 +- tools/testing/selftests/riscv/vector/Makefile | 17 +- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 84 +++++++ tools/testing/selftests/riscv/vector/v_helpers.c | 56 +++++ tools/testing/selftests/riscv/vector/v_helpers.h | 5 + tools/testing/selftests/riscv/vector/v_initval.c | 16 ++ .../selftests/riscv/vector/v_initval_nolibc.c | 68 ------ .../testing/selftests/riscv/vector/vstate_prctl.c | 266 ++++++++++++-----= ---- 8 files changed, 324 insertions(+), 191 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/.gitignore b/tools/testin= g/selftests/riscv/vector/.gitignore index 9ae7964491d5..7d9c87cd0649 100644 --- a/tools/testing/selftests/riscv/vector/.gitignore +++ b/tools/testing/selftests/riscv/vector/.gitignore @@ -1,3 +1,4 @@ vstate_exec_nolibc vstate_prctl -v_initval_nolibc +v_initval +v_exec_initval_nolibc diff --git a/tools/testing/selftests/riscv/vector/Makefile b/tools/testing/= selftests/riscv/vector/Makefile index bfff0ff4f3be..995746359477 100644 --- a/tools/testing/selftests/riscv/vector/Makefile +++ b/tools/testing/selftests/riscv/vector/Makefile @@ -2,18 +2,27 @@ # Copyright (C) 2021 ARM Limited # Originally tools/testing/arm64/abi/Makefile =20 -TEST_GEN_PROGS :=3D vstate_prctl v_initval_nolibc -TEST_GEN_PROGS_EXTENDED :=3D vstate_exec_nolibc +TEST_GEN_PROGS :=3D v_initval vstate_prctl +TEST_GEN_PROGS_EXTENDED :=3D vstate_exec_nolibc v_exec_initval_nolibc sys_= hwprobe.o v_helpers.o =20 include ../../lib.mk =20 -$(OUTPUT)/vstate_prctl: vstate_prctl.c ../hwprobe/sys_hwprobe.S +$(OUTPUT)/sys_hwprobe.o: ../hwprobe/sys_hwprobe.S + $(CC) -static -c -o$@ $(CFLAGS) $^ + +$(OUTPUT)/v_helpers.o: v_helpers.c + $(CC) -static -c -o$@ $(CFLAGS) $^ + +$(OUTPUT)/vstate_prctl: vstate_prctl.c $(OUTPUT)/sys_hwprobe.o $(OUTPUT)/v= _helpers.o $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ =20 $(OUTPUT)/vstate_exec_nolibc: vstate_exec_nolibc.c $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc =20 -$(OUTPUT)/v_initval_nolibc: v_initval_nolibc.c +$(OUTPUT)/v_initval: v_initval.c $(OUTPUT)/sys_hwprobe.o $(OUTPUT)/v_helpe= rs.o + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ + +$(OUTPUT)/v_exec_initval_nolibc: v_exec_initval_nolibc.c $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc diff --git a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c b= /tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c new file mode 100644 index 000000000000..74b13806baf0 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Get values of vector registers as soon as the program starts to test if + * is properly cleaning the values before starting a new program. Vector + * registers are caller saved, so no function calls may happen before read= ing + * the values. To further ensure consistency, this file is compiled without + * libc and without auto-vectorization. + * + * To be "clean" all values must be either all ones or all zeroes. + */ + +#define __stringify_1(x...) #x +#define __stringify(x...) __stringify_1(x) + +int main(int argc, char **argv) +{ + char prev_value =3D 0, value; + unsigned long vl; + int first =3D 1; + + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" + ".option pop\n\t" + : [vl] "=3Dr" (vl) + ); + +#define CHECK_VECTOR_REGISTER(register) ({ \ + for (int i =3D 0; i < vl; i++) { \ + asm volatile ( \ + ".option push\n\t" \ + ".option arch, +v\n\t" \ + "vmv.x.s %0, " __stringify(register) "\n\t" \ + "vsrl.vi " __stringify(register) ", " __stringify(register) ", 8\n\t" \ + ".option pop\n\t" \ + : "=3Dr" (value)); \ + if (first) { \ + first =3D 0; \ + } else if (value !=3D prev_value || !(value =3D=3D 0x00 || value =3D=3D = 0xff)) { \ + printf("Register " __stringify(register) " values not clean! value: %u\= n", value); \ + exit(-1); \ + } \ + prev_value =3D value; \ + } \ +}) + + CHECK_VECTOR_REGISTER(v0); + CHECK_VECTOR_REGISTER(v1); + CHECK_VECTOR_REGISTER(v2); + CHECK_VECTOR_REGISTER(v3); + CHECK_VECTOR_REGISTER(v4); + CHECK_VECTOR_REGISTER(v5); + CHECK_VECTOR_REGISTER(v6); + CHECK_VECTOR_REGISTER(v7); + CHECK_VECTOR_REGISTER(v8); + CHECK_VECTOR_REGISTER(v9); + CHECK_VECTOR_REGISTER(v10); + CHECK_VECTOR_REGISTER(v11); + CHECK_VECTOR_REGISTER(v12); + CHECK_VECTOR_REGISTER(v13); + CHECK_VECTOR_REGISTER(v14); + CHECK_VECTOR_REGISTER(v15); + CHECK_VECTOR_REGISTER(v16); + CHECK_VECTOR_REGISTER(v17); + CHECK_VECTOR_REGISTER(v18); + CHECK_VECTOR_REGISTER(v19); + CHECK_VECTOR_REGISTER(v20); + CHECK_VECTOR_REGISTER(v21); + CHECK_VECTOR_REGISTER(v22); + CHECK_VECTOR_REGISTER(v23); + CHECK_VECTOR_REGISTER(v24); + CHECK_VECTOR_REGISTER(v25); + CHECK_VECTOR_REGISTER(v26); + CHECK_VECTOR_REGISTER(v27); + CHECK_VECTOR_REGISTER(v28); + CHECK_VECTOR_REGISTER(v29); + CHECK_VECTOR_REGISTER(v30); + CHECK_VECTOR_REGISTER(v31); + +#undef CHECK_VECTOR_REGISTER + + return 0; +} diff --git a/tools/testing/selftests/riscv/vector/v_helpers.c b/tools/testi= ng/selftests/riscv/vector/v_helpers.c new file mode 100644 index 000000000000..15c22318db72 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_helpers.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "../hwprobe/hwprobe.h" +#include +#include +#include +#include + +int is_vector_supported(void) +{ + struct riscv_hwprobe pair; + + pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; + riscv_hwprobe(&pair, 1, 0, NULL, 0); + return pair.value & RISCV_HWPROBE_IMA_V; +} + +int launch_test(char *next_program, int test_inherit) +{ + char *exec_argv[3], *exec_envp[1]; + int rc, pid, status; + + pid =3D fork(); + if (pid < 0) { + printf("fork failed %d", pid); + return -1; + } + + if (!pid) { + exec_argv[0] =3D next_program; + exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; + exec_argv[2] =3D NULL; + exec_envp[0] =3D NULL; + /* launch the program again to check inherit */ + rc =3D execve(next_program, exec_argv, exec_envp); + if (rc) { + perror("execve"); + printf("child execve failed %d\n", rc); + exit(-1); + } + } + + rc =3D waitpid(-1, &status, 0); + if (rc < 0) { + printf("waitpid failed\n"); + return -3; + } + + if ((WIFEXITED(status) && WEXITSTATUS(status) =3D=3D -1) || + WIFSIGNALED(status)) { + printf("child exited abnormally\n"); + return -4; + } + + return WEXITSTATUS(status); +} diff --git a/tools/testing/selftests/riscv/vector/v_helpers.h b/tools/testi= ng/selftests/riscv/vector/v_helpers.h new file mode 100644 index 000000000000..88719c4be496 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_helpers.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +int is_vector_supported(void); + +int launch_test(char *next_program, int test_inherit); diff --git a/tools/testing/selftests/riscv/vector/v_initval.c b/tools/testi= ng/selftests/riscv/vector/v_initval.c new file mode 100644 index 000000000000..f38b5797fa31 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/v_initval.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "../../kselftest_harness.h" +#include "v_helpers.h" + +#define NEXT_PROGRAM "./v_exec_initval_nolibc" + +TEST(v_initval) +{ + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0)); +} + +TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/vector/v_initval_nolibc.c b/tool= s/testing/selftests/riscv/vector/v_initval_nolibc.c deleted file mode 100644 index 1dd94197da30..000000000000 --- a/tools/testing/selftests/riscv/vector/v_initval_nolibc.c +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "../../kselftest.h" -#define MAX_VSIZE (8192 * 32) - -void dump(char *ptr, int size) -{ - int i =3D 0; - - for (i =3D 0; i < size; i++) { - if (i !=3D 0) { - if (i % 16 =3D=3D 0) - printf("\n"); - else if (i % 8 =3D=3D 0) - printf(" "); - } - printf("%02x ", ptr[i]); - } - printf("\n"); -} - -int main(void) -{ - int i; - unsigned long vl; - char *datap, *tmp; - - datap =3D malloc(MAX_VSIZE); - if (!datap) { - ksft_test_result_fail("fail to allocate memory for size =3D %d\n", MAX_V= SIZE); - exit(-1); - } - - tmp =3D datap; - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vse8.v v0, (%2)\n\t" - "add %1, %2, %0\n\t" - "vse8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl), "=3Dr" (tmp) : "r" (datap) : "memory"); - - ksft_print_msg("vl =3D %lu\n", vl); - - if (datap[0] !=3D 0x00 && datap[0] !=3D 0xff) { - ksft_test_result_fail("v-regesters are not properly initialized\n"); - dump(datap, vl * 4); - exit(-1); - } - - for (i =3D 1; i < vl * 4; i++) { - if (datap[i] !=3D datap[0]) { - ksft_test_result_fail("detect stale values on v-regesters\n"); - dump(datap, vl * 4); - exit(-2); - } - } - - free(datap); - ksft_exit_pass(); - return 0; -} diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/te= sting/selftests/riscv/vector/vstate_prctl.c index 27668fb3b6d0..528e8c544db0 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -3,50 +3,13 @@ #include #include #include +#include +#include =20 -#include "../hwprobe/hwprobe.h" -#include "../../kselftest.h" +#include "../../kselftest_harness.h" +#include "v_helpers.h" =20 #define NEXT_PROGRAM "./vstate_exec_nolibc" -static int launch_test(int test_inherit) -{ - char *exec_argv[3], *exec_envp[1]; - int rc, pid, status; - - pid =3D fork(); - if (pid < 0) { - ksft_test_result_fail("fork failed %d", pid); - return -1; - } - - if (!pid) { - exec_argv[0] =3D NEXT_PROGRAM; - exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; - exec_argv[2] =3D NULL; - exec_envp[0] =3D NULL; - /* launch the program again to check inherit */ - rc =3D execve(NEXT_PROGRAM, exec_argv, exec_envp); - if (rc) { - perror("execve"); - ksft_test_result_fail("child execve failed %d\n", rc); - exit(-1); - } - } - - rc =3D waitpid(-1, &status, 0); - if (rc < 0) { - ksft_test_result_fail("waitpid failed\n"); - return -3; - } - - if ((WIFEXITED(status) && WEXITSTATUS(status) =3D=3D -1) || - WIFSIGNALED(status)) { - ksft_test_result_fail("child exited abnormally\n"); - return -4; - } - - return WEXITSTATUS(status); -} =20 int test_and_compare_child(long provided, long expected, int inherit) { @@ -54,14 +17,13 @@ int test_and_compare_child(long provided, long expected= , int inherit) =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, provided); if (rc !=3D 0) { - ksft_test_result_fail("prctl with provided arg %lx failed with code %d\n= ", - provided, rc); + printf("prctl with provided arg %lx failed with code %d\n", + provided, rc); return -1; } - rc =3D launch_test(inherit); + rc =3D launch_test(NEXT_PROGRAM, inherit); if (rc !=3D expected) { - ksft_test_result_fail("Test failed, check %d !=3D %ld\n", rc, - expected); + printf("Test failed, check %d !=3D %ld\n", rc, expected); return -2; } return 0; @@ -70,112 +32,180 @@ int test_and_compare_child(long provided, long expect= ed, int inherit) #define PR_RISCV_V_VSTATE_CTRL_CUR_SHIFT 0 #define PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT 2 =20 -int main(void) +TEST(get_control_no_v) { - struct riscv_hwprobe pair; - long flag, expected; long rc; =20 - pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; - rc =3D riscv_hwprobe(&pair, 1, 0, NULL, 0); - if (rc < 0) { - ksft_test_result_fail("hwprobe() failed with %ld\n", rc); - return -1; - } + if (is_vector_supported()) + SKIP(return, "Test expects vector to be not supported"); =20 - if (pair.key !=3D RISCV_HWPROBE_KEY_IMA_EXT_0) { - ksft_test_result_fail("hwprobe cannot probe RISCV_HWPROBE_KEY_IMA_EXT_0\= n"); - return -2; - } + rc =3D prctl(PR_RISCV_V_GET_CONTROL); + EXPECT_EQ(-1, rc) TH_LOG("GET_CONTROL should fail on kernel/hw without V"= ); + EXPECT_EQ(EINVAL, errno) TH_LOG("GET_CONTROL should fail on kernel/hw wit= hout V"); +} =20 - if (!(pair.value & RISCV_HWPROBE_IMA_V)) { - rc =3D prctl(PR_RISCV_V_GET_CONTROL); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n= "); - return -3; - } - - rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n= "); - return -4; - } - - ksft_test_result_skip("Vector not supported\n"); - return 0; - } +TEST(set_control_no_v) +{ + long rc; + + if (is_vector_supported()) + SKIP(return, "Test expects vector to be not supported"); + + rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); + EXPECT_EQ(-1, rc) TH_LOG("SET_CONTROL should fail on kernel/hw without V"= ); + EXPECT_EQ(EINVAL, errno) TH_LOG("SET_CONTROL should fail on kernel/hw wit= hout V"); +} + +TEST(vstate_on_current) +{ + long flag; + long rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_ON; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - if (rc !=3D 0) { - ksft_test_result_fail("Enabling V for current should always success\n"); - return -5; - } + EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always success"); +} + +TEST(vstate_off_eperm) +{ + long flag; + long rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_OFF; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - if (rc !=3D -1 || errno !=3D EPERM) { - ksft_test_result_fail("Disabling current's V alive must fail with EPERM(= %d)\n", - errno); - return -5; - } + EXPECT_EQ(EPERM, errno) TH_LOG("Disabling current's V alive must fail wit= h EPERM(%d)", errno); + EXPECT_EQ(-1, rc) TH_LOG("Disabling current's V alive must fail with EPER= M(%d)", errno); +} + +TEST(vstate_on_no_nesting) +{ + long flag; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn on next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; - if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)) - return -6; + + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)); +} + +TEST(vstate_off_nesting) +{ + long flag; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn off next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; - if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 0)) - return -7; + + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1)); +} + +TEST(vstate_on_inherit_no_nesting) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + /* Turn on next's vector explicitly and test no inherit */ + flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; + + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); +} + +TEST(vstate_on_inherit) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn on next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; - if (test_and_compare_child(flag, expected, 0)) - return -8; =20 - if (test_and_compare_child(flag, expected, 1)) - return -9; + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); +} + +TEST(vstate_off_inherit_no_nesting) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + /* Turn off next's vector explicitly and test no inherit */ + flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; + + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); +} + +TEST(vstate_off_inherit) +{ + long flag, expected; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 /* Turn off next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; - if (test_and_compare_child(flag, expected, 0)) - return -10; =20 - if (test_and_compare_child(flag, expected, 1)) - return -11; + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); +} + +/* arguments should fail with EINVAL */ +TEST(inval_set_control_1) +{ + int rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 - /* arguments should fail with EINVAL */ rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xff0); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); +} + +/* arguments should fail with EINVAL */ +TEST(inval_set_control_2) +{ + int rc; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0x3); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); +} =20 - rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } +/* arguments should fail with EINVAL */ +TEST(inval_set_control_3) +{ + int rc; =20 - rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); - if (rc !=3D -1 || errno !=3D EINVAL) { - ksft_test_result_fail("Undefined control argument should return EINVAL\n= "); - return -12; - } + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); =20 - ksft_test_result_pass("tests for riscv_v_vstate_ctrl pass\n"); - ksft_exit_pass(); - return 0; + rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); + EXPECT_EQ(-1, rc); + EXPECT_EQ(EINVAL, errno); } + +TEST_HARNESS_MAIN --=20 2.44.0 From nobody Thu Feb 12 17:27:44 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E109E6BB33 for ; Mon, 10 Jun 2024 04:46:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994765; cv=none; b=Vjw14QQPPANySPZGIFnsFGH7Bps3ZDv+nK87bGZiqjUCOOlBtZL86RnrZIckeDJKIoJr5e2ZC+vkgVbj7YMK1DZWujVTPwg2rMifcC+CgdMGg5PtvnWTUySPzMvnHRlg6EIuWAxwcQFGsbbFfPLy9r1ccoM0AIkaDYnHS18uZOA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717994765; c=relaxed/simple; bh=89do+Iu5RzVkWiXYu8asYhzFXtnE5ZFmYADPVBsb7VU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sGJ2IB+Ya8SjK+K7ef2ZkZg+8EVNzyIMQSajjpWvvOKiHkn6hfitGCmeCp+2hZ8138Ha//m/0u/U+oRg5I4F7AgNzSg5B9GswZndbvf95FbZoNa+ld9FeUdajfgfajyf2M9oDZZZIbzJfCfpOPlsnrDeBDiZDuzM4R+uK1Mn93k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=NyrNu1G/; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="NyrNu1G/" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-1f44b5b9de6so31572245ad.3 for ; Sun, 09 Jun 2024 21:46:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1717994763; x=1718599563; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=f2sfNsaQxId1BqeFASEoVxo8c/eR/7T/BctdU8871Fw=; b=NyrNu1G/KQW1Kfliqtl6pbyKcqteuL29g5IX2hFrmmSJkhsK3gn70sY9zk7pNKHbDl ImqeDCyR4pn/KskI7yUlha+iQPzhcSgaQzL3Brr1W/7mY+Wre5pN5IQZ3bq6CPmFQ5/x lwAs9vH4C64gmxYO1EF9SUQsDs7CnVUDa3f0xd1jYm8RveaKykdQItKLdcoEOn41hwva xd+8FGHlGpYpQT6Qjo89NmHU2oNjgYNzvRrvdcUVrTYaZqKwrA7n+x08KOfUZJkt1ByK 5rqVPU65f0etNHEAaH7ROUlw2w3GDevISQP4SnQ+aTzqWxr5jD8rxioPVIs8OEgxnnIc Wqbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717994763; x=1718599563; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f2sfNsaQxId1BqeFASEoVxo8c/eR/7T/BctdU8871Fw=; b=LhyAbso48hfCZtbsJF6ugOqDv04lpaWQzPvKiIsJZnPlSMtQvsqJ/62F9JmaDVvemU eQPf0aMPaguIQPeGftHWb16rtj/xK1pEo28KdABpchKAeWqte8G1iMbaODMFedBnLxys 1MX7ixR1Tc5GIAArFA/wltLFswioUpgVlzL5gMA6F1mX/9X3DsGgoP/df99ezDFNXPJg xIaUP2346SPkY43J80ToP/Mf6BBKgH/kbgMnsOvJH2pQDn3kmXSsegrQ4lmE8VPz8woD IojblwAtUc/60DKQySc/38B3kYxEEmXOj2SAdOuB5p/V6pFDt6GkZgs7zF5yyvnDQdNA ycXw== X-Forwarded-Encrypted: i=1; AJvYcCXVuSLUonXPPDg4rfTn2bJMrk2NHfTltxOcigf6INXtijhyT5Ug1qUkzEGl8vB7PpZHKL4v6dJY2H+yZ+f0gEfiW4F05zPzvJSSyrep X-Gm-Message-State: AOJu0Yx8X4Z7/qoZAH2g/q3AGjZULg+qDI+ZlR2rjXGQKmzAL99YsIf/ bQJiO4YFXsGGaIQZZahi4igoIRvAZodbLzj25FiRf+PVERE//yfcsSx1yYV9GVM= X-Google-Smtp-Source: AGHT+IGzFIKn4oe74vjWI+nQxzlKuj7RnKDlQQ7ToGun10qPUfHRxLbkmgSLo9Q400U96OtUdpdlBQ== X-Received: by 2002:a17:902:ea08:b0:1f6:8314:50f5 with SMTP id d9443c01a7336-1f6d02e6d36mr98504295ad.15.1717994762790; Sun, 09 Jun 2024 21:46:02 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6bd76ce8asm73124095ad.77.2024.06.09.21.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jun 2024 21:46:01 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:18 -0700 Subject: [PATCH 13/13] selftests: riscv: Support xtheadvector in vector tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240609-xtheadvector-v1-13-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=13221; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=89do+Iu5RzVkWiXYu8asYhzFXtnE5ZFmYADPVBsb7VU=; b=cPWLT+3iSTWOGDVUiyQgiH39Ne+yNXrdZId3fvSeCYyWYMtkXPaeZbjrnddBPWAx61JSTE+np s/p3zXqMIFECoNIXmSnJMP+fuV3gs3cX5Dw9SODO8ME5u95efvXur7m X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Extend existing vector tests to be compatible with the xtheadvector instructions. Signed-off-by: Charlie Jenkins --- .../selftests/riscv/vector/v_exec_initval_nolibc.c | 23 ++++-- tools/testing/selftests/riscv/vector/v_helpers.c | 17 +++- tools/testing/selftests/riscv/vector/v_helpers.h | 4 +- tools/testing/selftests/riscv/vector/v_initval.c | 12 ++- .../selftests/riscv/vector/vstate_exec_nolibc.c | 20 +++-- .../testing/selftests/riscv/vector/vstate_prctl.c | 91 ++++++++++++++----= ---- 6 files changed, 115 insertions(+), 52 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c b= /tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c index 74b13806baf0..58c29ea91b80 100644 --- a/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c +++ b/tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c @@ -18,13 +18,22 @@ int main(int argc, char **argv) unsigned long vl; int first =3D 1; =20 - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" - ".option pop\n\t" - : [vl] "=3Dr" (vl) - ); + if (argc > 2 && strcmp(argv[2], "x")) + asm volatile ( + // 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli + // vsetvli t4, x0, e8, m1, d1 + ".insn 0b00000000000000000111111011010111\n\t" + "mv %[vl], t4\n\t" + : [vl] "=3Dr" (vl) : : "t4" + ); + else + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %[vl], x0, e8, m1, ta, ma\n\t" + ".option pop\n\t" + : [vl] "=3Dr" (vl) + ); =20 #define CHECK_VECTOR_REGISTER(register) ({ \ for (int i =3D 0; i < vl; i++) { \ diff --git a/tools/testing/selftests/riscv/vector/v_helpers.c b/tools/testi= ng/selftests/riscv/vector/v_helpers.c index 15c22318db72..2c4df76eefe9 100644 --- a/tools/testing/selftests/riscv/vector/v_helpers.c +++ b/tools/testing/selftests/riscv/vector/v_helpers.c @@ -1,11 +1,21 @@ // SPDX-License-Identifier: GPL-2.0-only =20 #include "../hwprobe/hwprobe.h" +#include #include #include #include #include =20 +int is_xtheadvector_supported(void) +{ + struct riscv_hwprobe pair; + + pair.key =3D RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0; + riscv_hwprobe(&pair, 1, 0, NULL, 0); + return pair.value & RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR; +} + int is_vector_supported(void) { struct riscv_hwprobe pair; @@ -15,9 +25,9 @@ int is_vector_supported(void) return pair.value & RISCV_HWPROBE_IMA_V; } =20 -int launch_test(char *next_program, int test_inherit) +int launch_test(char *next_program, int test_inherit, int xtheadvector) { - char *exec_argv[3], *exec_envp[1]; + char *exec_argv[4], *exec_envp[1]; int rc, pid, status; =20 pid =3D fork(); @@ -29,7 +39,8 @@ int launch_test(char *next_program, int test_inherit) if (!pid) { exec_argv[0] =3D next_program; exec_argv[1] =3D test_inherit !=3D 0 ? "x" : NULL; - exec_argv[2] =3D NULL; + exec_argv[2] =3D xtheadvector !=3D 0 ? "x" : NULL; + exec_argv[3] =3D NULL; exec_envp[0] =3D NULL; /* launch the program again to check inherit */ rc =3D execve(next_program, exec_argv, exec_envp); diff --git a/tools/testing/selftests/riscv/vector/v_helpers.h b/tools/testi= ng/selftests/riscv/vector/v_helpers.h index 88719c4be496..67d41cb6f871 100644 --- a/tools/testing/selftests/riscv/vector/v_helpers.h +++ b/tools/testing/selftests/riscv/vector/v_helpers.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +int is_xtheadvector_supported(void); + int is_vector_supported(void); =20 -int launch_test(char *next_program, int test_inherit); +int launch_test(char *next_program, int test_inherit, int xtheadvector); diff --git a/tools/testing/selftests/riscv/vector/v_initval.c b/tools/testi= ng/selftests/riscv/vector/v_initval.c index f38b5797fa31..be9e1d18ad29 100644 --- a/tools/testing/selftests/riscv/vector/v_initval.c +++ b/tools/testing/selftests/riscv/vector/v_initval.c @@ -7,10 +7,16 @@ =20 TEST(v_initval) { - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + int xtheadvector =3D 0; =20 - ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0)); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } + + ASSERT_EQ(0, launch_test(NEXT_PROGRAM, 0, xtheadvector)); } =20 TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c b/to= ols/testing/selftests/riscv/vector/vstate_exec_nolibc.c index 1f9969bed235..12d30d3b90fa 100644 --- a/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c +++ b/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c @@ -6,13 +6,16 @@ =20 int main(int argc, char **argv) { - int rc, pid, status, test_inherit =3D 0; + int rc, pid, status, test_inherit =3D 0, xtheadvector =3D 0; long ctrl, ctrl_c; char *exec_argv[2], *exec_envp[2]; =20 - if (argc > 1) + if (argc > 1 && strcmp(argv[1], "x")) test_inherit =3D 1; =20 + if (argc > 2 && strcmp(argv[2], "x")) + xtheadvector =3D 1; + ctrl =3D my_syscall1(__NR_prctl, PR_RISCV_V_GET_CONTROL); if (ctrl < 0) { puts("PR_RISCV_V_GET_CONTROL is not supported\n"); @@ -53,11 +56,14 @@ int main(int argc, char **argv) puts("child's vstate_ctrl not equal to parent's\n"); exit(-1); } - asm volatile (".option push\n\t" - ".option arch, +v\n\t" - "vsetvli x0, x0, e32, m8, ta, ma\n\t" - ".option pop\n\t" - ); + if (xtheadvector) + asm volatile (".insn 0x00007ed7"); + else + asm volatile (".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e32, m8, ta, ma\n\t" + ".option pop\n\t" + ); exit(ctrl); } } diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/te= sting/selftests/riscv/vector/vstate_prctl.c index 528e8c544db0..375af40e88e6 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -11,7 +11,7 @@ =20 #define NEXT_PROGRAM "./vstate_exec_nolibc" =20 -int test_and_compare_child(long provided, long expected, int inherit) +int test_and_compare_child(long provided, long expected, int inherit, int = xtheadvector) { int rc; =20 @@ -21,7 +21,7 @@ int test_and_compare_child(long provided, long expected, = int inherit) provided, rc); return -1; } - rc =3D launch_test(NEXT_PROGRAM, inherit); + rc =3D launch_test(NEXT_PROGRAM, inherit, xtheadvector); if (rc !=3D expected) { printf("Test failed, check %d !=3D %ld\n", rc, expected); return -2; @@ -36,7 +36,7 @@ TEST(get_control_no_v) { long rc; =20 - if (is_vector_supported()) + if (is_vector_supported() || is_xtheadvector_supported()) SKIP(return, "Test expects vector to be not supported"); =20 rc =3D prctl(PR_RISCV_V_GET_CONTROL); @@ -48,7 +48,7 @@ TEST(set_control_no_v) { long rc; =20 - if (is_vector_supported()) + if (is_vector_supported() || is_xtheadvector_supported()) SKIP(return, "Test expects vector to be not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); @@ -61,12 +61,12 @@ TEST(vstate_on_current) long flag; long rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_ON; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always success"); + EXPECT_EQ(0, rc) TH_LOG("Enabling V for current should always succeed"); } =20 TEST(vstate_off_eperm) @@ -74,99 +74,128 @@ TEST(vstate_off_eperm) long flag; long rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 flag =3D PR_RISCV_V_VSTATE_CTRL_OFF; rc =3D prctl(PR_RISCV_V_SET_CONTROL, flag); - EXPECT_EQ(EPERM, errno) TH_LOG("Disabling current's V alive must fail wit= h EPERM(%d)", errno); - EXPECT_EQ(-1, rc) TH_LOG("Disabling current's V alive must fail with EPER= M(%d)", errno); + EXPECT_EQ(EPERM, errno) TH_LOG("Disabling V in current thread with V enab= led must fail with EPERM(%d)", errno); + EXPECT_EQ(-1, rc) TH_LOG("Disabling V in current thread with V enabled mu= st fail with EPERM(%d)", errno); } =20 TEST(vstate_on_no_nesting) { long flag; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; =20 - EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0, x= theadvector)); } =20 TEST(vstate_off_nesting) { long flag; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn off next's vector explicitly and test */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; =20 - EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 1, = xtheadvector)); } =20 TEST(vstate_on_inherit_no_nesting) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test no inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0, xtheadvector)); } =20 TEST(vstate_on_inherit) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn on next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_ON; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1, xtheadvector)); } =20 TEST(vstate_off_inherit_no_nesting) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); - + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } /* Turn off next's vector explicitly and test no inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 0)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 0, xtheadvector)); } =20 TEST(vstate_off_inherit) { long flag, expected; + int xtheadvector =3D 0; =20 - if (!is_vector_supported()) - SKIP(return, "Vector not supported"); + if (!is_vector_supported()) { + if (is_xtheadvector_supported()) + xtheadvector =3D 1; + else + SKIP(return, "Vector not supported"); + } =20 /* Turn off next's vector explicitly and test inherit */ flag =3D PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; flag |=3D PR_RISCV_V_VSTATE_CTRL_INHERIT; expected =3D flag | PR_RISCV_V_VSTATE_CTRL_OFF; =20 - EXPECT_EQ(0, test_and_compare_child(flag, expected, 1)); + EXPECT_EQ(0, test_and_compare_child(flag, expected, 1, xtheadvector)); } =20 /* arguments should fail with EINVAL */ @@ -174,7 +203,7 @@ TEST(inval_set_control_1) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xff0); @@ -187,7 +216,7 @@ TEST(inval_set_control_2) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0x3); @@ -200,7 +229,7 @@ TEST(inval_set_control_3) { int rc; =20 - if (!is_vector_supported()) + if (!is_vector_supported() && !is_xtheadvector_supported()) SKIP(return, "Vector not supported"); =20 rc =3D prctl(PR_RISCV_V_SET_CONTROL, 0xc); --=20 2.44.0