From nobody Thu Feb 12 20:29:25 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FF2D15B556; Fri, 7 Jun 2024 09:04:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717751092; cv=none; b=f6MnhCSI0I/DVlRZrrm6tw0OqNbaAONlymG7PG2HQsGPj3dzoXQGpMioliwEPTXYKevWN7myHS5obalOEoBCtnmpzXVO66pNHnwJ3vHcUxqafWOAtEZdAO9ArlTyPiL71FS3rDk/whoplqHfElqUQyqVNXTgsu88Ayh8lpkY4ac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717751092; c=relaxed/simple; bh=EfH6RGhEyXtRycnSNlIJFDnoF6A3+RynBwoX/CmEOgk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ul+ZMor/2AZwFev/n3FX4DPDtF9T51TDkLEFG3M5yu/nF17/Zi6qam5NXXREYC573Tt6h4mWbl3K8LHqRaAehAEc4dwN80LEF4PxZK82Sza/fbWs8kWC0hkhEYEqqKWqNvnJDMODgi+a+rl27jIeKXk9zzSjtMPNSzxVKhNEP/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Holxq3hw; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Holxq3hw" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45794fLA124345; Fri, 7 Jun 2024 04:04:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717751081; bh=y8iEQZdBJrT05CHGObd8DnQRyIVkw4FhSN7lZ87J+rY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Holxq3hw93NnBbihMlT3lnvXqxIH4DkWcQw/L6Qkbjwu2Fb/6tsTJWVK9d22Pq3wS gFiC3V/d8i9qpRt5xxltTpJFBTRHv4sv0zdMco0CXozaU21+FS2Vu08HP51GX/FCV1 OTKE5VXzJrCPfUvNyTpYkXuoBCz1MYQV2/LXGYGQ= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45794f5o018317 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 7 Jun 2024 04:04:41 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 7 Jun 2024 04:04:41 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 7 Jun 2024 04:04:41 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [10.24.69.66]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45794Xgk020305; Fri, 7 Jun 2024 04:04:38 -0500 From: Beleswar Padhi To: , CC: , , , , , , , , , Subject: [PATCH 1/3] arm64: dts: ti: Add R5F and C7x remote processor nodes Date: Fri, 7 Jun 2024 14:34:31 +0530 Message-ID: <20240607090433.488454-2-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240607090433.488454-1-b-padhi@ti.com> References: <20240607090433.488454-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Apurva Nandan The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. Add the DT nodes to support Inter-Processor Communication. Signed-off-by: Apurva Nandan Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j722s.dtsi | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index c75744edb1433..a894a132f1667 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -87,3 +87,66 @@ &oc_sram { reg =3D <0x00 0x70000000 0x00 0x40000>; ranges =3D <0x00 0x00 0x70000000 0x40000>; }; + +&cbass_main { + main_r5fss0: r5fss@78400000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78400000 0x00 0x78400000 0x8000>, + <0x78500000 0x00 0x78500000 0x8000>; + power-domains =3D <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + main_r5fss0_core0: r5f@78400000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78400000 0x00008000>, + <0x78500000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <262>; + ti,sci-proc-ids =3D <0x04 0xff>; + resets =3D <&k3_reset 262 1>; + firmware-name =3D "j722s-main-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + }; + }; + + c7x_0: dsp@7e000000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e000000 0x00 0x00200000>; + reg-names =3D "l2sram"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <208>; + ti,sci-proc-ids =3D <0x30 0xff>; + resets =3D <&k3_reset 208 1>; + firmware-name =3D "j722s-c71_0-fw"; + status =3D "disabled"; + }; + + c7x_1: dsp@7e200000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e200000 0x00 0x00200000>; + reg-names =3D "l2sram"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <268>; + ti,sci-proc-ids =3D <0x31 0xff>; + resets =3D <&k3_reset 268 1>; + firmware-name =3D "j722s-c71_1-fw"; + status =3D "disabled"; + }; +}; + +/* MCU domain overrides */ + +&mcu_r5fss0_core0 { + firmware-name =3D "j722s-mcu-r5f0_0-fw"; +}; + +/* Wakeup domain overrides */ + +&wkup_r5fss0_core0 { + firmware-name =3D "j722s-wkup-r5f0_0-fw"; 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Fri, 7 Jun 2024 04:04:45 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 7 Jun 2024 04:04:45 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 7 Jun 2024 04:04:45 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [10.24.69.66]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45794Xgl020305; Fri, 7 Jun 2024 04:04:42 -0500 From: Beleswar Padhi To: , CC: , , , , , , , , , Subject: [PATCH 2/3] arm64: dts: ti: k3-j722s-evm: Enable Mailbox clusters Date: Fri, 7 Jun 2024 14:34:32 +0530 Message-ID: <20240607090433.488454-3-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240607090433.488454-1-b-padhi@ti.com> References: <20240607090433.488454-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. The Inter-Processor communication between the main A72 cores and these R5F and DSP remote cores is achieved through shared memory and Mailboxes. Thus, enable the Mailbox clusters required for communication. Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 37 +++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index bf3c246d13d1f..a51925deb43b8 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -384,3 +384,40 @@ &sdhci1 { status =3D "okay"; bootph-all; }; + +&mailbox0_cluster0 { + status =3D "okay"; + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; --=20 2.34.1 From nobody Thu Feb 12 20:29:25 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6A1315B547; Fri, 7 Jun 2024 09:05:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717751108; cv=none; b=W2BNO1BHzou2EO4uM2GI8KzenxuHnUoMiXKyccU9VPeuShhF4MIEdWRNJP0yi9jYtOQaj2MbM1m7UxpCLfV8ZuEplI4KdQzeOmWTU5v/9+zk7afX8XTMjQHXyAoQo9lQrvK4exb0BlXMwRyHTcJ8LqO/Q3SHE46H5tml3IeQi0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717751108; c=relaxed/simple; bh=DsCWGwKSCDQpABox2ufY+za/xaJ250sXQdmmpQt5RPY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mG8yRAGqdfSVlnKiamWudK8KY2qyZasQvVJRsceZPQonANoQLXX4NXQuDlSccdU0nXwcajHYJ5ugpJb/Qd30Helia2U2firVD9X32LjDZxqY+3IngwEz0f0oNHLTMIjjoxZEaw+upQcf2HTKcEWrOIKpSlsUn5dDOSYGbNsvNCQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Yb0WCDUF; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Yb0WCDUF" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45794nR5054203; Fri, 7 Jun 2024 04:04:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717751089; bh=QP0/ho1jHT2b8fV+ijzgJx8hm5uDZ/97a6HnJKLegYU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Yb0WCDUF4IDnDMRSGqltF7TieGVMO03blo8e7bIsyLrMKDGlS4wabLX/2tZ3Aek/h nqaAPsf/PLnCzhDenqhzhjkTCqtd7boXSlwv70Tq3DD9ugSnnv6VqNzd9Kib3CeDEq MlVeMqQaxL+sjY7bybi7eLdrUz97vAhdeu9QllO8= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45794nkp047417 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 7 Jun 2024 04:04:49 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 7 Jun 2024 04:04:49 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 7 Jun 2024 04:04:48 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [10.24.69.66]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45794Xgm020305; Fri, 7 Jun 2024 04:04:45 -0500 From: Beleswar Padhi To: , CC: , , , , , , , , , Subject: [PATCH 3/3] arm64: dts: ti: k3-j722s-evm: Add memory carveouts for R5F and C7x Date: Fri, 7 Jun 2024 14:34:33 +0530 Message-ID: <20240607090433.488454-4-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240607090433.488454-1-b-padhi@ti.com> References: <20240607090433.488454-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Apurva Nandan The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. The Inter-Processor communication between the main A72 cores and these R5F and DSP remote cores is achieved through shared memory and Mailboxes. Thus, add the memory carveouts required for communication. Signed-off-by: Apurva Nandan Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 103 ++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index a51925deb43b8..b0b5b6c97b92d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -49,12 +49,71 @@ secure_ddr: optee@9e800000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a20000= 00 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x1c00000>; + alignment =3D <0x1000>; + no-map; + }; }; =20 vmain_pd: regulator-0 { @@ -421,3 +480,47 @@ mbox_c7x_1: mbox-c7x-1 { ti,mbox-tx =3D <3 0 0>; }; }; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; +}; + +&c7x_1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region =3D <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; +}; --=20 2.34.1