From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 826B31514F9; Fri, 7 Jun 2024 20:32:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792324; cv=none; b=e1or98+c395Hk5B3UiU1ENAvtO8sJ8daAW4trsTUQmLgqGqiz+Kn0Tl+QJYIxP73yZxM/47e2grtBVEvZZMZj2dHExagXgUHoCgt4hZJFiAinmDlfUxd6nHT+XJVifGkQJySAiE9TbSnum3YuG4GFaTrC3eJ5nIo4F5cYE7t228= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792324; c=relaxed/simple; bh=fgF8NeangU+IYDXxVWYK3CVB9PI5gI3tRv7iErEHfpY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L2+X7SZIR5qaPIExc6z6tX5Nezme43/BF276mbjQrFT90lRp/QrJePAV8+uMo2fyymUJZ/NuGvfccTbagqUNHyl067v0vQAfeppf6qbUdLihog8+98/LaV8KHuQygtE6Nvt6zvCgmaVmuCljNE0RmgjIxP3xQztO4Dn3urbcvps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hbCjfBcM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hbCjfBcM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2B66EC2BBFC; Fri, 7 Jun 2024 20:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792324; bh=fgF8NeangU+IYDXxVWYK3CVB9PI5gI3tRv7iErEHfpY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hbCjfBcM3eIR2Mal8CfRaYjzFSXUf6/Q7WYuXt5+rlxCh3OhtrAcB/W7haHwswniR WPaG6cXPDXUrbnFoYN80MYkqsNEvOC3vAAe61v9eRCaOZEn4xJYKEJ9TnF/T+QbfVA x+4hoeaAg2vOJ19VydY4g+A6DsCQWzYhBw+TvlDMzWrBvtZpvr+hdQ9kKX9xPgwBev DvPPIOupbR5mAC5+r4aPHnJnCSXB5zGqBYD6+ciqcHKME26/hL0Xcc9GppC1x2eCwR X7Wke+Gs5eN6LbU1ZxEOcW4pUEa7kfp2ix1ibcVKLge8q/eneo/QQjJzHdylDmMrUo CmUsL4H07aPIg== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:26 -0600 Subject: [PATCH 1/9] perf/arm: Move 32-bit PMU drivers to drivers/perf/ Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-1-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev It is preferred to put drivers under drivers/ rather than under arch/. The PMU drivers also depend on arm_pmu.c, so it's better to place them all together. Signed-off-by: Rob Herring (Arm) Acked-by: Mark Rutland --- arch/arm/kernel/Makefile | 2 -- drivers/perf/Kconfig | 12 ++++++++= ++++ drivers/perf/Makefile | 3 +++ arch/arm/kernel/perf_event_v6.c =3D> drivers/perf/arm_v6_pmu.c | 3 --- arch/arm/kernel/perf_event_v7.c =3D> drivers/perf/arm_v7_pmu.c | 3 --- .../perf_event_xscale.c =3D> drivers/perf/arm_xscale_pmu.c | 3 --- 6 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 89a77e3f51d2..aaae31b8c4a5 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -78,8 +78,6 @@ obj-$(CONFIG_CPU_XSC3) +=3D xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) +=3D xscale-cp0.o obj-$(CONFIG_IWMMXT) +=3D iwmmxt.o obj-$(CONFIG_PERF_EVENTS) +=3D perf_regs.o perf_callchain.o -obj-$(CONFIG_HW_PERF_EVENTS) +=3D perf_event_xscale.o perf_event_v6.o \ - perf_event_v7.o AFLAGS_iwmmxt.o :=3D -Wa,-mcpu=3Diwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) +=3D topology.o obj-$(CONFIG_VDSO) +=3D vdso.o diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 7526a9e714fa..aa9530b4064f 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -56,6 +56,18 @@ config ARM_PMU Say y if you want to use CPU performance monitors on ARM-based systems. =20 +config ARM_V6_PMU + depends on ARM_PMU && (CPU_V6 || CPU_V6K) + def_bool y + +config ARM_V7_PMU + depends on ARM_PMU && CPU_V7 + def_bool y + +config ARM_XSCALE_PMU + depends on ARM_PMU && CPU_XSCALE + def_bool y + config RISCV_PMU depends on RISCV bool "RISC-V PMU framework" diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 29b1c28203ef..d43df81d52f7 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -6,6 +6,9 @@ obj-$(CONFIG_ARM_DSU_PMU) +=3D arm_dsu_pmu.o obj-$(CONFIG_ARM_PMU) +=3D arm_pmu.o arm_pmu_platform.o obj-$(CONFIG_ARM_PMU_ACPI) +=3D arm_pmu_acpi.o obj-$(CONFIG_ARM_PMUV3) +=3D arm_pmuv3.o +obj-$(CONFIG_ARM_V6_PMU) +=3D arm_v6_pmu.o +obj-$(CONFIG_ARM_V7_PMU) +=3D arm_v7_pmu.o +obj-$(CONFIG_ARM_XSCALE_PMU) +=3D arm_xscale_pmu.o obj-$(CONFIG_ARM_SMMU_V3_PMU) +=3D arm_smmuv3_pmu.o obj-$(CONFIG_FSL_IMX8_DDR_PMU) +=3D fsl_imx8_ddr_perf.o obj-$(CONFIG_FSL_IMX9_DDR_PMU) +=3D fsl_imx9_ddr_perf.o diff --git a/arch/arm/kernel/perf_event_v6.c b/drivers/perf/arm_v6_pmu.c similarity index 99% rename from arch/arm/kernel/perf_event_v6.c rename to drivers/perf/arm_v6_pmu.c index d9fd53841591..f7593843bb85 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/drivers/perf/arm_v6_pmu.c @@ -31,8 +31,6 @@ * enable the interrupt. */ =20 -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) - #include #include =20 @@ -445,4 +443,3 @@ static struct platform_driver armv6_pmu_driver =3D { }; =20 builtin_platform_driver(armv6_pmu_driver); -#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */ diff --git a/arch/arm/kernel/perf_event_v7.c b/drivers/perf/arm_v7_pmu.c similarity index 99% rename from arch/arm/kernel/perf_event_v7.c rename to drivers/perf/arm_v7_pmu.c index a3322e2b3ea4..fdd936fbd188 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/drivers/perf/arm_v7_pmu.c @@ -17,8 +17,6 @@ * counter and all 4 performance counters together can be reset separatel= y. */ =20 -#ifdef CONFIG_CPU_V7 - #include #include #include @@ -2002,4 +2000,3 @@ static struct platform_driver armv7_pmu_driver =3D { }; =20 builtin_platform_driver(armv7_pmu_driver); -#endif /* CONFIG_CPU_V7 */ diff --git a/arch/arm/kernel/perf_event_xscale.c b/drivers/perf/arm_xscale_= pmu.c similarity index 99% rename from arch/arm/kernel/perf_event_xscale.c rename to drivers/perf/arm_xscale_pmu.c index 7a2ba1c689a7..3d8b72d6b37f 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/drivers/perf/arm_xscale_pmu.c @@ -13,8 +13,6 @@ * PMU structures. */ =20 -#ifdef CONFIG_CPU_XSCALE - #include #include =20 @@ -745,4 +743,3 @@ static struct platform_driver xscale_pmu_driver =3D { }; =20 builtin_platform_driver(xscale_pmu_driver); -#endif /* CONFIG_CPU_XSCALE */ --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F8EB154BFB; Fri, 7 Jun 2024 20:32:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792326; cv=none; b=bchkU6eFkNYvTyejCaJykS4cQsuKjWQfZVQN/Ug17GjrXTZvchbKFHf1Qe2AD4PL5+66VTXYqvi55OhCm/900gJfhjYrvtAAe66fD9rUmzr06uGCnC5TgOsl594k4XEnkC+1ZLS/EN9peDoqADgmq2KXeUOkx0Jkuw03eVvIW0I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792326; c=relaxed/simple; bh=HBZLgS2LXgUqfTn0Nl4TrmtgYXpXNMKYvKyVmoxUwjM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V/ebQSj98BtJRTnPiI2xk3MmVRm9hrs3jg/+2i02ByRNjBLYCF/VNeVhCnDFlgw3bIMiCWwb1P4e1q8vVFaxbJs101mgi4Sta4WsKfM/3krg1TAAYgxQnJfGm1QAG1iwDP1Vs02EmPghAirfCHU+x4ZHCKDmK/CmOujvEjwds8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WfNPxBQm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WfNPxBQm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9961EC32781; Fri, 7 Jun 2024 20:32:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792325; bh=HBZLgS2LXgUqfTn0Nl4TrmtgYXpXNMKYvKyVmoxUwjM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WfNPxBQmwRVXcwIST4BC7IJCXp4/rTNUJzAVD1GARUWz+0AQo/etwkM3OsQv8Vo0p XESZqf74bQPPhqiZOiEcKeRq+UT6ew2fETMERBLxdZ89F8pSL3jTLlSP440aC96oK4 en8jJV05w0ydNPZFs0NiGWMkfCsv/XrQOAM6NP1lJXq7DfwTVisEtKWYT9qrJ/i2fw 2ZBEpyMjbiN1r4JPzUK2JFmDXXJcUijg3kRygcklKYFUZSKfmFpJ2XUC2If3yjbAlp az42GwH5bBlFdXzTSAs5xeKSP35ihrxkF4QJ0sngzZo4/3Ivh3O6uWZ+BwCCvYyX6b w+Cq5myiqzu6w== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:27 -0600 Subject: [PATCH 2/9] perf: arm_v6/7_pmu: Drop non-DT probe support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-2-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev There are no non-DT based PMU users for v6 or v7, so drop the custom non-DT probe table. Note that this drops support for arm1156 PMU, but there are no arm1156 based systems supported in the kernel. Signed-off-by: Rob Herring (Arm) Acked-by: Mark Rutland --- drivers/perf/arm_v6_pmu.c | 17 +---------------- drivers/perf/arm_v7_pmu.c | 10 +--------- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/drivers/perf/arm_v6_pmu.c b/drivers/perf/arm_v6_pmu.c index f7593843bb85..0bb685b4bac5 100644 --- a/drivers/perf/arm_v6_pmu.c +++ b/drivers/perf/arm_v6_pmu.c @@ -401,13 +401,6 @@ static int armv6_1136_pmu_init(struct arm_pmu *cpu_pmu) return 0; } =20 -static int armv6_1156_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv6pmu_init(cpu_pmu); - cpu_pmu->name =3D "armv6_1156"; - return 0; -} - static int armv6_1176_pmu_init(struct arm_pmu *cpu_pmu) { armv6pmu_init(cpu_pmu); @@ -421,17 +414,9 @@ static const struct of_device_id armv6_pmu_of_device_i= ds[] =3D { { /* sentinel value */ } }; =20 -static const struct pmu_probe_info armv6_pmu_probe_table[] =3D { - ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init), - ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init), - ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init), - { /* sentinel value */ } -}; - static int armv6_pmu_device_probe(struct platform_device *pdev) { - return arm_pmu_device_probe(pdev, armv6_pmu_of_device_ids, - armv6_pmu_probe_table); + return arm_pmu_device_probe(pdev, armv6_pmu_of_device_ids, NULL); } =20 static struct platform_driver armv6_pmu_driver =3D { diff --git a/drivers/perf/arm_v7_pmu.c b/drivers/perf/arm_v7_pmu.c index fdd936fbd188..928ac3d626ed 100644 --- a/drivers/perf/arm_v7_pmu.c +++ b/drivers/perf/arm_v7_pmu.c @@ -1977,17 +1977,9 @@ static const struct of_device_id armv7_pmu_of_device= _ids[] =3D { {}, }; =20 -static const struct pmu_probe_info armv7_pmu_probe_table[] =3D { - ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init), - ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init), - { /* sentinel value */ } -}; - - static int armv7_pmu_device_probe(struct platform_device *pdev) { - return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, - armv7_pmu_probe_table); + return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, NULL); } =20 static struct platform_driver armv7_pmu_driver =3D { --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56E8E1552FE; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lNcY58s/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DDD7C2BBFC; Fri, 7 Jun 2024 20:32:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792327; bh=Kh3hE+1Gs+zXanDUXgcZshpNG3gFdrLfk06vy2eXTqg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lNcY58s/uDW/WxxDrRVPAGaP3/klN9jQ4olwzRdIQ6s8JkboXuf7ssp/WU0NTmKZs cV2tAAbDJjm7flpE85JsszWpa0mnprEC3oxXkX/Ra4Uw2tYTXGodu2gPfPAz47y2IE FEEu71K2DjIQqtWFrLxZIFNXapAH9nLGODuLyKf3XxY6YtCOWtW3XlkMWRAoCVy0c0 wlJNSbQQt6naBeOgZaSa3Hxbdgfcx62+dB/8XR+XrX8fCnO/4b871TdZ27RqoeappS UYl4osRKMmr96JYirBqcIZaCe/yhpd+WxnJrCfcatjuThwco95kjP3NzKS/QV73rG6 ekFzRycTEl4Og== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:28 -0600 Subject: [PATCH 3/9] perf: arm_pmu: Remove event index to counter remapping Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-3-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev Xscale and Armv6 PMUs defined the cycle counter at 0 and event counters starting at 1 and had 1:1 event index to counter numbering. On Armv7 and later, this changed the cycle counter to 31 and event counters start at 0. The drivers for Armv7 and PMUv3 kept the old event index numbering and introduced an event index to counter conversion. The conversion uses masking to convert from event index to a counter number. This operation relies on having at most 32 counters so that the cycle counter index 0 can be transformed to counter number 31. Armv9.4 adds support for an additional fixed function counter (instructions) which increases possible counters to more than 32, and the conversion won't work anymore as a simple subtract and mask. The primary reason for the translation (other than history) seems to be to have a contiguous mask of counters 0-N. Keeping that would result in more complicated index to counter conversions. Instead, store a mask of available counters rather than just number of events. That provides more information in addition to the number of events. No (intended) functional changes. Signed-off-by: Rob Herring (Arm) --- arch/arm64/kvm/pmu-emul.c | 6 ++-- drivers/perf/arm_pmu.c | 11 ++++--- drivers/perf/arm_pmuv3.c | 57 ++++++++++---------------------- drivers/perf/arm_v6_pmu.c | 6 ++-- drivers/perf/arm_v7_pmu.c | 77 ++++++++++++++++-----------------------= ---- drivers/perf/arm_xscale_pmu.c | 12 ++++--- include/linux/perf/arm_pmu.h | 2 +- 7 files changed, 69 insertions(+), 102 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index a35ce10e0a9f..da5ba9d061e8 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -911,10 +911,10 @@ u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm) struct arm_pmu *arm_pmu =3D kvm->arch.arm_pmu; =20 /* - * The arm_pmu->num_events considers the cycle counter as well. - * Ignore that and return only the general-purpose counters. + * The arm_pmu->cntr_mask considers the fixed counter(s) as well. + * Ignore those and return only the general-purpose counters. */ - return arm_pmu->num_events - 1; + return bitmap_weight(arm_pmu->cntr_mask, 31); } =20 static void kvm_arm_set_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 8458fe2cebb4..398cce3d76fc 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -522,7 +522,7 @@ static void armpmu_enable(struct pmu *pmu) { struct arm_pmu *armpmu =3D to_arm_pmu(pmu); struct pmu_hw_events *hw_events =3D this_cpu_ptr(armpmu->hw_events); - bool enabled =3D !bitmap_empty(hw_events->used_mask, armpmu->num_events); + bool enabled =3D !bitmap_empty(hw_events->used_mask, ARMPMU_MAX_HWEVENTS); =20 /* For task-bound events we may be called on other CPUs */ if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) @@ -742,7 +742,7 @@ static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, un= signed long cmd) struct perf_event *event; int idx; =20 - for (idx =3D 0; idx < armpmu->num_events; idx++) { + for_each_set_bit(idx, armpmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { event =3D hw_events->events[idx]; if (!event) continue; @@ -772,7 +772,7 @@ static int cpu_pm_pmu_notify(struct notifier_block *b, = unsigned long cmd, { struct arm_pmu *armpmu =3D container_of(b, struct arm_pmu, cpu_pm_nb); struct pmu_hw_events *hw_events =3D this_cpu_ptr(armpmu->hw_events); - bool enabled =3D !bitmap_empty(hw_events->used_mask, armpmu->num_events); + bool enabled =3D !bitmap_empty(hw_events->used_mask, ARMPMU_MAX_HWEVENTS); =20 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) return NOTIFY_DONE; @@ -924,8 +924,9 @@ int armpmu_register(struct arm_pmu *pmu) if (ret) goto out_destroy; =20 - pr_info("enabled with %s PMU driver, %d counters available%s\n", - pmu->name, pmu->num_events, + pr_info("enabled with %s PMU driver, %d (%*pb) counters available%s\n", + pmu->name, bitmap_weight(pmu->cntr_mask, ARMPMU_MAX_HWEVENTS), + ARMPMU_MAX_HWEVENTS, &pmu->cntr_mask, has_nmi ? ", using NMIs" : ""); =20 kvm_host_pmu_init(pmu); diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 23fa6c5da82c..80202346fc7a 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -451,9 +451,7 @@ static const struct attribute_group armv8_pmuv3_caps_at= tr_group =3D { /* * Perf Events' indices */ -#define ARMV8_IDX_CYCLE_COUNTER 0 -#define ARMV8_IDX_COUNTER0 1 -#define ARMV8_IDX_CYCLE_COUNTER_USER 32 +#define ARMV8_IDX_CYCLE_COUNTER 31 =20 /* * We unconditionally enable ARMv8.5-PMU long event counter support @@ -492,13 +490,6 @@ static bool armv8pmu_event_is_chained(struct perf_even= t *event) /* * ARMv8 low level PMU access */ - -/* - * Perf Event to low level counters mapping - */ -#define ARMV8_IDX_TO_COUNTER(x) \ - (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK) - static u64 armv8pmu_pmcr_read(void) { return read_pmcr(); @@ -518,14 +509,12 @@ static int armv8pmu_has_overflowed(u32 pmovsr) =20 static int armv8pmu_counter_has_overflowed(u32 pmnc, int idx) { - return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx)); + return pmnc & BIT(idx); } =20 static u64 armv8pmu_read_evcntr(int idx) { - u32 counter =3D ARMV8_IDX_TO_COUNTER(idx); - - return read_pmevcntrn(counter); + return read_pmevcntrn(idx); } =20 static u64 armv8pmu_read_hw_counter(struct perf_event *event) @@ -592,9 +581,7 @@ static u64 armv8pmu_read_counter(struct perf_event *eve= nt) =20 static void armv8pmu_write_evcntr(int idx, u64 value) { - u32 counter =3D ARMV8_IDX_TO_COUNTER(idx); - - write_pmevcntrn(counter, value); + write_pmevcntrn(idx, value); } =20 static void armv8pmu_write_hw_counter(struct perf_event *event, @@ -625,7 +612,6 @@ static void armv8pmu_write_counter(struct perf_event *e= vent, u64 value) =20 static void armv8pmu_write_evtype(int idx, unsigned long val) { - u32 counter =3D ARMV8_IDX_TO_COUNTER(idx); unsigned long mask =3D ARMV8_PMU_EVTYPE_EVENT | ARMV8_PMU_INCLUDE_EL2 | ARMV8_PMU_EXCLUDE_EL0 | @@ -635,7 +621,7 @@ static void armv8pmu_write_evtype(int idx, unsigned lon= g val) mask |=3D ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; =20 val &=3D mask; - write_pmevtypern(counter, val); + write_pmevtypern(idx, val); } =20 static void armv8pmu_write_event_type(struct perf_event *event) @@ -664,7 +650,7 @@ static void armv8pmu_write_event_type(struct perf_event= *event) =20 static u32 armv8pmu_event_cnten_mask(struct perf_event *event) { - int counter =3D ARMV8_IDX_TO_COUNTER(event->hw.idx); + int counter =3D event->hw.idx; u32 mask =3D BIT(counter); =20 if (armv8pmu_event_is_chained(event)) @@ -723,8 +709,7 @@ static void armv8pmu_enable_intens(u32 mask) =20 static void armv8pmu_enable_event_irq(struct perf_event *event) { - u32 counter =3D ARMV8_IDX_TO_COUNTER(event->hw.idx); - armv8pmu_enable_intens(BIT(counter)); + armv8pmu_enable_intens(BIT(event->hw.idx)); } =20 static void armv8pmu_disable_intens(u32 mask) @@ -738,8 +723,7 @@ static void armv8pmu_disable_intens(u32 mask) =20 static void armv8pmu_disable_event_irq(struct perf_event *event) { - u32 counter =3D ARMV8_IDX_TO_COUNTER(event->hw.idx); - armv8pmu_disable_intens(BIT(counter)); + armv8pmu_disable_intens(BIT(event->hw.idx)); } =20 static u32 armv8pmu_getreset_flags(void) @@ -783,7 +767,7 @@ static void armv8pmu_enable_user_access(struct arm_pmu = *cpu_pmu) struct pmu_hw_events *cpuc =3D this_cpu_ptr(cpu_pmu->hw_events); =20 /* Clear any unused counters to avoid leaking their contents */ - for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) { + for_each_clear_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { if (i =3D=3D ARMV8_IDX_CYCLE_COUNTER) write_pmccntr(0); else @@ -866,7 +850,7 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *= cpu_pmu) * to prevent skews in group events. */ armv8pmu_stop(cpu_pmu); - for (idx =3D 0; idx < cpu_pmu->num_events; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { struct perf_event *event =3D cpuc->events[idx]; struct hw_perf_event *hwc; =20 @@ -905,7 +889,7 @@ static int armv8pmu_get_single_idx(struct pmu_hw_events= *cpuc, { int idx; =20 - for (idx =3D ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, 31) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -921,7 +905,9 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events = *cpuc, * Chaining requires two consecutive event counters, where * the lower idx must be even. */ - for (idx =3D ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx +=3D = 2) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, 31) { + if (!(idx & 0x1)) + continue; if (!test_and_set_bit(idx, cpuc->used_mask)) { /* Check if the preceding even counter is available */ if (!test_and_set_bit(idx - 1, cpuc->used_mask)) @@ -974,15 +960,7 @@ static int armv8pmu_user_event_idx(struct perf_event *= event) if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event)) return 0; =20 - /* - * We remap the cycle counter index to 32 to - * match the offset applied to the rest of - * the counter indices. - */ - if (event->hw.idx =3D=3D ARMV8_IDX_CYCLE_COUNTER) - return ARMV8_IDX_CYCLE_COUNTER_USER; - - return event->hw.idx; + return event->hw.idx + 1; } =20 /* @@ -1207,10 +1185,11 @@ static void __armv8pmu_probe_pmu(void *info) probe->present =3D true; =20 /* Read the nb of CNTx counters supported from PMNC */ - cpu_pmu->num_events =3D FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read()); + bitmap_set(cpu_pmu->cntr_mask, + 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read())); =20 /* Add the CPU cycles counter */ - cpu_pmu->num_events +=3D 1; + bitmap_set(cpu_pmu->cntr_mask, ARMV8_IDX_CYCLE_COUNTER, 1); =20 pmceid[0] =3D pmceid_raw[0] =3D read_pmceid0(); pmceid[1] =3D pmceid_raw[1] =3D read_pmceid1(); diff --git a/drivers/perf/arm_v6_pmu.c b/drivers/perf/arm_v6_pmu.c index 0bb685b4bac5..b09615bb2bb2 100644 --- a/drivers/perf/arm_v6_pmu.c +++ b/drivers/perf/arm_v6_pmu.c @@ -64,6 +64,7 @@ enum armv6_counters { ARMV6_CYCLE_COUNTER =3D 0, ARMV6_COUNTER0, ARMV6_COUNTER1, + ARMV6_NUM_COUNTERS }; =20 /* @@ -254,7 +255,7 @@ armv6pmu_handle_irq(struct arm_pmu *cpu_pmu) */ armv6_pmcr_write(pmcr); =20 - for (idx =3D 0; idx < cpu_pmu->num_events; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV6_NUM_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct hw_perf_event *hwc; =20 @@ -391,7 +392,8 @@ static void armv6pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->start =3D armv6pmu_start; cpu_pmu->stop =3D armv6pmu_stop; cpu_pmu->map_event =3D armv6_map_event; - cpu_pmu->num_events =3D 3; + + bitmap_set(cpu_pmu->cntr_mask, 0, ARMV6_NUM_COUNTERS); } =20 static int armv6_1136_pmu_init(struct arm_pmu *cpu_pmu) diff --git a/drivers/perf/arm_v7_pmu.c b/drivers/perf/arm_v7_pmu.c index 928ac3d626ed..d815fcde7d84 100644 --- a/drivers/perf/arm_v7_pmu.c +++ b/drivers/perf/arm_v7_pmu.c @@ -649,24 +649,12 @@ static struct attribute_group armv7_pmuv2_events_attr= _group =3D { /* * Perf Events' indices */ -#define ARMV7_IDX_CYCLE_COUNTER 0 -#define ARMV7_IDX_COUNTER0 1 -#define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \ - (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) - -#define ARMV7_MAX_COUNTERS 32 -#define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1) - +#define ARMV7_IDX_CYCLE_COUNTER 31 +#define ARMV7_IDX_COUNTER_MAX 31 /* * ARMv7 low level PMNC access */ =20 -/* - * Perf Event to low level counters mapping - */ -#define ARMV7_IDX_TO_COUNTER(x) \ - (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK) - /* * Per-CPU PMNC: config reg */ @@ -725,19 +713,17 @@ static inline int armv7_pmnc_has_overflowed(u32 pmnc) =20 static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int id= x) { - return idx >=3D ARMV7_IDX_CYCLE_COUNTER && - idx <=3D ARMV7_IDX_COUNTER_LAST(cpu_pmu); + return test_bit(idx, cpu_pmu->cntr_mask); } =20 static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx) { - return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx)); + return pmnc & BIT(idx); } =20 static inline void armv7_pmnc_select_counter(int idx) { - u32 counter =3D ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); + asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (idx)); isb(); } =20 @@ -787,29 +773,25 @@ static inline void armv7_pmnc_write_evtsel(int idx, u= 32 val) =20 static inline void armv7_pmnc_enable_counter(int idx) { - u32 counter =3D ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); + asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(idx))); } =20 static inline void armv7_pmnc_disable_counter(int idx) { - u32 counter =3D ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); + asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(idx))); } =20 static inline void armv7_pmnc_enable_intens(int idx) { - u32 counter =3D ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); + asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(idx))); } =20 static inline void armv7_pmnc_disable_intens(int idx) { - u32 counter =3D ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); + asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(idx))); isb(); /* Clear the overflow flag in case an interrupt is pending. */ - asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); + asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(idx))); isb(); } =20 @@ -853,15 +835,12 @@ static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_= pmu) asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=3Dr" (val)); pr_info("CCNT =3D0x%08x\n", val); =20 - for (cnt =3D ARMV7_IDX_COUNTER0; - cnt <=3D ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) { + for_each_set_bit(cnt, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { armv7_pmnc_select_counter(cnt); asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=3Dr" (val)); - pr_info("CNT[%d] count =3D0x%08x\n", - ARMV7_IDX_TO_COUNTER(cnt), val); + pr_info("CNT[%d] count =3D0x%08x\n", cnt, val); asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=3Dr" (val)); - pr_info("CNT[%d] evtsel=3D0x%08x\n", - ARMV7_IDX_TO_COUNTER(cnt), val); + pr_info("CNT[%d] evtsel=3D0x%08x\n", cnt, val); } } #endif @@ -958,7 +937,7 @@ static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *= cpu_pmu) */ regs =3D get_irq_regs(); =20 - for (idx =3D 0; idx < cpu_pmu->num_events; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { struct perf_event *event =3D cpuc->events[idx]; struct hw_perf_event *hwc; =20 @@ -1027,7 +1006,7 @@ static int armv7pmu_get_event_idx(struct pmu_hw_event= s *cpuc, * For anything other than a cycle counter, try and use * the events counters */ - for (idx =3D ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -1073,7 +1052,7 @@ static int armv7pmu_set_event_filter(struct hw_perf_e= vent *event, static void armv7pmu_reset(void *info) { struct arm_pmu *cpu_pmu =3D (struct arm_pmu *)info; - u32 idx, nb_cnt =3D cpu_pmu->num_events, val; + u32 idx, val; =20 if (cpu_pmu->secure_access) { asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=3Dr" (val)); @@ -1082,7 +1061,7 @@ static void armv7pmu_reset(void *info) } =20 /* The counter and interrupt enable registers are unknown at reset. */ - for (idx =3D ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { armv7_pmnc_disable_counter(idx); armv7_pmnc_disable_intens(idx); } @@ -1161,20 +1140,22 @@ static void armv7pmu_init(struct arm_pmu *cpu_pmu) =20 static void armv7_read_num_pmnc_events(void *info) { - int *nb_cnt =3D info; + int nb_cnt; + struct arm_pmu *cpu_pmu =3D info; =20 /* Read the nb of CNTx counters supported from PMNC */ - *nb_cnt =3D (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; + nb_cnt =3D (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; + bitmap_set(cpu_pmu->cntr_mask, 0, nb_cnt); =20 /* Add the CPU cycles counter */ - *nb_cnt +=3D 1; + bitmap_set(cpu_pmu->cntr_mask, ARMV7_IDX_CYCLE_COUNTER, 1); } =20 static int armv7_probe_num_events(struct arm_pmu *arm_pmu) { return smp_call_function_any(&arm_pmu->supported_cpus, armv7_read_num_pmnc_events, - &arm_pmu->num_events, 1); + arm_pmu, 1); } =20 static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) @@ -1524,7 +1505,7 @@ static void krait_pmu_reset(void *info) { u32 vval, fval; struct arm_pmu *cpu_pmu =3D info; - u32 idx, nb_cnt =3D cpu_pmu->num_events; + u32 idx; =20 armv7pmu_reset(info); =20 @@ -1538,7 +1519,7 @@ static void krait_pmu_reset(void *info) venum_post_pmresr(vval, fval); =20 /* Reset PMxEVNCTCR to sane default */ - for (idx =3D ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { armv7_pmnc_select_counter(idx); asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); } @@ -1562,7 +1543,7 @@ static int krait_event_to_bit(struct perf_event *even= t, unsigned int region, * Lower bits are reserved for use by the counters (see * armv7pmu_get_event_idx() for more info) */ - bit +=3D ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; + bit +=3D bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); =20 return bit; } @@ -1845,7 +1826,7 @@ static void scorpion_pmu_reset(void *info) { u32 vval, fval; struct arm_pmu *cpu_pmu =3D info; - u32 idx, nb_cnt =3D cpu_pmu->num_events; + u32 idx; =20 armv7pmu_reset(info); =20 @@ -1860,7 +1841,7 @@ static void scorpion_pmu_reset(void *info) venum_post_pmresr(vval, fval); =20 /* Reset PMxEVNCTCR to sane default */ - for (idx =3D ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { armv7_pmnc_select_counter(idx); asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); } @@ -1883,7 +1864,7 @@ static int scorpion_event_to_bit(struct perf_event *e= vent, unsigned int region, * Lower bits are reserved for use by the counters (see * armv7pmu_get_event_idx() for more info) */ - bit +=3D ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; + bit +=3D bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); =20 return bit; } diff --git a/drivers/perf/arm_xscale_pmu.c b/drivers/perf/arm_xscale_pmu.c index 3d8b72d6b37f..e075df521350 100644 --- a/drivers/perf/arm_xscale_pmu.c +++ b/drivers/perf/arm_xscale_pmu.c @@ -52,6 +52,8 @@ enum xscale_counters { XSCALE_COUNTER1, XSCALE_COUNTER2, XSCALE_COUNTER3, + XSCALE2_NUM_COUNTERS, + XSCALE_NUM_COUNTERS =3D 3, }; =20 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] =3D { @@ -168,7 +170,7 @@ xscale1pmu_handle_irq(struct arm_pmu *cpu_pmu) =20 regs =3D get_irq_regs(); =20 - for (idx =3D 0; idx < cpu_pmu->num_events; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, XSCALE_NUM_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct hw_perf_event *hwc; =20 @@ -364,7 +366,8 @@ static int xscale1pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->start =3D xscale1pmu_start; cpu_pmu->stop =3D xscale1pmu_stop; cpu_pmu->map_event =3D xscale_map_event; - cpu_pmu->num_events =3D 3; + + bitmap_set(cpu_pmu->cntr_mask, 0, XSCALE_NUM_COUNTERS); =20 return 0; } @@ -500,7 +503,7 @@ xscale2pmu_handle_irq(struct arm_pmu *cpu_pmu) =20 regs =3D get_irq_regs(); =20 - for (idx =3D 0; idx < cpu_pmu->num_events; ++idx) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, XSCALE2_NUM_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct hw_perf_event *hwc; =20 @@ -719,7 +722,8 @@ static int xscale2pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->start =3D xscale2pmu_start; cpu_pmu->stop =3D xscale2pmu_stop; cpu_pmu->map_event =3D xscale_map_event; - cpu_pmu->num_events =3D 5; + + bitmap_set(cpu_pmu->cntr_mask, 0, XSCALE2_NUM_COUNTERS); =20 return 0; } diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index b3b34f6670cf..e5d6d204beab 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -96,7 +96,7 @@ struct arm_pmu { void (*stop)(struct arm_pmu *); void (*reset)(void *); int (*map_event)(struct perf_event *event); - int num_events; + DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS); bool secure_access; /* 32-bit ARM only */ #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBDF7155327; Fri, 7 Jun 2024 20:32:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792328; cv=none; b=EQS/eMnDwB5MvjjmiQApG6qfC2V3IPwWvelHvUkzUiisIAGm5yEvmyrnEEuOrF5CyuE5j8m1bbj2zKY1dxlPz9SFu31px/mU2fSWxDWpaBAMGEOhogxLzOH9KxrElEkVKfE29TeRhIIPtsW/9RaWFeYWjPbVSLB7ors/nKVywjo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792328; c=relaxed/simple; bh=jv6I//u4kiy067WM9j7nQpCzNmt/EmG8L431w65kapY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jlDQd8X756biyqWvvIvTFViU/uu17fEqphXMP6hjLFckglcybnvfsG0feFlKreUKhVu4H9NIhfEwFQ5zw2BGoGTilfv3Euwm9BPDJQxquMLLIAxVTVwJnNixm7EnR9CxL5v6L/VJVzzsYTcmIAm6WEY61qowETWzHj8zrjCDF5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cz9RAujV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cz9RAujV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B8C0C32781; Fri, 7 Jun 2024 20:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792328; bh=jv6I//u4kiy067WM9j7nQpCzNmt/EmG8L431w65kapY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Cz9RAujVRSVykG84xKGt8jox6CwAksYwFMYQGYPLBNKI4RyESrKOl9rAznxRB47KM +BQps0kvmLwkh6e5H2bV94JWS4qwNiRd/+wbu1kP46lphWQRDitlgpvNCV/L/Rmc1z GCSniEHpQgXtvHp+cDbyxbHXsp46G4UvjXkG+Heehu2V+aWv4EB5jcBB0EkxVGFIg+ nhU9QFLQwHouPSXo5ziMa+uGLX1TIfIlQwU64umB9/98fFQs81lHUshVlXdcqAkEq7 a7r+NNfR8gLTcNLaQQVKaNqF21UbjqN4LC5+Kc3xXRKMmyuoLJOn12us2BALeBmZ48 /OxxcxkSKFuKw== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:29 -0600 Subject: [PATCH 4/9] perf: arm_pmuv3: Prepare for more than 32 counters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-4-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev Various PMUv3 registers which are a mask of counters are 64-bit registers, but the accessor functions take a u32. This has been fine as the upper 32-bits have been RES0 as there has been a maximum of 32 counters prior to Armv9.4/8.9. With Armv9.4/8.9, a 33rd counter is added. Update the accessor functions to use a u64 instead. Signed-off-by: Rob Herring (Arm) Acked-by: Mark Rutland --- arch/arm64/include/asm/arm_pmuv3.h | 12 ++++++------ arch/arm64/include/asm/kvm_host.h | 8 ++++---- arch/arm64/kvm/pmu.c | 8 ++++---- drivers/perf/arm_pmuv3.c | 40 ++++++++++++++++++++--------------= ---- include/kvm/arm_pmu.h | 4 ++-- 5 files changed, 37 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/ar= m_pmuv3.h index c27404fa4418..e96ce7900fc7 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -71,22 +71,22 @@ static inline u64 read_pmccntr(void) return read_sysreg(pmccntr_el0); } =20 -static inline void write_pmcntenset(u32 val) +static inline void write_pmcntenset(u64 val) { write_sysreg(val, pmcntenset_el0); } =20 -static inline void write_pmcntenclr(u32 val) +static inline void write_pmcntenclr(u64 val) { write_sysreg(val, pmcntenclr_el0); } =20 -static inline void write_pmintenset(u32 val) +static inline void write_pmintenset(u64 val) { write_sysreg(val, pmintenset_el1); } =20 -static inline void write_pmintenclr(u32 val) +static inline void write_pmintenclr(u64 val) { write_sysreg(val, pmintenclr_el1); } @@ -96,12 +96,12 @@ static inline void write_pmccfiltr(u64 val) write_sysreg(val, pmccfiltr_el0); } =20 -static inline void write_pmovsclr(u32 val) +static inline void write_pmovsclr(u64 val) { write_sysreg(val, pmovsclr_el0); } =20 -static inline u32 read_pmovsclr(void) +static inline u64 read_pmovsclr(void) { return read_sysreg(pmovsclr_el0); } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 8170c04fde91..6243a01d9d26 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1267,12 +1267,12 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kv= m_vcpu *vcpu); void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); =20 #ifdef CONFIG_KVM -void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); -void kvm_clr_pmu_events(u32 clr); +void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); +void kvm_clr_pmu_events(u64 clr); bool kvm_set_pmuserenr(u64 val); #else -static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *att= r) {} -static inline void kvm_clr_pmu_events(u32 clr) {} +static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *att= r) {} +static inline void kvm_clr_pmu_events(u64 clr) {} static inline bool kvm_set_pmuserenr(u64 val) { return false; diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index 329819806096..e633b4434c6a 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -35,7 +35,7 @@ struct kvm_pmu_events *kvm_get_pmu_events(void) * Add events to track that we may want to switch at guest entry/exit * time. */ -void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) +void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) { struct kvm_pmu_events *pmu =3D kvm_get_pmu_events(); =20 @@ -51,7 +51,7 @@ void kvm_set_pmu_events(u32 set, struct perf_event_attr *= attr) /* * Stop tracking events */ -void kvm_clr_pmu_events(u32 clr) +void kvm_clr_pmu_events(u64 clr) { struct kvm_pmu_events *pmu =3D kvm_get_pmu_events(); =20 @@ -176,7 +176,7 @@ static void kvm_vcpu_pmu_disable_el0(unsigned long even= ts) void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) { struct kvm_pmu_events *pmu; - u32 events_guest, events_host; + u64 events_guest, events_host; =20 if (!kvm_arm_support_pmu_v3() || !has_vhe()) return; @@ -197,7 +197,7 @@ void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) { struct kvm_pmu_events *pmu; - u32 events_guest, events_host; + u64 events_guest, events_host; =20 if (!kvm_arm_support_pmu_v3() || !has_vhe()) return; diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 80202346fc7a..3b49144f3a58 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -502,14 +502,14 @@ static void armv8pmu_pmcr_write(u64 val) write_pmcr(val); } =20 -static int armv8pmu_has_overflowed(u32 pmovsr) +static int armv8pmu_has_overflowed(u64 pmovsr) { - return pmovsr & ARMV8_PMU_OVERFLOWED_MASK; + return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK); } =20 -static int armv8pmu_counter_has_overflowed(u32 pmnc, int idx) +static int armv8pmu_counter_has_overflowed(u64 pmnc, int idx) { - return pmnc & BIT(idx); + return !!(pmnc & BIT(idx)); } =20 static u64 armv8pmu_read_evcntr(int idx) @@ -648,17 +648,17 @@ static void armv8pmu_write_event_type(struct perf_eve= nt *event) } } =20 -static u32 armv8pmu_event_cnten_mask(struct perf_event *event) +static u64 armv8pmu_event_cnten_mask(struct perf_event *event) { int counter =3D event->hw.idx; - u32 mask =3D BIT(counter); + u64 mask =3D BIT(counter); =20 if (armv8pmu_event_is_chained(event)) mask |=3D BIT(counter - 1); return mask; } =20 -static void armv8pmu_enable_counter(u32 mask) +static void armv8pmu_enable_counter(u64 mask) { /* * Make sure event configuration register writes are visible before we @@ -671,7 +671,7 @@ static void armv8pmu_enable_counter(u32 mask) static void armv8pmu_enable_event_counter(struct perf_event *event) { struct perf_event_attr *attr =3D &event->attr; - u32 mask =3D armv8pmu_event_cnten_mask(event); + u64 mask =3D armv8pmu_event_cnten_mask(event); =20 kvm_set_pmu_events(mask, attr); =20 @@ -680,7 +680,7 @@ static void armv8pmu_enable_event_counter(struct perf_e= vent *event) armv8pmu_enable_counter(mask); } =20 -static void armv8pmu_disable_counter(u32 mask) +static void armv8pmu_disable_counter(u64 mask) { write_pmcntenclr(mask); /* @@ -693,7 +693,7 @@ static void armv8pmu_disable_counter(u32 mask) static void armv8pmu_disable_event_counter(struct perf_event *event) { struct perf_event_attr *attr =3D &event->attr; - u32 mask =3D armv8pmu_event_cnten_mask(event); + u64 mask =3D armv8pmu_event_cnten_mask(event); =20 kvm_clr_pmu_events(mask); =20 @@ -702,7 +702,7 @@ static void armv8pmu_disable_event_counter(struct perf_= event *event) armv8pmu_disable_counter(mask); } =20 -static void armv8pmu_enable_intens(u32 mask) +static void armv8pmu_enable_intens(u64 mask) { write_pmintenset(mask); } @@ -712,7 +712,7 @@ static void armv8pmu_enable_event_irq(struct perf_event= *event) armv8pmu_enable_intens(BIT(event->hw.idx)); } =20 -static void armv8pmu_disable_intens(u32 mask) +static void armv8pmu_disable_intens(u64 mask) { write_pmintenclr(mask); isb(); @@ -726,9 +726,9 @@ static void armv8pmu_disable_event_irq(struct perf_even= t *event) armv8pmu_disable_intens(BIT(event->hw.idx)); } =20 -static u32 armv8pmu_getreset_flags(void) +static u64 armv8pmu_getreset_flags(void) { - u32 value; + u64 value; =20 /* Read */ value =3D read_pmovsclr(); @@ -823,7 +823,7 @@ static void armv8pmu_stop(struct arm_pmu *cpu_pmu) =20 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) { - u32 pmovsr; + u64 pmovsr; struct perf_sample_data data; struct pmu_hw_events *cpuc =3D this_cpu_ptr(cpu_pmu->hw_events); struct pt_regs *regs; @@ -1035,14 +1035,16 @@ static int armv8pmu_set_event_filter(struct hw_perf= _event *event, static void armv8pmu_reset(void *info) { struct arm_pmu *cpu_pmu =3D (struct arm_pmu *)info; - u64 pmcr; + u64 pmcr, mask; + + bitmap_to_arr64(&mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS); =20 /* The counter and interrupt enable registers are unknown at reset. */ - armv8pmu_disable_counter(U32_MAX); - armv8pmu_disable_intens(U32_MAX); + armv8pmu_disable_counter(mask); + armv8pmu_disable_intens(mask); =20 /* Clear the counters we flip at guest entry/exit */ - kvm_clr_pmu_events(U32_MAX); + kvm_clr_pmu_events(mask); =20 /* * Initialize & Reset PMNC. Request overflow interrupt for diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 35d4ca4f6122..334d7c5503cf 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -19,8 +19,8 @@ struct kvm_pmc { }; =20 struct kvm_pmu_events { - u32 events_host; - u32 events_guest; + u64 events_host; + u64 events_guest; }; =20 struct kvm_pmu { --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FDC514F9E6; Fri, 7 Jun 2024 20:32:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792330; cv=none; b=bM98k7Rvi0SO+VO7nxIKu/J6Aa6H2UwI49JYnJ70+jmff/YQ9WSybpCMDMiwEunAjAW28NW52HjFABi08mxdBwrqy3DIFsjP16jDEY+NtNhPXIA/XmoyL3pu10QI5HBFH52nYOpv/BTWJgLMnxyrPhfpdaUe9ZLytZH2T8gcgyA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717792330; c=relaxed/simple; bh=So81qq/+gb60JLTHqTChOcgxxJijDT58nbB4wbQsq8g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DaCVuXpwtCN7AObgYCVq6jE9/D9qxrpfUhFAzxN03ZBw6sPRffjtQfbUxivK3ywJkqplm9iRS8aR4xd+SeRPKY2gAwB95/tguEmDwgZe28qoD3+8/XRBGRTQ4ZgOHp14Cawg6gvKxjC74uihcPguB7LXmrzeo2BvTQrAb7qLgRo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Os1O+c6P; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Os1O+c6P" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D3F6BC4AF07; Fri, 7 Jun 2024 20:32:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792330; bh=So81qq/+gb60JLTHqTChOcgxxJijDT58nbB4wbQsq8g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Os1O+c6PV6nohVgamceFCl6xwUO8m7/6KNsOfJUC7H+ty7rcv5l/1uKzz1XeamcXT AFdNjPgF/bihI05aSyIVjWiocVYb00xiRYSeVQPhEZ91XABZF6cscgtuXtGHUeQ2ch wfSDyo4Pp5efW6HOQcoR2uRIMxxT3P7Bd24H7c9+8fEgOHis1OCcMVcC/gipitZRnz ZDQW4KTeHvpZaD1dvVa/WWZzajrFDBx+BUx7is/On+pxCDufrLq5BzfnbnaZ1UZMg5 yPl4iJmU/2x/MTvgBXE8+t0KrKuuK1/r03F+GhS6CgdVlep6UD+jUGGtl8SsrfxziH L2OceIbqjZ++Q== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:30 -0600 Subject: [PATCH 5/9] KVM: arm64: pmu: Use arm_pmuv3.h register accessors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-5-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev Commit df29ddf4f04b ("arm64: perf: Abstract system register accesses away") split off PMU register accessor functions to a standalone header. Let's use it for KVM PMU code and get rid one copy of the ugly switch macro. Signed-off-by: Rob Herring (Arm) Acked-by: Mark Rutland --- arch/arm64/include/asm/arm_pmuv3.h | 13 ++++++++ arch/arm64/kvm/pmu.c | 67 +++++-----------------------------= ---- 2 files changed, 22 insertions(+), 58 deletions(-) diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/ar= m_pmuv3.h index e96ce7900fc7..1ed91334fede 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -33,6 +33,14 @@ static inline void write_pmevtypern(int n, unsigned long= val) PMEVN_SWITCH(n, WRITE_PMEVTYPERN); } =20 +#define RETURN_READ_PMEVTYPERN(n) \ + return read_sysreg(pmevtyper##n##_el0) +static inline unsigned long read_pmevtypern(int n) +{ + PMEVN_SWITCH(n, RETURN_READ_PMEVTYPERN); + return 0; +} + static inline unsigned long read_pmmir(void) { return read_cpuid(PMMIR_EL1); @@ -96,6 +104,11 @@ static inline void write_pmccfiltr(u64 val) write_sysreg(val, pmccfiltr_el0); } =20 +static inline u64 read_pmccfiltr(void) +{ + return read_sysreg(pmccfiltr_el0); +} + static inline void write_pmovsclr(u64 val) { write_sysreg(val, pmovsclr_el0); diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index e633b4434c6a..01c9a9efdd1c 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -6,6 +6,8 @@ #include #include =20 +#include + static DEFINE_PER_CPU(struct kvm_pmu_events, kvm_pmu_events); =20 /* @@ -62,63 +64,16 @@ void kvm_clr_pmu_events(u64 clr) pmu->events_guest &=3D ~clr; } =20 -#define PMEVTYPER_READ_CASE(idx) \ - case idx: \ - return read_sysreg(pmevtyper##idx##_el0) - -#define PMEVTYPER_WRITE_CASE(idx) \ - case idx: \ - write_sysreg(val, pmevtyper##idx##_el0); \ - break - -#define PMEVTYPER_CASES(readwrite) \ - PMEVTYPER_##readwrite##_CASE(0); \ - PMEVTYPER_##readwrite##_CASE(1); \ - PMEVTYPER_##readwrite##_CASE(2); \ - PMEVTYPER_##readwrite##_CASE(3); \ - PMEVTYPER_##readwrite##_CASE(4); \ - PMEVTYPER_##readwrite##_CASE(5); \ - PMEVTYPER_##readwrite##_CASE(6); \ - PMEVTYPER_##readwrite##_CASE(7); \ - PMEVTYPER_##readwrite##_CASE(8); \ - PMEVTYPER_##readwrite##_CASE(9); \ - PMEVTYPER_##readwrite##_CASE(10); \ - PMEVTYPER_##readwrite##_CASE(11); \ - PMEVTYPER_##readwrite##_CASE(12); \ - PMEVTYPER_##readwrite##_CASE(13); \ - PMEVTYPER_##readwrite##_CASE(14); \ - PMEVTYPER_##readwrite##_CASE(15); \ - PMEVTYPER_##readwrite##_CASE(16); \ - PMEVTYPER_##readwrite##_CASE(17); \ - PMEVTYPER_##readwrite##_CASE(18); \ - PMEVTYPER_##readwrite##_CASE(19); \ - PMEVTYPER_##readwrite##_CASE(20); \ - PMEVTYPER_##readwrite##_CASE(21); \ - PMEVTYPER_##readwrite##_CASE(22); \ - PMEVTYPER_##readwrite##_CASE(23); \ - PMEVTYPER_##readwrite##_CASE(24); \ - PMEVTYPER_##readwrite##_CASE(25); \ - PMEVTYPER_##readwrite##_CASE(26); \ - PMEVTYPER_##readwrite##_CASE(27); \ - PMEVTYPER_##readwrite##_CASE(28); \ - PMEVTYPER_##readwrite##_CASE(29); \ - PMEVTYPER_##readwrite##_CASE(30) - /* * Read a value direct from PMEVTYPER where idx is 0-30 * or PMCCFILTR_EL0 where idx is ARMV8_PMU_CYCLE_IDX (31). */ static u64 kvm_vcpu_pmu_read_evtype_direct(int idx) { - switch (idx) { - PMEVTYPER_CASES(READ); - case ARMV8_PMU_CYCLE_IDX: - return read_sysreg(pmccfiltr_el0); - default: - WARN_ON(1); - } + if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) + return read_pmccfiltr(); =20 - return 0; + return read_pmevtypern(idx); } =20 /* @@ -127,14 +82,10 @@ static u64 kvm_vcpu_pmu_read_evtype_direct(int idx) */ static void kvm_vcpu_pmu_write_evtype_direct(int idx, u32 val) { - switch (idx) { - PMEVTYPER_CASES(WRITE); - case ARMV8_PMU_CYCLE_IDX: - write_sysreg(val, pmccfiltr_el0); - break; - default: - WARN_ON(1); - } + if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) + write_pmccfiltr(val); + else + write_pmevtypern(idx, val); } =20 /* --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE3561553B3; Fri, 7 Jun 2024 20:32:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 7 Jun 2024 20:32:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792331; bh=17s7vSwqMHxRakvVibGY5mJGrj06gq60Ot/dN3g7oE4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=aDPEBnH9NLeUYGjfwx3osqF0LmxCqyAbikVBzrj4G6ikVfzPK+sSyKoMUQCdEXk+r 3hsuIgwYr2vUA4mzSmfBh40bLNP87n8Pj0izjjbHa3BAH3uNJfddorZDets554XtSq 6Rh+H2EmApltvf3zKsRV1vWEBLdJM+4r7OUsW7y+OmD7I7MEGYcN8Ejh7ejHmM7fVZ E21xIdqtHrVX5Zp89YhWABjZGzVdfN9hTyg9z2G2DlBvYdMwPeJ4+zm/R/ZLG5gOXx DMBAlOeBAE3XVM+Jbc8CFuVUSUOFsjIo0TndVEVFZ+xvVzKSCqXjA5wPH6A9or43V7 Ji5hhE2OXSuJQ== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:31 -0600 Subject: [PATCH 6/9] KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-6-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev ARMV8_PMU_COUNTER_MASK is really a mask for the PMSELR_EL0.SEL register field. Make that clear by adding a standard sysreg definition for the register, and using it instead. Signed-off-by: Rob Herring (Arm) Acked-by: Mark Rutland Reviewed-by: Mark Rutland --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kvm/sys_regs.c | 10 +++++----- arch/arm64/tools/sysreg | 5 +++++ include/linux/perf/arm_pmuv3.h | 1 - 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index af3b206fa423..b0d6c33f9ecc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -403,7 +403,6 @@ #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) -#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 22b45a15d068..f8b5db48ea8a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -880,7 +880,7 @@ static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const= struct sys_reg_desc *r) static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *= r) { reset_unknown(vcpu, r); - __vcpu_sys_reg(vcpu, r->reg) &=3D ARMV8_PMU_COUNTER_MASK; + __vcpu_sys_reg(vcpu, r->reg) &=3D PMSELR_EL0_SEL_MASK; =20 return __vcpu_sys_reg(vcpu, r->reg); } @@ -972,7 +972,7 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct= sys_reg_params *p, else /* return PMSELR.SEL field */ p->regval =3D __vcpu_sys_reg(vcpu, PMSELR_EL0) - & ARMV8_PMU_COUNTER_MASK; + & PMSELR_EL0_SEL_MASK; =20 return true; } @@ -1040,8 +1040,8 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, if (pmu_access_event_counter_el0_disabled(vcpu)) return false; =20 - idx =3D __vcpu_sys_reg(vcpu, PMSELR_EL0) - & ARMV8_PMU_COUNTER_MASK; + idx =3D SYS_FIELD_GET(PMSELR_EL0, SEL, + __vcpu_sys_reg(vcpu, PMSELR_EL0)); } else if (r->Op2 =3D=3D 0) { /* PMCCNTR_EL0 */ if (pmu_access_cycle_counter_el0_disabled(vcpu)) @@ -1091,7 +1091,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,= struct sys_reg_params *p, =20 if (r->CRn =3D=3D 9 && r->CRm =3D=3D 13 && r->Op2 =3D=3D 1) { /* PMXEVTYPER_EL0 */ - idx =3D __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; + idx =3D SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); reg =3D PMEVTYPER0_EL0 + idx; } else if (r->CRn =3D=3D 14 && (r->CRm & 12) =3D=3D 12) { idx =3D ((r->CRm & 3) << 3) | (r->Op2 & 7); diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a4c1dd4741a4..231817a379b5 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2153,6 +2153,11 @@ Field 4 P Field 3:0 ALIGN EndSysreg =20 +Sysreg PMSELR_EL0 3 3 9 12 5 +Res0 63:5 +Field 4:0 SEL +EndSysreg + SysregFields CONTEXTIDR_ELx Res0 63:32 Field 31:0 PROCID diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index 46377e134d67..caa09241ad4f 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -7,7 +7,6 @@ #define __PERF_ARM_PMUV3_H =20 #define ARMV8_PMU_MAX_COUNTERS 32 -#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1) =20 /* * Common architectural and microarchitectural event numbers. --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 492DC155A47; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KAUj+VV4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A82C7C32782; Fri, 7 Jun 2024 20:32:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792332; bh=0PuD070n2iQEaU9GwC/6rdl3ex4y0laQrCuOVZ80ZSM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KAUj+VV4IljDqnnGXjXbzgTEJO9m2AWbY51T7niBiiXSJgW/4fkvZJuCOlqAw4X5G b+f5H1ZTXo9khnQEN7o/eSXMOUA7gVZtvCZ/xmPtpEnA3BYSrnh78upORearDd8rJ2 zzbzGpkbKLjh439z3pcJ1EI1BsWCl3Zpu9kw17GAC4P8A8husFUQk7yjjuK7ZKwLpS VJP2+OKt1hEUsUkUsTO10AJKd9vIkV3RDFO5bLiIt9Q3GF9YirLGQPxoqGX/8pU0vB RyFilF/uBjTzHtMYtvDNR5DNB3v6vNUq6mb3ItKcsqBTBRdxmMBaoFjh3hLzKfNOK3 W+ksPlXAkBgZw== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:32 -0600 Subject: [PATCH 7/9] arm64: perf/kvm: Use a common PMU cycle counter define Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-7-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev The PMUv3 and KVM code each have a define for the PMU cycle counter index. Move KVM's define to a shared location and use it for PMUv3 driver. Signed-off-by: Rob Herring (Arm) --- arch/arm/include/asm/arm_pmuv3.h | 2 ++ arch/arm64/include/asm/arm_pmuv3.h | 2 ++ arch/arm64/kvm/sys_regs.c | 1 + drivers/perf/arm_pmuv3.c | 23 +++++++++-------------- include/kvm/arm_pmu.h | 1 - 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pm= uv3.h index a41b503b7dcd..ac2cf37b57e3 100644 --- a/arch/arm/include/asm/arm_pmuv3.h +++ b/arch/arm/include/asm/arm_pmuv3.h @@ -9,6 +9,8 @@ #include #include =20 +#define ARMV8_PMU_CYCLE_IDX 31 + #define PMCCNTR __ACCESS_CP15_64(0, c9) =20 #define PMCR __ACCESS_CP15(c9, 0, c12, 0) diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/ar= m_pmuv3.h index 1ed91334fede..46930729fb3f 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -11,6 +11,8 @@ #include #include =20 +#define ARMV8_PMU_CYCLE_IDX 31 + #define RETURN_READ_PMEVCNTRN(n) \ return read_sysreg(pmevcntr##n##_el0) static inline unsigned long read_pmevcntrn(int n) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f8b5db48ea8a..22393ae7ce14 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -18,6 +18,7 @@ #include #include =20 +#include #include #include #include diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 3b49144f3a58..468a0a3bbd5a 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -448,11 +448,6 @@ static const struct attribute_group armv8_pmuv3_caps_a= ttr_group =3D { .attrs =3D armv8_pmuv3_caps_attrs, }; =20 -/* - * Perf Events' indices - */ -#define ARMV8_IDX_CYCLE_COUNTER 31 - /* * We unconditionally enable ARMv8.5-PMU long event counter support * (64-bit events) where supported. Indicate if this arm_pmu has long @@ -484,7 +479,7 @@ static bool armv8pmu_event_is_chained(struct perf_event= *event) return !armv8pmu_event_has_user_read(event) && armv8pmu_event_is_64bit(event) && !armv8pmu_has_long_event(cpu_pmu) && - (idx !=3D ARMV8_IDX_CYCLE_COUNTER); + (idx !=3D ARMV8_PMU_CYCLE_IDX); } =20 /* @@ -543,7 +538,7 @@ static bool armv8pmu_event_needs_bias(struct perf_event= *event) return false; =20 if (armv8pmu_has_long_event(cpu_pmu) || - idx =3D=3D ARMV8_IDX_CYCLE_COUNTER) + idx =3D=3D ARMV8_PMU_CYCLE_IDX) return true; =20 return false; @@ -571,7 +566,7 @@ static u64 armv8pmu_read_counter(struct perf_event *eve= nt) int idx =3D hwc->idx; u64 value; =20 - if (idx =3D=3D ARMV8_IDX_CYCLE_COUNTER) + if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) value =3D read_pmccntr(); else value =3D armv8pmu_read_hw_counter(event); @@ -604,7 +599,7 @@ static void armv8pmu_write_counter(struct perf_event *e= vent, u64 value) =20 value =3D armv8pmu_bias_long_counter(event, value); =20 - if (idx =3D=3D ARMV8_IDX_CYCLE_COUNTER) + if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) write_pmccntr(value); else armv8pmu_write_hw_counter(event, value); @@ -641,7 +636,7 @@ static void armv8pmu_write_event_type(struct perf_event= *event) armv8pmu_write_evtype(idx - 1, hwc->config_base); armv8pmu_write_evtype(idx, chain_evt); } else { - if (idx =3D=3D ARMV8_IDX_CYCLE_COUNTER) + if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) write_pmccfiltr(hwc->config_base); else armv8pmu_write_evtype(idx, hwc->config_base); @@ -768,7 +763,7 @@ static void armv8pmu_enable_user_access(struct arm_pmu = *cpu_pmu) =20 /* Clear any unused counters to avoid leaking their contents */ for_each_clear_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { - if (i =3D=3D ARMV8_IDX_CYCLE_COUNTER) + if (i =3D=3D ARMV8_PMU_CYCLE_IDX) write_pmccntr(0); else armv8pmu_write_evcntr(i, 0); @@ -928,8 +923,8 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events = *cpuc, =20 /* Always prefer to place a cycle counter into the cycle counter. */ if (evtype =3D=3D ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { - if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) - return ARMV8_IDX_CYCLE_COUNTER; + if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask)) + return ARMV8_PMU_CYCLE_IDX; else if (armv8pmu_event_is_64bit(event) && armv8pmu_event_want_user_access(event) && !armv8pmu_has_long_event(cpu_pmu)) @@ -1191,7 +1186,7 @@ static void __armv8pmu_probe_pmu(void *info) 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read())); =20 /* Add the CPU cycles counter */ - bitmap_set(cpu_pmu->cntr_mask, ARMV8_IDX_CYCLE_COUNTER, 1); + bitmap_set(cpu_pmu->cntr_mask, ARMV8_PMU_CYCLE_IDX, 1); =20 pmceid[0] =3D pmceid_raw[0] =3D read_pmceid0(); pmceid[1] =3D pmceid_raw[1] =3D read_pmceid1(); diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 334d7c5503cf..871067fb2616 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -10,7 +10,6 @@ #include #include =20 -#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1) =20 #if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM) struct kvm_pmc { --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EADAB15622F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VZkQ9mCP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 068B7C4AF19; Fri, 7 Jun 2024 20:32:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792334; bh=J5oFR+H4wsl5jwtJxa1F6XIK60SO7/dL0k4zTxfNnJU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VZkQ9mCPELqch99bhj9fGm3AHA9lhMvD5G2GMqborXIHRQOSnKOohBKeQe3nnNCGk hbBgxpgW1YZD/vPsJsYzRf3acBai3oJXjp/EXzlK+0jMyjKw8wxRjI4QisbCMgGACr v63rYBo1pUbiWQkoUVGbc+mCKn6MzOiAJXNTv6W/Aywq4tvbzzyxKxnBqdNL/xr1zi GT3Pk0cv7fGrbbL1Zm126O3YiwEqNWcX9WQk8vEqZ5KAZvOvRlg/fdlRrbJBA4wY6p V7HZ0ysUBp53srbB+TDLHX40mNjcwnVwCQpRJKEpUvKoNXdRFhKDBYTYDeE5c6HX52 pRGOYADtk7f4A== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:33 -0600 Subject: [PATCH 8/9] KVM: arm64: Refine PMU defines for number of counters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-8-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev There are 2 defines for the number of PMU counters: ARMV8_PMU_MAX_COUNTERS and ARMPMU_MAX_HWEVENTS. Both are the same currently, but Armv9.4/8.9 increases the number of possible counters from 32 to 33. With this change, the maximum number of counters will differ for KVM's PMU emulation which is PMUv3.4. Give KVM PMU emulation its own define to decouple it from the rest of the kernel's number PMU counters. The VHE PMU code needs to match the PMU driver, so switch it to use ARMPMU_MAX_HWEVENTS instead. Signed-off-by: Rob Herring (Arm) Acked-by: Mark Rutland --- arch/arm64/kvm/pmu-emul.c | 8 ++++---- arch/arm64/kvm/pmu.c | 5 +++-- include/kvm/arm_pmu.h | 3 ++- include/linux/perf/arm_pmuv3.h | 2 -- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index da5ba9d061e8..77fe79b2ba04 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -234,7 +234,7 @@ void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) int i; struct kvm_pmu *pmu =3D &vcpu->arch.pmu; =20 - for (i =3D 0; i < ARMV8_PMU_MAX_COUNTERS; i++) + for (i =3D 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) pmu->pmc[i].idx =3D i; } =20 @@ -261,7 +261,7 @@ void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) { int i; =20 - for (i =3D 0; i < ARMV8_PMU_MAX_COUNTERS; i++) + for (i =3D 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) kvm_pmu_release_perf_event(kvm_vcpu_idx_to_pmc(vcpu, i)); irq_work_sync(&vcpu->arch.pmu.overflow_work); } @@ -292,7 +292,7 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu,= u64 val) if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) || !val) return; =20 - for (i =3D 0; i < ARMV8_PMU_MAX_COUNTERS; i++) { + for (i =3D 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) { struct kvm_pmc *pmc; =20 if (!(val & BIT(i))) @@ -324,7 +324,7 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu= , u64 val) if (!kvm_vcpu_has_pmu(vcpu) || !val) return; =20 - for (i =3D 0; i < ARMV8_PMU_MAX_COUNTERS; i++) { + for (i =3D 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) { struct kvm_pmc *pmc; =20 if (!(val & BIT(i))) diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index 01c9a9efdd1c..7eaf5f7aeae9 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -5,6 +5,7 @@ */ #include #include +#include =20 #include =20 @@ -96,7 +97,7 @@ static void kvm_vcpu_pmu_enable_el0(unsigned long events) u64 typer; u32 counter; =20 - for_each_set_bit(counter, &events, 32) { + for_each_set_bit(counter, &events, ARMPMU_MAX_HWEVENTS) { typer =3D kvm_vcpu_pmu_read_evtype_direct(counter); typer &=3D ~ARMV8_PMU_EXCLUDE_EL0; kvm_vcpu_pmu_write_evtype_direct(counter, typer); @@ -111,7 +112,7 @@ static void kvm_vcpu_pmu_disable_el0(unsigned long even= ts) u64 typer; u32 counter; =20 - for_each_set_bit(counter, &events, 32) { + for_each_set_bit(counter, &events, ARMPMU_MAX_HWEVENTS) { typer =3D kvm_vcpu_pmu_read_evtype_direct(counter); typer |=3D ARMV8_PMU_EXCLUDE_EL0; kvm_vcpu_pmu_write_evtype_direct(counter, typer); diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 871067fb2616..e08aeec5d936 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -10,6 +10,7 @@ #include #include =20 +#define KVM_ARMV8_PMU_MAX_COUNTERS 32 =20 #if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM) struct kvm_pmc { @@ -25,7 +26,7 @@ struct kvm_pmu_events { struct kvm_pmu { struct irq_work overflow_work; struct kvm_pmu_events events; - struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS]; + struct kvm_pmc pmc[KVM_ARMV8_PMU_MAX_COUNTERS]; int irq_num; bool created; bool irq_level; diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index caa09241ad4f..c902fe64f070 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -6,8 +6,6 @@ #ifndef __PERF_ARM_PMUV3_H #define __PERF_ARM_PMUV3_H =20 -#define ARMV8_PMU_MAX_COUNTERS 32 - /* * Common architectural and microarchitectural event numbers. */ --=20 2.43.0 From nobody Thu Feb 12 19:05:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A2FC15667D; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SfEFfAJa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 63D92C4AF08; Fri, 7 Jun 2024 20:32:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792335; bh=KgRp/liFFW85v8ZYPjrAlhpw4VYmeoKaJTUjzgMXSH8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SfEFfAJakAM6y716aMbuLsXQ7hiXrXoRRlhuEJzKbSlZ+h/7iR0bxUl85iriTPTVf x34WZPWhQsUVyIylyXWZCIOTLTBsao46V3fJkG2vuoqgF/XAcpvduTqdaRgbyVpGfm kgziXenKnVLm0dX1XvZPR+jcJ69/G+/GdhTCycADrMxldsTSB5juejkkcsuoqFX1YR jI44DspO9vyxgizA1pfpmem3MgeRFS2G2+r1dItJ/qGNTmXbIeTEmuSkBtV/1Cv8xL IKIA3jXWvxjYA7pRLDQtU+N6HC3p/2PFljYLJ8qDFs6VTR/MfUePvaCJgHf81pSTPV pNHZJWU3pW/oA== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:34 -0600 Subject: [PATCH 9/9] perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240607-arm-pmu-3-9-icntr-v1-9-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev Armv9.4/8.9 PMU adds optional support for a fixed instruction counter similar to the fixed cycle counter. Support for the feature is indicated in the ID_AA64DFR1_EL1 register PMICNTR field. The counter is not accessible in AArch32. Existing userspace using direct counter access won't know how to handle the fixed instruction counter, so we have to avoid using the counter when user access is requested. Signed-off-by: Rob Herring (Arm) --- arch/arm/include/asm/arm_pmuv3.h | 21 +++++++++++++++++++++ arch/arm64/include/asm/arm_pmuv3.h | 29 +++++++++++++++++++++++++++++ arch/arm64/kvm/pmu.c | 8 ++++++-- arch/arm64/tools/sysreg | 25 +++++++++++++++++++++++++ drivers/perf/arm_pmuv3.c | 28 ++++++++++++++++++++++++++-- include/linux/perf/arm_pmu.h | 8 ++++++-- include/linux/perf/arm_pmuv3.h | 4 +++- 7 files changed, 116 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pm= uv3.h index ac2cf37b57e3..b836537ddfbf 100644 --- a/arch/arm/include/asm/arm_pmuv3.h +++ b/arch/arm/include/asm/arm_pmuv3.h @@ -10,6 +10,7 @@ #include =20 #define ARMV8_PMU_CYCLE_IDX 31 +#define ARMV8_PMU_INSTR_IDX 32 /* Not accessible from AArch32 */ =20 #define PMCCNTR __ACCESS_CP15_64(0, c9) =20 @@ -129,6 +130,12 @@ static inline u32 read_pmuver(void) return (dfr0 >> 24) & 0xf; } =20 +static inline bool pmuv3_has_icntr(void) +{ + /* FEAT_PMUv3_ICNTR not accessible for 32-bit */ + return false; +} + static inline void write_pmcr(u32 val) { write_sysreg(val, PMCR); @@ -154,6 +161,13 @@ static inline u64 read_pmccntr(void) return read_sysreg(PMCCNTR); } =20 +static inline void write_pmicntr(u64 val) {} + +static inline u64 read_pmicntr(void) +{ + return 0; +} + static inline void write_pmcntenset(u32 val) { write_sysreg(val, PMCNTENSET); @@ -179,6 +193,13 @@ static inline void write_pmccfiltr(u32 val) write_sysreg(val, PMCCFILTR); } =20 +static inline void write_pmicfiltr(u64 val) {} + +static inline u64 read_pmicfiltr(void) +{ + return 0; +} + static inline void write_pmovsclr(u32 val) { write_sysreg(val, PMOVSR); diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/ar= m_pmuv3.h index 46930729fb3f..a13a10e97c01 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -12,6 +12,7 @@ #include =20 #define ARMV8_PMU_CYCLE_IDX 31 +#define ARMV8_PMU_INSTR_IDX 32 =20 #define RETURN_READ_PMEVCNTRN(n) \ return read_sysreg(pmevcntr##n##_el0) @@ -56,6 +57,14 @@ static inline u32 read_pmuver(void) ID_AA64DFR0_EL1_PMUVer_SHIFT); } =20 +static inline bool pmuv3_has_icntr(void) +{ + u64 dfr1 =3D read_sysreg(id_aa64dfr1_el1); + + return !!cpuid_feature_extract_unsigned_field(dfr1, + ID_AA64DFR1_EL1_PMICNTR_SHIFT); +} + static inline void write_pmcr(u64 val) { write_sysreg(val, pmcr_el0); @@ -81,6 +90,16 @@ static inline u64 read_pmccntr(void) return read_sysreg(pmccntr_el0); } =20 +static inline void write_pmicntr(u64 val) +{ + write_sysreg_s(val, SYS_PMICNTR_EL0); +} + +static inline u64 read_pmicntr(void) +{ + return read_sysreg_s(SYS_PMICNTR_EL0); +} + static inline void write_pmcntenset(u64 val) { write_sysreg(val, pmcntenset_el0); @@ -111,6 +130,16 @@ static inline u64 read_pmccfiltr(void) return read_sysreg(pmccfiltr_el0); } =20 +static inline void write_pmicfiltr(u64 val) +{ + write_sysreg_s(val, SYS_PMICFILTR_EL0); +} + +static inline u64 read_pmicfiltr(void) +{ + return read_sysreg_s(SYS_PMICFILTR_EL0); +} + static inline void write_pmovsclr(u64 val) { write_sysreg(val, pmovsclr_el0); diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index 7eaf5f7aeae9..9420835cce91 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -67,24 +67,28 @@ void kvm_clr_pmu_events(u64 clr) =20 /* * Read a value direct from PMEVTYPER where idx is 0-30 - * or PMCCFILTR_EL0 where idx is ARMV8_PMU_CYCLE_IDX (31). + * or PMxCFILTR_EL0 where idx is 31-32. */ static u64 kvm_vcpu_pmu_read_evtype_direct(int idx) { if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) return read_pmccfiltr(); + else if (idx =3D=3D ARMV8_PMU_INSTR_IDX) + return read_pmicfiltr(); =20 return read_pmevtypern(idx); } =20 /* * Write a value direct to PMEVTYPER where idx is 0-30 - * or PMCCFILTR_EL0 where idx is ARMV8_PMU_CYCLE_IDX (31). + * or PMxCFILTR_EL0 where idx is 31-32. */ static void kvm_vcpu_pmu_write_evtype_direct(int idx, u32 val) { if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) write_pmccfiltr(val); + else if (idx =3D=3D ARMV8_PMU_INSTR_IDX) + write_pmicfiltr(val); else write_pmevtypern(idx, val); } diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 231817a379b5..8ab6e09871de 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2029,6 +2029,31 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg =20 +Sysreg PMICNTR_EL0 3 3 9 4 0 +Field 63:0 ICNT +EndSysreg + +Sysreg PMICFILTR_EL0 3 3 9 6 0 +Res0 63:59 +Field 58 SYNC +Field 57:56 VS +Res0 55:32 +Field 31 P +Field 30 U +Field 29 NSK +Field 28 NSU +Field 27 NSH +Field 26 M +Res0 25 +Field 24 SH +Field 23 T +Field 22 RLK +Field 21 RLU +Field 20 RLH +Res0 19:16 +Field 15:0 evtCount +EndSysreg + Sysreg PMSCR_EL1 3 0 9 9 0 Res0 63:8 Field 7:6 PCT diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 468a0a3bbd5a..890efc686e11 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -479,7 +479,7 @@ static bool armv8pmu_event_is_chained(struct perf_event= *event) return !armv8pmu_event_has_user_read(event) && armv8pmu_event_is_64bit(event) && !armv8pmu_has_long_event(cpu_pmu) && - (idx !=3D ARMV8_PMU_CYCLE_IDX); + (idx < ARMV8_PMU_CYCLE_IDX); } =20 /* @@ -538,7 +538,7 @@ static bool armv8pmu_event_needs_bias(struct perf_event= *event) return false; =20 if (armv8pmu_has_long_event(cpu_pmu) || - idx =3D=3D ARMV8_PMU_CYCLE_IDX) + idx >=3D ARMV8_PMU_CYCLE_IDX) return true; =20 return false; @@ -568,6 +568,8 @@ static u64 armv8pmu_read_counter(struct perf_event *eve= nt) =20 if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) value =3D read_pmccntr(); + else if (idx =3D=3D ARMV8_PMU_INSTR_IDX) + value =3D read_pmicntr(); else value =3D armv8pmu_read_hw_counter(event); =20 @@ -601,6 +603,8 @@ static void armv8pmu_write_counter(struct perf_event *e= vent, u64 value) =20 if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) write_pmccntr(value); + else if (idx =3D=3D ARMV8_PMU_INSTR_IDX) + write_pmicntr(value); else armv8pmu_write_hw_counter(event, value); } @@ -638,6 +642,8 @@ static void armv8pmu_write_event_type(struct perf_event= *event) } else { if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) write_pmccfiltr(hwc->config_base); + else if (idx =3D=3D ARMV8_PMU_INSTR_IDX) + write_pmicfiltr(hwc->config_base); else armv8pmu_write_evtype(idx, hwc->config_base); } @@ -765,6 +771,8 @@ static void armv8pmu_enable_user_access(struct arm_pmu = *cpu_pmu) for_each_clear_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { if (i =3D=3D ARMV8_PMU_CYCLE_IDX) write_pmccntr(0); + else if (i =3D=3D ARMV8_PMU_INSTR_IDX) + write_pmicntr(0); else armv8pmu_write_evcntr(i, 0); } @@ -931,6 +939,18 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events= *cpuc, return -EAGAIN; } =20 + /* + * Always prefer to place a instruction counter into the instruction coun= ter, + * but don't expose the instruction counter to userspace access as usersp= ace + * may not know how to handle it. + */ + if (test_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask) && + (evtype =3D=3D ARMV8_PMUV3_PERFCTR_INST_RETIRED) && + !armv8pmu_event_want_user_access(event)) { + if (!test_and_set_bit(ARMV8_PMU_INSTR_IDX, cpuc->used_mask)) + return ARMV8_PMU_INSTR_IDX; + } + /* * Otherwise use events counters */ @@ -1188,6 +1208,10 @@ static void __armv8pmu_probe_pmu(void *info) /* Add the CPU cycles counter */ bitmap_set(cpu_pmu->cntr_mask, ARMV8_PMU_CYCLE_IDX, 1); =20 + /* Add the CPU instructions counter */ + if (pmuv3_has_icntr()) + bitmap_set(cpu_pmu->cntr_mask, ARMV8_PMU_INSTR_IDX, 1); + pmceid[0] =3D pmceid_raw[0] =3D read_pmceid0(); pmceid[1] =3D pmceid_raw[1] =3D read_pmceid1(); =20 diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index e5d6d204beab..4b5b83677e3f 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -17,10 +17,14 @@ #ifdef CONFIG_ARM_PMU =20 /* - * The ARMv7 CPU PMU supports up to 32 event counters. + * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters. + * The Armv8.9/9.4 CPU PMU supports up to 33 event counters. */ +#ifdef CONFIG_ARM #define ARMPMU_MAX_HWEVENTS 32 - +#else +#define ARMPMU_MAX_HWEVENTS 33 +#endif /* * ARM PMU hw_event flags */ diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index c902fe64f070..0472c4270d66 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -224,8 +224,10 @@ */ #define ARMV8_PMU_OVSR_P GENMASK(30, 0) #define ARMV8_PMU_OVSR_C BIT(31) +#define ARMV8_PMU_OVSR_F BIT_ULL(32) /* arm64 only */ /* Mask for writable bits is both P and C fields */ -#define ARMV8_PMU_OVERFLOWED_MASK (ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C) +#define ARMV8_PMU_OVERFLOWED_MASK (ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C | \ + ARMV8_PMU_OVSR_F) =20 /* * PMXEVTYPER: Event selection reg --=20 2.43.0