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Signed-off-by: Srinivas Kandagatla --- .../qcom,sm4250-lpass-lpi-pinctrl.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm4250-l= pass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpas= s-lpi-pinctrl.yaml new file mode 100644 index 000000000000..3968a363aa51 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinct= rl.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM4250 SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC. + +properties: + compatible: + const: qcom,sm4250-lpass-lpi-pinctrl + + reg: + maxItems: 2 + + clocks: + items: + - description: LPASS Audio voting clock + + clock-names: + items: + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm4250-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm4250-lpass-state" + additionalProperties: false + +$defs: + qcom-sm4250-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|1[0-8])$" + minItems: 1 + maxItems: 19 + + function: + enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, + dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1= _a, + ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws, + i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, + qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_= data, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_= clk, + swr_wsa_data ] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + lpi_tlmm: pinctrl@a7c0000 { + compatible =3D "qcom,sm4250-lpass-lpi-pinctrl"; + reg =3D <0xa7c0000 0x20000>, + <0xa950000 0x10000>; + clocks =3D <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUP= LE_NO>; + clock-names =3D "audio"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpi_tlmm 0 0 19>; + + i2s2-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "i2s2_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio12"; + function =3D "i2s2_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + }; + }; + + i2s2-sleep-clk-state { + pins =3D "gpio10"; + function =3D "i2s2_clk"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; --=20 2.25.1 From nobody Thu Feb 12 21:46:51 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60761195F0F for ; Thu, 6 Jun 2024 13:04:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 06 Jun 2024 06:04:11 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35ef5d49dfcsm1505286f8f.39.2024.06.06.06.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:04:10 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: andersson@kernel.org, linus.walleij@linaro.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, srinivas.kandagatla@linaro.org, linux-arm-msm@vger.kernel.org, inux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] pinctrl: qcom: Introduce SM4250 LPI pinctrl driver Date: Thu, 6 Jun 2024 14:03:23 +0100 Message-Id: <20240606130323.138970-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240606130323.138970-1-srinivas.kandagatla@linaro.org> References: <20240606130323.138970-1-srinivas.kandagatla@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Srinivas Kandagatla Add support for the pin controller block on SM4250 Low Power Island. Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 191 ++++++++++++++++++ 3 files changed, 201 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 24619e80b2cc..dd9bbe8f3e11 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platfo= rm. =20 +config PINCTRL_SM4250_LPASS_LPI + tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller drive= r" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platfo= rm. + config PINCTRL_SM6115_LPASS_LPI tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index e2e76071d268..eb04297b6388 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SDM845) +=3D pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) +=3D pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) +=3D pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) +=3D pinctrl-sdx75.o +obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) +=3D pinctrl-sm4250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM4450) +=3D pinctrl-sm4450.o obj-$(CONFIG_PINCTRL_SM6115) +=3D pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) +=3D pinctrl-sm6115-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm4250-lpass-lpi.c new file mode 100644 index 000000000000..6c5d09241e82 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_ext_mclk0_a, + LPI_MUX_ext_mclk0_b, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_slim_clk, + LPI_MUX_slim_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_swr_wsa_clk, + LPI_MUX_swr_wsa_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sm4250_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const dmic01_clk_groups[] =3D { "gpio6" }; +static const char * const dmic01_data_groups[] =3D { "gpio7" }; +static const char * const dmic23_clk_groups[] =3D { "gpio8" }; +static const char * const dmic23_data_groups[] =3D { "gpio9" }; +static const char * const dmic4_clk_groups[] =3D { "gpio10" }; +static const char * const dmic4_data_groups[] =3D { "gpio11" }; +static const char * const ext_mclk0_a_groups[] =3D { "gpio13" }; +static const char * const ext_mclk0_b_groups[] =3D { "gpio5" }; +static const char * const ext_mclk1_a_groups[] =3D { "gpio18" }; +static const char * const ext_mclk1_b_groups[] =3D { "gpio9" }; +static const char * const ext_mclk1_c_groups[] =3D { "gpio17" }; +static const char * const slim_clk_groups[] =3D { "gpio14" }; +static const char * const slim_data_groups[] =3D { "gpio15" }; +static const char * const i2s1_clk_groups[] =3D { "gpio6" }; +static const char * const i2s1_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] =3D { "gpio7" }; +static const char * const i2s2_clk_groups[] =3D { "gpio10" }; +static const char * const i2s2_data_groups[] =3D { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] =3D { "gpio11" }; +static const char * const i2s3_clk_groups[] =3D { "gpio14" }; +static const char * const i2s3_data_groups[] =3D { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] =3D { "gpio15" }; +static const char * const qua_mi2s_data_groups[] =3D { "gpio2", "gpio3", "= gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] =3D { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] =3D { "gpio1" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2" }; +static const char * const swr_wsa_clk_groups[] =3D { "gpio10" }; +static const char * const swr_wsa_data_groups[] =3D { "gpio11" }; + + +static const struct lpi_pingroup sm4250_groups[] =3D { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk0_b, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, i2s2_clk, swr_wsa_clk, dmic4_clk, _), + LPI_PINGROUP(11, 18, i2s2_ws, swr_wsa_data, dmic4_data, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic23_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic23_data, i2s2_data, ext_mclk0_a, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, slim_clk, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, slim_data, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, ext_mclk1_c, _, _), + LPI_PINGROUP(18, 20, ext_mclk1_a, swr_rx_data, _, _), +}; + +static const struct lpi_function sm4250_functions[] =3D { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(ext_mclk0_a), + LPI_FUNCTION(ext_mclk0_b), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(slim_clk), + LPI_FUNCTION(slim_data), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(swr_wsa_clk), + LPI_FUNCTION(swr_wsa_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_a), +}; + +static const struct lpi_pinctrl_variant_data sm4250_lpi_data =3D { + .pins =3D sm4250_lpi_pins, + .npins =3D ARRAY_SIZE(sm4250_lpi_pins), + .groups =3D sm4250_groups, + .ngroups =3D ARRAY_SIZE(sm4250_groups), + .functions =3D sm4250_functions, + .nfunctions =3D ARRAY_SIZE(sm4250_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { .compatible =3D "qcom,sm4250-lpass-lpi-pinctrl", .data =3D &sm4250_lpi_= data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sm4250-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove_new =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM4250 LPI GPIO pin control driver"); +MODULE_AUTHOR("Srinivas Kandagatla "); +MODULE_LICENSE("GPL"); --=20 2.25.1